TiN Gate Electrode Research Articles

Analog Performance of SOI nFinFETs with Different TiN Gate Electrode Thickness

This work presents an analysis of the analog performance of SOI FinFET devices and the impact of different TiN metal gate electrode thickness. Thinner TiN metal gate allows achieving large gain in spite of the reduced variation observed on gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA enhance suggests an increase of the transversal electrical field for thin TiN metal gate (reduced effective oxide thickness - EOT) that is confirmed with the increment of the GIDL current. This impact on the voltage gain is maintained for short channel length.

Nanoscale p-MOS Thin-Film Transistor With TiN Gate Electrode Fabricated by Low-Temperature Microwave Dopant Activation

In this letter, nanoscale p-MOS TFTs with a TiN gate electrode were realized using a novel microwave (MW) dopant-activation technique. We compared both low-temperature MW annealing and rapid thermal annealing. We successfully activated the source/drain region and suppressed the short-channel effects using low-temperature MW annealing. This technique is promising from the viewpoint of realizing high-performance and low-cost upper layer nanoscale transistors required for low-temperature 3-D integrated circuit fabrication.

Oxygen migration in TiO2-based higher-k gate stacks

We report on the stability of high-permittivity (high-k) TiO2 films incorporated in metal-oxide-silicon capacitor structures with a TiN metal gate electrode, focusing on oxygen migration. Titanium oxide films are deposited by either Ti sputtering [physical vapor deposition (PVD)] followed by radical shower oxidation or by plasma-enhanced atomic layer deposition (PEALD) from titanium isopropoxide (Ti{OCH(CH3)2}4) and O2 plasma. Both PVD and PEALD films result in near-stoichiometric TiO2 prior to high-temperature annealing. We find that dopant activation anneals of TiO2-containing gate stacks at 1000 °C cause 5 Å or more of additional SiO2 to be formed at the gate-dielectric/Si-channel interface. Furthermore, we demonstrate for the first time that oxygen released from TiO2 diffuses through the TiN gate electrode and oxidizes the poly-Si contact. The thickness of this upper SiO2 layer continues to increase with increasing TiO2 thickness, while the thickness of the regrown SiO2 at the gate-dielectric/Si interface saturates. The upper SiO2 layer degrades gate stack capacitance, and simultaneously the oxygen-deficient TiOx becomes a poor insulator. In an attempt to mitigate O loss from the TiO2, top and bottom Al2O3 layers are added to the TiO2 gate dielectric as oxygen barriers. However, they are found to be ineffective, due to Al2O3-TiO2 interdiffusion during activation annealing. Bottom HfO2/Si3N4 interlayers are found to serve as more effective oxygen barriers, reducing, though not preventing, oxygen downdiffusion.

Analysis of the Interface Trap Density in SOI FinFETs with Different TiN Gate Electrode Thickness through Charge Pumping Technique

This work presents the analysis of the interface trap density in triple-gate silicon-on-insulator FinFET gated-diode structures with different TiN gate electrode thickness and fin widths by using the charge pumping technique. It is shown that a thicker metal gate corresponds with more traps. The fin width comparison shows that narrow fin devices exhibit a higher interface trap density due to the (110) sidewall contribution.

Vestiges of Multiple Progressive Dielectric Breakdown on HfSiON Surfaces

We have developed a new technique with conductive atomic force microscopy (CAFM) to define the position of dielectric breakdown spots in HfSiON dielectrics. It was demonstrated that, after the removal of TiN gate electrodes, dielectric breakdown spots in HfSiON were detected as protrusions, which were observed as leakage spots by CAFM. It was also shown that there is good correlation between the number of dielectric breakdown spots estimated by time-dependent leakage current analysis and the number of protrusions obtained by CAFM analysis. Furthermore, from the etching characteristics of dielectric breakdown spots obtained using diluted HF, it was revealed that the transformation of HfSiON dielectrics occured at protrusions. We concluded that the local crystallization of HfSiON occured at the dielectric breakdown spots.

Performance improvement in narrow MuGFETs by gate work function and source/drain implant engineering

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1,2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage ( V T) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width ( W fin) and gate length ( L g) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance ( R SD) engineering become more challenging. In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial R SD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 nm.

Effect of Annealing on Electronic Characteristics of HfSiON Films fabricated by Damascene Gate Process

The conduction mechanism of HfSiON stacked-gate dielectric films after a spike annealing is investigated. FETs fabricated using the Damascene process is used to evaluate the electronic characteristics of a stacked-gate dielectric film. The effect of an additional spike annealing after the TiN gate electrode fabrication on the conductivity is analyzed. The electron current over the entire range of gate voltage is increased, while the hole current remains unchanged. The TAT and Schottky analyses derive a consistent energy level of the intermediate trap centers contributing to the electron conduction. The average lifetime is improved by annealing. However, the spike annealing does not change the slope of the TDDB Weibull plots. The average lifetime is improved by annealing. From NBTI analyses, the threshold voltages displayed linearly shifts with increasing injection charge concentration, both with and without the spike annealing. The slope of the threshold voltage shift is defined as a degradation rate.

Methodology for Flatband Voltage Measurement in Fully Depleted Floating-Body FinFETs

Among the novel methods for flatband voltage (Vfb) measurement, we demonstrate that a gate-leakage-based technique is the most suitable for measuring Vfb in floating-body MOSFETs with ultrathin gate dielectrics. Starting from carrier separation experiments on planar MOSFETs, we show the universality of the gate conduction mechanism dependence on band alignment for both n- and p-FETs. We demonstrate that metrics based on the gate leakage (either its valence-band electron-tunneling component or its first-order derivative) reflect this dependence and allow equivalent-oxide-thickness-independent Vfb quantification. This dependence is also valid for high-k and capped gate dielectrics, whereas their gate conduction mechanism is dominated by direct tunneling. To illustrate, we extract gate-leakage-derivative-based metrics and measure Vfb of TaN and TiN gate electrodes in multiple-fin FETs integrated on silicon-on-insulator.

Tight Distribution of Dielectric Characteristics of HfSiON in Metal Gate Devices

Leakage current characteristics with significantly reduced dispersion were achieved for HfSiON gate dielectric film by selecting TiN gate electrode with low reactivity, compared to the conventional poly-Si gate. The breakdown lifetime and its characteristic homogeneity were also enormously improved. With intensive study on these electrical characteristics, it was concluded that the concentration of oxygen vacancy was significantly reduced, giving rise to the homogeneity improvement. Moreover, we have shown an explanation for the dielectric breakdown in terms of oxygen transport in the Hf-based dielectric film.

Low Temperature Chatacterization of High-k Dielectric Metal Gate FD-SOI nMOSFETs

Fully Depleted devices with HfO2 dielectric and TiN gate electrode have been studied at different temperatures. Noise measurements have also been carried out on these devices. The effects specific to short channels are evidenced and studied. The precise doping density of the silicon film has also been calculated.

Sub 2 nm Thick Zirconium Doped Hafnium Oxide High-K Gate Dielectrics

Zr-doped HfOx high-k gate dielectric films with TiN gate electrode were sputter deposited on 1 nm SiO2 or SiOxNy interface layer. Electrical properties including the equivalent oxide thickness, flat band voltage, interface state density, and the oxide charge trapped density of the MOS capacitors were investigated with respect to fabrication parameters such as Zr doping condition, post deposition annealing ambient, and type of bottom interface layer. Excellent electrical properties were obtained for films deposited at low sputtering powers. An equivalent oxide thickness of 1.7 nm was achieved for Zr-doped HfOx on a 1 nm SiO2 interface. The leakage current is four orders of magnitude lower than that of the SiO2 film. The magnitude and polarity of the flat band voltage is influenced by the high-k film deposition method, the dopant concentration, and the post deposition annealing condition. With the same SiOxNy interface layer, the Zr-doped film has a lower leakage current and a smaller interface density of states than the undoped film.

Thermal Degradation of HfSiON Dielectrics Caused by TiN Gate Electrodes and Its Impact on Electrical Properties

We studied thermal reactions in TiN/HfSiON gate stacks and discussed their impact on electrical properties. Physical analysis revealed that reactions at the metal/high-k interface form a polycrystalline TiO2 layer at 700 °C. The interface between the TiN electrode and the ultrathin TiO2 interlayer remained smooth and the formation of this high-permittivity metal oxide layer did not cause any electrical degradation in terms of equivalent oxide thickness (EOT) versus gate leakage (Ig) characteristics. However, interface roughness and electrical degradation, such as increases in electrical thickness and interface-trap density, were present after annealing at 900 °C. At 1100 °C, we observed marked increases in EOT and Ig, which respectively indicated oxide (SiO2) growth at the bottom interface and dielectric degradation both of the interface TiO2 and HfSiON layers.

Effects of Low-temperature NH3 Treatment on the Characteristics of HfO2 ∕ SiO2 Gate Stack

The effects of postdeposition low-temperature treatment (LTN treatment) on the characteristics of the gate stack with the TiN gate electrode were studied in this work. After the films were deposited using an AIXTRON Tricent atomic vapor deposition system, the LTN treatment was performed prior to the postdeposition annealing (PDA) step to prevent the growth of an additional interfacial layer, which is known to accompany the traditional high-temperature nitridation technique. The effective electrical oxide thickness for the devices annealed at 700°C PDA, either with or without LTN treatment, was estimated to be about 2.2 and 2.3 nm, respectively, without considering quantum effects. It was found that the LTN treatment effectively improves the characteristics of the stack gates, such as capacitance-voltage characteristics, frequency dispersion, trap generation rate, and dielectric breakdown voltage even at the high PDA temperature of 700°C.

Physical comparison of HfO2 transistors with polycrystalline silicon and TiN electrodes

Transistor gate stack systems consisting of atomic layer deposited HfO2 with polycrystalline silicon or TiN gate electrodes have been characterized by analytical electron microscopy to elucidate underlying physical contributions to electrical performance differences. High-angle annular dark-field scanning transmission electron microscopy was used to determine film and interface thickness dimensions and chemical analysis depth profiling was obtained from electron energy loss spectra and energy dispersive x-ray spectra. The high-k gate dielectric film system is shown to be influenced by the choice of electrode material with the formation of an HfO2-poly-Si interface that increases the dielectric equivalent oxide thickness and may affect electron trapping characteristics.

Temperature Effects of Constant Bias Stress on n-Channel FETs with Hf-based Gate Dielectric

Temperature dependence of degradation and breakdown behavior of hafnium silicate gate dielectrics in n-channel field-effect transistors (NFET) with polysilicon and TiN gate electrodes has been investigated. At elevated temperatures under positive gate bias, devices with polysilicon gate electrodes exhibit a so-called Vth turn around phenomenon (a change of the direction of the Vth shift from positive to negative), accompanied by decreasing transconductance and increasing gate leakage current. Hot-holes generation in the poly-Si gate by the injected electrons and a subsequent hole diffusion and trapping near the high-k/Si-substrate interface is proposed to contribute to the turn around behavior. No Vth turn around phenomenon was observed in devices with the TiN gate electrode. This hole induced degradation of the high-k/poly-Si gate stack may further complicate integration of the polysilicon gate electrode with high-k dielectrics.

Trapping/De-Trapping Gate Bias Dependence of Hf-Silicate Dielectrics with Poly and TiN Gate Electrode

Constant voltage stress induced Vth shift and its detrapping characteristics under the negative gate bias has been extensively investigated with HF-silicate dielectrics with poly and TiN gate electrode. The threshold voltage shift in negative-channel metal-oxide semiconductor (NMOS) transistors under the positive gate bias stress is found to be associated mostly with the reversible electron trapping. A proper negative bias can be used to de-trap the electrons accumulated during the positive stress. However, an aggressive de-trapping can cause an additional Vth instability due to the excessive de-trapping of existing charge or additional hole trapping at the interface with poly gate. TiN metal gate is found to be more stable with de-trapping negative gate bias. To de-trap the electrons accumulated in the dielectric during the positive constant voltage stress (CVS), the negative bias and its duration should be chosen very carefully to avoid the additional charging associated with the hole trapping.

The characteristics of hole trapping in HfO2∕SiO2 gate dielectrics with TiN gate electrode

The characteristics of charge trapping during constant voltage stress in an n-type metal–oxide–semiconductor capacitor with HfO2∕SiO2 gate stack and TiN gate electrode were studied. We found that the dominant charge trapping mechanism in the high-k gate stack is hole trapping rather than electron trapping. This behavior can be well described by the distributed capture cross-section model. In particular, the flatband voltage shift (ΔVfb) is mainly caused by the trap filling instead of the trap creation [Zafar et al., J. Appl. Phys. 93, 9298 (2003)]. The dominant hole trapping can be ascribed to a higher probability for hole tunneling from the substrate, compared to electron tunneling from the gate, due to a shorter tunneling path over the barrier for holes due to the work function of the TiN gate electrode.

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO 2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high- k gate dielectric transistors were investigated. The performance of O 3 vs. HF-last/NH 3 pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO 2 gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high- k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO 2 microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO 2/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high- k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.

Stress induced charge trapping effects in SiO2/Al2O3 gate stacks with TiN electrodes

Strong polarity dependent charge trapping effects have been observed in as-deposited SiO2/Al2O3 gate stacks with TiN gate electrodes on n- and p-type Si substrates using current–voltage (I–V) and capacitance–voltage (C–V) sensing techniques. For substrate injection, electron trapping occurs mainly in the bulk of the Al2O3, resulting in positive voltage shifts for both I–V and C–V measurements. In the case of gate injection, positive charge trapping near the SiO2/Al2O3 interface leads to negative voltage shifts for C–V and positive shifts for I–V measurements. The polarity dependent charging effects are explained in terms of the difference in barrier height for substrate and gate injection and of the inherent asymmetry of the dual layer gate dielectric.

Growth and effects of remote-plasma oxidation on thin films of HfO2 prepared by metal-organic chemical-vapor deposition

The metal-organic (MO) chemical vapor deposition of hafnium oxide (HfO2) films from a new MO precursor, Hf(OC(CH3)2CH2OCH3)4, was investigated. The deposition rate of HfO2 is higher when oxygen gas is being supplied with the precursor. However, films deposited in the presence of added oxygen contain large amounts of H2O due to oxidation of the Hf precursor. O2 addition process degraded HfO2 film properties. In situ remote-plasma oxidation (RPO) is found to be effective in reducing the contaminants in HfO2. Leakage current in HfO2/Si capacitors with TiN gate electrode is also shown to be lower when deposition is without the oxygen addition and RPO treatment is subsequently performed.