Time-to-digital Converter Research Articles

Transfer-Path-Based Hardware-Reuse Strong PUF Achieving Modeling Attack Resilience With200 Million Training CRPs

This paper presents a hardware-reuse strong physical unclonable function (PUF) based on the intrinsic transfer paths (TPs) of a conventional digital multiplier to achieve a strong modeling attack resilience. With the multiplier input employed as the PUF challenge and the path delay as the entropy source, all the possible valid propagation paths from distinct input/output pairs can serve as PUF primitives. We can quantize the path delay using a time-to-digital converter (TDC), and select the suitable TDC output bits as the PUF response. We further propose a lightweight dynamic obfuscation algorithm (DOA) and a secure mutual authentication protocol to counteract modeling attacks. The proposed strong PUF using a 32×32 multiplier as implemented in the Xilinx ZYNQ-7000 SoC features a total of 2048 intrinsic PUF primitives, while achieving a response stream (RS) with an average of 1024 responses per TDC output bit per challenge. With <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bit</i> (5) and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bit</i> (6) of the TDC output selected for PUF response generation, they demonstrate a measured reliability and uniqueness of up to 98.31% and 49.34%, respectively, with their excellent randomness performance as validated by the NIST SP800-22 tests. Under machine learning (ML)-based modeling attack with artificial neural network (ANN), the measured prediction accuracy of both <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bit</i> (5) and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Bit</i> (6) can still be maintained at ~50% with a total of >200 million CRPs as the training set.

3-D Raman Imaging Using Time-Resolving CMOS SPAD Line Sensor and 2-D Mapping

The capability of Raman imaging to produce 2D and 3D chemical presentations of samples has gained a lot of interest in different application fields. In this paper, we present a 3D chemical image reconstruction based on 2D scanning of a sample utilizing a time-resolved Raman spectrometer based on a CMOS single-photon avalanche diode (SPAD) line sensor. The 2D scanning data contains the lateral information (XY-plane) whereas the time-of-arrival data of the Raman photons measured by the sensor carries the axial information (i.e., depth information, Z-axis). The sensor is fabricated in 110-nm CMOS technology. It has 256-spectral channels and each channel has its own 7-bit on-chip time-to-digital converter (TDC) with an adjustable resolution from 25 ps to 65 ps. In addition to the 3D chemical reconstruction of the scanned sample, we have also shown the ability to retrieve depth profiling information of each scanned pixel such as the boundaries and middle points of any selected layer over the depth range of the scanned object by means of a single measurement for each scanned pixel. In addition, we have discussed the system components and the post-processing parameters that affect the depth profiling accuracy and the 3D reconstruction operation the most. Results showed that the instrument response function of the system and the time gate window width in a post-processing phase are playing the most important role in determining the axial (depth) accuracy. We believe that our system will enable a whole new class of Raman applications that will allow simultaneous 3D chemical geometric representation at the cm-level during Raman operations.

Voltage Sensor Implementations for Remote Power Attacks on FPGAs

This article presents a study of two types of on-chip FPGA voltage sensors based on ring oscillators (ROs) and time-to-digital converter (TDCs), respectively. It has previously been shown that these sensors are often used to extract side-channel information from FPGAs without physical access. The performance of the sensors is evaluated in the presence of circuits that deliberately waste power, resulting in localized voltage drops. The effects of FPGA power supply features and sensor sensitivity in detecting voltage drops in an FPGA power distribution network (PDN) are evaluated for Xilinx Artix-7, Zynq 7000, and Zynq UltraScale+ FPGAs. We show that both sensor types are able to detect supply voltage drops, and that their measurements are consistent with each other. Our findings show that TDC-based sensors are more sensitive and can detect voltage drops that are shorter in duration, while RO sensors are easier to implement because calibration is not required. Furthermore, we present a new time-interleaved TDC design that sweeps the sensor phase. The new sensor generates data that can reconstruct voltage transients on the order of tens of picoseconds.

High-resolution time-to-digital converters (TDCs) with a bidirectional encoder

A high-resolution time-to-digital converter (TDC) based on wave union (four-edge WU A), dual-sampling, and sub-TDL methods is proposed and implemented in a 16-nm Xilinx UltraScale + field-programmable gate array (FPGA). We combine WU and dual-sampling techniques to achieve a high resolution. Besides, we use the sub-TDL method and the proposed bidirectional encoder to suppress bubbles and encode four-transition pseudo thermometer codes efficiently. Experimental results indicate the proposed TDC achieves a 0.4 ps resolution with a 450 MHz sampling clock and a less than 9 ps RMS precision from 0 ns to 100 ns (achieving a 3.06 ps RMS precision in the best-case scenario). These characteristics make this design suitable for particle physics, biomedical imaging (such as positron emission tomography, PET), and general-purpose scientific instruments.

DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs

Digital-to-time converter (DTC) based quantization noise cancellation (QNC) has recently been shown to enable excellent fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLL performance, but it requires a highly-linear DTC. Known DTC linearization strategies include analog-domain techniques which involve performance tradeoffs and digital predistortion techniques which converge slowly relative to typical required PLL settling times. Alternatively, a DTC implemented as a cascade of 1-bit DTC stages can be made highly linear without special techniques, but such DTCs typically introduce excessive error from component mismatches which has so far hindered their use in low-jitter PLLs. This paper presents a background calibration technique that addresses this issue by adaptively canceling error from DTC component mismatches. The technique is entirely digital, is compatible with a large class of digital fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> PLLs, and has at least an order of magnitude lower convergence time than the above-mentioned predistortion techniques. The paper presents a rigorous theoretical analysis closely supported by simulation results which quantifies the calibration technique’s convergence time and noise performance.

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter

Time-to-Digital Converters (TDCs) are major components for the measurements of time intervals. Recent developments in Field-Programmable Gate Array (FPGA) have enabled the opportunity to implement high-performance TDCs, which were only possible using dedicated hardware. In order to eliminate empty histogram bins and achieve a higher level of linearity, FPGA-based TDCs typically apply compensation methods either using multiple delay lines consuming more resources or post-processing, leading to a permanent loss of temporal information. We propose a novel TDC with a single delay line and without compensation to realize a highly linear TDC by encoding the states of the delay lines instead of the thermometer code used in the conventional TDCs. The experimental results show our states-based approach achieves an improved Differential Non-Linearity (DNL) of [-0.998, -1.533] for time resolution of 5.00 ps, [-0.44,0.49] for 10.04 ps, [-0.16, 0.19] for 21.65 ps, [-0.10, 0.11] for 43.87 ps, [-0.06, 0.07] for 64.12 ps, and [-0.07, 0.05] for 87.73 ps, whilst no empty bins have been observed. To our knowledge, the achieved raw linearity together with the zero empty bins and a simple delay line structure exceeds previously reported of the FPGA-based TDCs.

A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR

This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> HV-CMOS technology in a 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times32$ </tex-math></inline-formula> array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.

A 10-GS/s 8-bit 2850-μm2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC

This article presents an 8-bit time-domain analog-to-digital converter (ADC) achieving ten-GS/s conversion speed with only two time-interleaved (TI) channels. A successive approximation register (SAR) time-to-digital converter (TDC) is implemented for the subpicosecond resolution time quantization with high power/area efficiency and low jitter. The throughput of the SAR TDC is enhanced by a unique delay-tracking pipelining technique to enable a 5-GS/s single-channel conversion. On the circuit level, the reference time generation for the SAR TDC is realized by the proposed selective delay tuning (SDT) cell for high efficiency and small reference time variation. Fabricated in the 14-nm FinFet CMOS technology, this ADC achieves a 37.2-dB signal-to-noise and distortion ratio (SNDR) and a 50.6-dB spurious-free dynamic range (SFDR) at the Nyquist input frequency, leading to a 24.8-fJ/conv-step Walden figure of merit with an active area of only 2850 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> .

A Novel 12-Bit 0.6-mW Two-Step Coarse-Fine Time-to-Digital Converter

A novel two-step coarse-fine time-to-digital converter (TDC) is fabricated in 65-nm CMOS, with a relaxation oscillator based peak counter (ROC) for the coarse stage and a successive approximation analog-to-digital converter (SAR-ADC) for the fine stage. A reconfigurable 3-bit digital counter expands the dynamic range, and a high-precision 9-bit SAR-ADC ensures the resolution. The proposed ROC-ADC scheme conducts the time residence and the transfer linearity well for two-step quantization. Experimental results show that the presented 12-bit TDC achieves a high resolution less than 8 ps and a wide dynamic range up to 30 ns, with the differential nonlinearity (DNL) and integral nonlinearity (INL) values of 0.92 LSB and 1.07 LSB, respectively. The TDC consumes a low power of 0.6 mW from a 1-V supply, with the active area of 0.14 mm2.

A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

This work presents a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> ring-oscillator (RO)-based digital phase-locked loop (DPLL). To achieve ultralow jitter, the proposed RO-DPLL used a technique to reduce the dominant source of in-band noise, i.e., the thermal noise of the digital-to-time converters (DTCs). A key building block of this technique is the quadruple-timing-margin phase selector (QTM-PS) that dynamically selects the proper phase among the eight phases of the RO, effectively reducing the required dynamic range of the DTCs and, thus, suppressing the thermal noise significantly. Based on the reduced in-band noise, the dual-edge generator (DEG) doubles the bandwidth of the DPLL, further suppressing the jitter of the RO. The integrated background calibrator (IBC) that can perform multiple least mean squares (LMS)-based calibrations was used to guarantee the stable operation and performance of both the QTM-PS and the DEG. The proposed RO-DPLL was fabricated in 65-nm CMOS, and it used 0.139-mm2 silicon area and 15.67-mW power. At a fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> frequency near 5.2 GHz, the rms jitter and the figure of merit (FoM) of the output signal were 188 fs and–243 dB, respectively.

Multievent Histogramming TDC With Pre–Post Weighted Histogramming Filter for CMOS LiDAR Sensors

In this study, we have proposed a CMOS light detection and ranging (LiDAR) sensor with high immunity for background noise (BGN) and inter-LiDAR interference (IF). To mitigate pileup distortions that cause signal loss due to large BGN, we implemented multievent weighted histogramming time-to-digital converter (TDC) with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times4$ </tex-math></inline-formula> macro-pixels. The 11-bit two-step TDC and mixed-signal accumulator (MA) were utilized to implement histogramming with area efficiency. To overcome the limited dynamic range of histogram accumulation while preserving the maximum detectable range (MDR), a pre–post weighted histogram filter was implemented to detect only time-correlated time-of-flight (TOF) out of BGN from both sunlight and increased dark noise while enhancing sensitivity through higher excess voltage of single-photon avalanche diodes (SPADs). In addition, the infinite IF canceling (IIC) scheme that employs pulse-position modulation and time-difference modulation was designed to be compatible with the pre–post weighted histogram filter. For the IIC, the ON-chip SPAD-based random number generator provides a random code. A theoretical analysis of LiDAR performance such as MDR was introduced to prove the effectiveness of the pre-post weighted histogram filter. The fabricated sensor demonstrated 8.08-cm accuracy for a range of 32 m under high BGN (105-klx sunlight and 48.72-kcps dark-count rate with increased excess bias voltage) through the pre–post weighted histogram filter and IF immunity through the IIC scheme.

Time-Based Compute-in-Memory for Cryogenic Neural Network With Successive Approximation Register Time-to-Digital Converter

This article explores a compute-in-memory (CIM) paradigm’s new application for cryogenic neural network. Using the 28-nm cryogenic transistor model calibrated at 4 K, the time-based CIM macro comprised of the following: 1) area-efficient unit delay cell design for cryogenic operation and 2) area and power efficient, and a high-resolution achievable successive approximation register (SAR) time-to-digital converter (TDC) is proposed. The benchmark simulation first shows that the proposed macro has better latency than the current-based CIM counterpart. Next, the simulation further shows that it has better scalability for a larger size decoder design and process technology optimization.

Ion Microscope Imaging Mass Spectrometry Using a Timepix3-Based Optical Camera.

Ion microscopy allows for high-throughput mass spectrometry imaging. In order to resolve congested mass spectra, a high degree of timing precision is required from the microscope detector. In this paper we present an ion microscope mass spectrometer that uses a Timepix3 hybrid pixel readout with an optimal 1.56 ns resolution. A novel triggering technique is also employed to remove the need for an external time-to-digital converter (TDC) and allow the experiment to be performed using a low-cost and commercially available readout system. Results obtained from samples of rhodamine B demonstrate the application of multimass imaging sensors for microscope mass spectrometry imaging with high mass resolution.

An FPGA-based 48-channel, 250 mega samples per second throughput time measurement system

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) have been developed for years, which are widely used in high-energy physics, nuclear medical imaging and so on. In an application with large amount of channels and great destructiveness, TDC-based time measurement system should be optimized for real-time sampling and high data rate transmission when it is implemented in FPGA. In this paper, an FPGA-based 48-channel, 250 mega samples per second time measurement system is presented. A sampling controller is designed to overcome the length variation of carry chains. The sampling controller enables each carry chain to be distributed in one clock domain, which avoid the ultra-wide bins between different clock domains. Inner FIFOs are used to realize real-time sampling in a finite time, which can record every valid sampling with a dead time of 2 ns. Gigabit transceivers are utilized to support 10-Gb/s data transmission. Test results show that the average RMS resolution is about 16.4 ps.

Performance and Integration Results of a High Resolution Time-to-Digital Converter Designed for INO ICAL Experiment

INO ICAL Experiment emphasis on studying various properties of atmospheric neutrinos. A 50 kton Iron Calorimeter and Resistive plate Chamber (RPC) in stacked geometry will be used to track neutrinos. Position and directional information are to be used to identify particle energies. RPC detector signal of rise time less than 1ns is amplified-discriminated and given to Digital Front End (RPC-DAQ). To measure these fast pulses, we designed a low power, compact multi-channel Delay Chain based time-to-digital converter (TDC) in a 0.13μm CMOS process which will be integrated with the RPC-DAQ module. This TDC is capable of handling multiple hits per channel with a single-shot precision better than 65.34 ps. A 4-line or 11-line serial peripheral interface (SPI) is used for readout and configuration. This paper presents the performance and integration results of this TDC.

Development of a timing chip prototype in 110 nm CMOS technology

We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of 100x100 μm2, where the sensors are Low Gain Avalanche Diodes (LGADs). The long term focus is towards a possible replacement of disks in the extended forward pixel system (TEPX) of the CMS experiment during the High Luminosity LHC (HL-LHC). The requirements for this ASIC are the incorporation of a Time to Digital Converter (TDC) in the small pixel area, low power consumption, and radiation tolerance up to 5 × 1015 n eq cm−2 to withstand the radiation levels in the innermost detector modules for 3000 fb−1 of the HL-LHC (in the TEPX). A prototype has been designed and produced in 110 nm CMOS technology at LFoundry and UMC with different versions of TDC structures, together with a front end circuitry to interface with the sensors. The design of the TDC will be discussed, with the test set-up for the measurements, and the first results comparing the performance of the different structures.

Picosecond Timing Electronics for a DIRC-Like Detector at the Super Tau-Charm Facility

The DIRC-like time-of-flight detector (DTOF) at the Super Tau-Charm Facility (STCF) in China is a Cherenkov light detector that uses the TOF technique to identify charged particles. To achieve the expected target that provides a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\sigma \pi $ </tex-math></inline-formula> /K separation at 2-Ge/c momentum, a single-photon time resolution of better than 50 ps is required, while the contribution from electronics should be lower than 15 ps. To meet the requirements with high channel count integration, the timing electronics using leading-edge discrimination and field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) are employed in the DTOF detector. This article reports the results of the first phase of project where the timing electronics with 128 channels has been constructed and its performance has been evaluated. Including the uncertainty of system clock distribution and synchronization, the intrinsic timing resolution of the electronics is better than 10-ps rms. Taking fast microchannel plate photomultiplier tubes (MCP-PMTs) as Cherenkov photodetectors and adopting time-over-threshold (TOT) measurement for time walk correction, the measured single-photon time resolutions are better than 40-ps rms. The test results confirm that the proposed timing electronics has advantages of high precision and high integration, which is highly demanded in future picosecond timing detectors.

A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS

This paper presents a high-current calibration-free analog-digital hybrid controlled LDO for large-area digital load. The proposed architecture has the advantages of an analog controller (continuous and high DC accuracy) with distributed digital power transistors (flexible and scalable for high current applications). Distinctive from the conventional digital LDOs that directly quantize the output voltage, the proposed LDO utilizes an error amplifier (EA) to pre-amplify the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm {OUT}}$ </tex-math></inline-formula> error. Then, a 5-bit time-to-digital converter (TDC) quantizes the processed analog error signal subsequently transformed into a thermometer code that directly controls the distributed digital power transistors. This design can pull off high DC accuracy even without calibration. Besides, we implement an auxiliary constant current (ACC) circuit to solve reliability issues and to improve the stability under a large voltage dropout. Fabricated in a 28-nm bulk CMOS process with a 1.2-A load capability, the proposed LDO achieves 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{V}$ </tex-math></inline-formula> /mA load regulation and close to 1.5% output accuracy. By employing a wide bandwidth EA and a fast TDC, the hybrid LDO can obtain a fast transient response. The measured undershoot is 70 mV with a 0.6-A load step within 10-ns edge time, and the output voltage can scale from 0.6 V to 0.9 V within 30 ns.

CMOS Monolithic Thermostatic Microwave Heater With Bioimpedance Load Effect Compensation

Based on microwave heating, a monolithic low-power temperature-programmable high-precision microheater is implemented for thermotherapy. The microwave heater is designed and fabricated in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. The <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> -factor of the on-chip inductor that serves as the heat applicator would be degraded by the bioimpedance load effect when the heating target is in the vicinity of the microwave heater. Because of such bioimpedance load effect, the electric field around the heat applicator is decreased, which limits the heating efficiency of the microwave heater. To improve the heating efficiency, a bioimpedance load effect compensation technique is adopted to enhance the electric field around the heat applicator. Moreover, a time-to-digital converter (TDC)-based temperature sensor with a sensing resolution of 0.052 is employed to realize the thermostatic function with the precision of ±0.1 °C. Consuming 136 mW, the power amplifier of the heater delivers the output power of 25.36 mW (14 dBm). The heating rate of 0.24 °C/min and heating efficiency of 34.4 J/°C are achieved.

Linearity improvement of UltraScale+ FPGA-based time-to-digital converter

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the ‘HU method’ (HU TDC) and with ‘both HU and MCT methods’ (HU-MCT TDC) were measured and compared to those of the TDC with ‘DDL alone’ (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.