Time Violations Research Articles

Statistical analysis of hold time violations

Performance variability is increasing as CMOS devices are continuously scaled down to nanometer dimensions and is posing a major challenge to the profitability of scaled technologies. One of the major goals of a design flow is to satisfy timing constraints without sacrificing area and power. One of the most important tasks of design optimization is to identify and remove setup and hold time violations. Variability issues must be taken into account in order to improve the accuracy of violation removal algorithm. In this manuscript we derive statistical models for flip-flop race immunity and clock skew. Then we propose a probabilistic approach for hold-time violations. We present comparisons between probabilistic approach and worst-case approach and prove that the probabilistic method is less pessimistic while being more accurate. We propose a variation-aware methodology for computing the delay so as to satisfy the yield constraint.

Federico Lenzerini (ed.), Reparations for Indigenous Peoples: International and Comparative Perspectives

Indigenous peoples’ rights are historically grounded, not only because indigenous peoples have ‘historical continuity with pre-invasion and pre-colonial societies’,1 but also, and mainly, because they have been victims of serious historical human rights violations. As the United Nations Declaration on the Rights of Indigenous Peoples acknowledges, ‘indigenous peoples have suffered from historic injustices’. Such historical injustices include acts of genocide, slavery, dispossession of their lands, and general acts of discrimination. In most situations indigenous peoples are still awaiting justice. The issue of reparation for past human rights violations is usually controversial. The 2001 Durban World Conference on Racism nearly collapsed on issues relating to reparation for slavery and colonialism. A central issue of contention is the connection between present time and past violations. Reparation for indigenous peoples is equally problematic. The 22-year process that finally led to the adoption of the Declaration on the Rights of Indigenous Peoples in...

Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation

Supply voltage scaling is one of the easiest ways to reduce energy dissipation. Therefore, researchers have considered subthreshold logic as a promising option to achieve ultra low energy dissipation. However, circuit propagation delay is extremely sensitive to PVT variations under subthreshold operation. Hence, large delay margin is required for successful operation of conventional synchronous designs. Since leakage energy contributes to a substantial portion of total energy dissipation in subthreshold operation, the leakage energy dissipated for the required delay margin degrades energy efficiency significantly. In addition, even small intra-die variations result in large clock skew and hence, it is difficult to efficiently handle timing issues such as the setup and the hold time violations. In this work, we explore asynchronous design approach to address these challenges in subthreshold operation. We employ critical-path replica to generate completion signals of combinational logic blocks and use classical four-phase handshaking for communication between pipeline flip-flops. Since the proposed design approach uses only local clock buffers, it is easier to handle timing problems compared to synchronous designs. We compared iso-yield minimum energy dissipation of two design approaches (synchronous and asynchronous) in an inverter chain. Despite leakage overhead due to pad delay of critical-path delay line and ?return-to-zero? time of four-phase handshaking, the proposed asynchronous design shows 71% energy savings compared to its synchronous counterpart. To demonstrate subthreshold operation of the proposed design approach, we fabricated an 8-tap FIR filter in 90 nm CMOS. Measured oscilloscope plots of handshaking and output bus signals show that the design operates successfully below 300 mV. We also measured energy consumption of the FIR filter from 19 test chips-the average was 4.64 pJ and the standard deviation was 0.3526 pJ.

An empirical comparison of improvement heuristics for the mixed-model U-line balancing problem

Mixed-model assembly lines often create model imbalance due to differences in task times for the different product models. Smoothing algorithms guided by meta-heuristics that can escape local optimums can be used to reduce model imbalance. In this research, we utilise the meta-heuristics tabu search (TS), the great deluge algorithm (GDA) and record-to-record travel (RTR) to reduce three objective functions: the absolute deviation from cycle time, the maximum deviation from cycle time, and the sum of the cycle time violations. We found that the GDA was significantly superior to the RTR and TS algorithms across all problem sizes and objective functions. For the 19 task problems, RTR performed significantly better than TS for all three objective functions. On the other hand, for the 61 and 111 task problems TS performed significantly better than RTR for all three objective functions.

Delay in blood glucose monitoring during an insulin infusion protocol is associated with increased risk of hypoglycemia in intensive care units

Hypoglycemia during insulin infusion therapy is a major problem. We investigated whether a delay in blood glucose (BG) monitoring during an insulin infusion protocol (IIP) in the intensive care unit (ICU) is associated with hypoglycemia. Data were collected for 50 consecutive patients treated with Brigham and Women's Hospital's IIP. Point-of-care BG values were obtained from the bedside paper flow sheets and the exact times of individual measurements were ascertained from an internet-based glucose meter download program. Data were carefully studied for protocol time violations, defined as a delay of >10 minutes after the recommended time for BG measurement. A total of 2309 BG values were evaluated for time violation. A total of 1474 (63.9%) measurements had been obtained at the recommended time or earlier; 835 (36.1%) measurements had been obtained >10 minutes after the recommended time for measurement. There were a significantly higher proportion of BG values <80 mg/dL following the time violation as compared to no time violation (17.8% versus 11.6%; P < 0.001). We conclude that the risk of hypoglycemia during insulin infusion therapy is higher after a delay in BG measurement.

Impact of Phase Scheme on Development and Performance of a Logic Rule-Based Bus Rapid Transit Signal Priority

Focusing on isolated signalized intersections with four approaches along arterial median busway, a logic rule-based bus rapid transit signal priority (BRTSP), aiming to speed up bus rapid transit (BRT) service with less negative impact on general traffic, is developed based on a phase scheme including two BRT phases, eight vehicle phases, and four pedestrian phases. Two attributes for each vehicle phase, i.e., initial phase and terminal phase, are introduced to analyze the principles of potential phase sequences. Check-in and check-out detectors are placed on the busway to detect BRT vehicle arrivals and departures. Inductive loop detector is placed on each lane of the vehicle phase to monitor time headway(s) on a lane-by-lane basis. All the components of BRTSP can accommodate the variety of phase scheme. The minimum green time of the vehicle phase and the walk interval of the pedestrian phase are calculated cycle by cycle. In case of a BRT vehicle arrival or departure, a priority request either for green extension or for early green may be generated or cancelled by rules for priority request generation. Rules for phase transition can manipulate phase transition durations and avoid intergreen time violations. Using a binary choice approach, rules for green duration adjustment and rules for barrier crossing can serve the priority requests and adjust the green duration of each vehicle phase in an acyclic manner. Simulation experiments conducted by a microscopic, behavior-based multipurpose traffic simulation program indicated that (1) for the phase sequences where the through vehicle phases concurrent with the BRT phases were specified as the terminal phases, the left-turn vehicle phases adjacent to the BRT phases were not recommended to serve early green request in heavy load scenarios; (2) the phase sequence with more through vehicle phases being specified as the initial phases had the potential to enable BRTSP to yield better intersection performance.

Promoting Acute Thrombolysis for Ischaemic Stroke (PRACTISE)

Thrombolysis with intravenous rtPA is an effective treatment for patients with ischaemic stroke if given within 3 h from onset. Generally, more than 20% of stroke patients arrive in time to be treated with thrombolysis. Nevertheless, in most hospitals, only 1-8% of all stroke patients are actually treated. Interorganisational, intraorganisational, medical and psychological barriers are hampering broad implementation of thrombolysis for acute ischaemic stroke. To evaluate the effect of a high-intensity implementation strategy for intravenous thrombolysis in acute ischaemic stroke, compared with regular implementation; to identify success factors and obstacles for implementation and to assess its cost-effectiveness, taking into account the costs of implementation. The PRACTISE study is a national cluster-randomised-controlled trial. Twelve hospitals have been assigned to the regular or high-intensity intervention by random allocation after pair-wise matching. The high-intensity implementation consists of training sessions in conformity with the Breakthrough model, and a tool kit. All patients who are admitted with acute stroke and onset of symptoms not longer than 24 h are registered. The primary outcome measure is treatment with thrombolysis. Secondary outcomes are admission within 4 h after onset of symptoms, death or disability at 3 months, the rate of haemorrhagic complications in patients treated with thrombolysis, and costs of implementation and stroke care in the acute setting. Tertiary outcomes are derived from detailed criteria for the organisational characteristics, such as door-to-needle time and protocol violations. These can be used to monitor the implementation process and study the effectiveness of specific interventions. This study will provide important information on the effectiveness and cost-effectiveness of actively implementing an established treatment for acute ischaemic stroke. The multifaceted aspect of the intervention will make it difficult to attribute a difference in the primary outcome measure to a specific aspect of the intervention. However, careful monitoring of intermediate parameters as well as monitoring of accomplished SMART tasks can be expected to provide useful insights into the nature and role of factors associated with implementation of thrombolysis for acute ischaemic stroke, and of effective acute interventions in general.

FABSYN: floorplan-aware bus architecture synthesis

As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design How, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort.

A hybrid genetic approach for airborne sensor vehicle routing in real-time reconnaissance missions

Past initiatives to address surveillance and reconnaissance mission planning mainly focused on low-level control aspects such as real-time path planning and collision avoidance algorithms in limited environment. However, few efforts have been spent on high-level real-time task allocation. It is believed that automated decision capabilities supporting real-time resource allocation for sensor control and interactions might significantly reduce user workload, focusing attention on alternate tasks and objectives while assigning hard computational tasks to artificial agents. In this paper, we propose a new hybrid genetic algorithm to solve the dynamic vehicle routing problem with time windows, in which a group of airborne sensors are engaged in a reconnaissance mission evolving in a dynamic uncertain environment involving known and unknown targets/threats. In that context, visiting a target may consist in carrying out a collection of subtasks such as search, detect, recognize and confirm suspected targets, discover and confirm new ones. The approach consists in concurrently evolving two populations of solutions to minimize total travel time and temporal constraint violation using genetic operators combining variations of key concepts inspired from routing techniques and search strategies. A least commitment principle in servicing scheduled customers is also exploited to potentially improve solution quality.

Resource Sharing Combined with Layout Effects in High-Level Synthesis

In deep-submicron designs, the interconnects are equally as or more important than the logic gates. In particular, to achieve timing closure, it is necessary and critical to consider the interconnect delay at an early stage of the synthesis process. It has been known that resource sharing in high-level synthesis is one of the major synthesis tasks which greatly affect the final synthesis/layout results. In this paper, we propose a new layout-aware resource sharing approach to overcome some of the limitations of the previous works in which the effects of layout on the synthesis have never been taken into account or considered in local and limited ways, or whose computation time is excessively large. The proposed approach consists of two steps: (Step 1) We relax the integrated resource sharing and placement into an efficient linear programming (LP) formulation based on the concept of $discretisizing$ placement space; (Step 2) We derive a feasible solution from the solution obtained in Step 1. Then, we employ an iterative mechanism based on the two steps to tightly integrate resource sharing and placement tasks so that the slack time violation due to interconnect delay (determined by placement) as well as logic delay (determined by resource sharing) should be minimized. From experiments using a set of benchmark designs, it is shown that the approach is effective, and efficient, completely removing the slack time violation produced by conventional methods.

Handling inverted temperature dependence in static timing analysis

In digital circuit design, it is typically assumed that cell delay increases with decreasing voltage and increasing temperature. This assumption is the basis of the cornering approach with cell libraries in static timing analysis (STA). However, this assumption breaks down at low supply voltages because cell delay can decrease with increasing temperature. This phenomenon is caused by a competition between mobility and threshold voltage to dominate cell delay. We refer to this phenomenon as the inverted temperature dependence (ITD). Due to ITD, it becomes very difficult to analytically determine the temperatures that maximize or minimize the delay of a cell or a path. As such, ITD has profound consequences for STA: (1) ITD essentially invalidates the approach of defining corners by independently varying voltage and temperature; (2) ITD makes it more difficult to find short paths, leading to difficulties in detecting hold time violations; and (3) the effect of ITD will worsen as supply voltages decrease and threshold voltage variations increase. This article analyzes the consequences of ITD in STA and proposes a proper handling of ITD in an industrial sign-off STA tool. To the best of our knowledge, this article is the first such work.

FABSYN: floorplan-aware bus architecture synthesis

As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design How, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort.

On the Way to Experimental Test of the Time Reversal Invariance in the Nuclear Reactions.

Time (T) violation can be related with charge-parity (CP) violation through the CPT theorem. The CP violation was discovered experimentally in the K0-meson decays about 35 years ago. The T violating interaction related with the CP violation violates parity as well. However, an extension of the theory beyond the locality of the interactions might violate the CPT theorem. The result of the CPLEAR experiment [1], which has given direct evidence of T violation in the elementary-particle phenomena, could be considered under assumption of the CPT invariance.

Self-Regulation and Inhibition in Comorbid ADHD Children: An Evaluation of Executive Functions

The relationship between executive function and comorbid diagnoses in ADHD children is examined. One hundred six children between 7 and 15 years of age are assessed using the Tower of London (TOL), a test of executive function, and the Kiddie Schedule of Affective Disorders and Schizophrenia, Present and Lifetime Version, a diagnostic interview. All children met the diagnostic criteria for ADHD. A majority of the children had comorbid anxiety disorders, mood disorders, or oppositional defiant disorder. Measures on the TOL are total move score, total initiation time, and total rule violations. Age is predictive in all three measures of executive function as assessed by the TOL. Gender is predictive of total initiation time and total rule violations. Comorbid disorders are found to not have significance on executive function as measured by the TOL. This study concludes that comorbid disorders may not affect executive function

The Tower of London and neuropsychological assessment of ADHD in adults

Executive function refers to a variety of behaviors and abilities related to planning and strategy use, as well as the maintenance of attention and behavior in the pursuit of some goal; these behaviors are generally deficient in individuals with Attention Deficit Hyperactivity Disorder (ADHD). The Tower of London (TOL) is one task used in the assessment of executive function. For adults with ADHD, there is minimal research on the extent to which they demonstrate impaired performance on tower tasks. With a sample of 102 individuals between the ages of 16 and 33 years, the extent to which performance on the TOL–Drexel Edition (TOL DX) was related to performance on other measures of executive function and diagnostic grouping was investigated. Results indicated that TOL DX variables are not correlated significantly with age or Global Assessment of Functioning (GAF). Of the TOL DX variables, only Rule Violations correlated with multiple other executive function variables. Rule Violations correlated minimally, but significantly, with cognitive ability, perceptual skills, Matrix Reasoning, Processing Speed, and immediate memory. As might be expected, Processing Speed also significantly correlated with Total Time and Time Violations. Notably, scores on the TOL DX did not correlate significantly with behavioral self-report; no between-group (ADHD, Clinical Control, No Diagnosis) differences emerged for any of the TOL DX variables. Further, with this sample, mean scores across the TOL DX variables were well within the average range. Taken together, these results suggest that while the TOL DX measures aspects of ability not tapped by other measures, and may therefore provide additional information on individual functioning, results should not be interpreted as indicative of the presence or absence of a disorder.

High energy physics - phenomenology

Models with extra dimensions are often invoked to resolve cosmological problems. We investigate the possibility of apparent acausality as seen by a brane-based observer resulting from signal propagation through the extra dimensions. Null geodesics are first computed in static and cosmological single-brane models, following which we derive the equations of motion for the inter-brane distance in a two-brane scenario, which we use to examine possible acausality in this more complex setup. Despite observing significant effective acausality in some situations there is no a priori solution to the horizon problem using this mechanism. In the two-brane scenario there can be significant late time violation of gravitational Lorentz invariance, resulting in the gravitational horizon being larger than the particle horizon, leading to potential signals in gravitational wave detectors.

Ricci-Tersenghiet al.Reply:

In a Comment (cond-mat/0103444) on our recent paper "Two time scales and violation of FDT in a finite dimensional model for structural glasses" [1], A. de Candia and A. Coniglio show evidence that the equilibrium overlap distribution P(q) of the frustrated Ising lattice gas (FILG) does not coincide with the one that could be estimated from the off-equilibrium results presented in [1]. In this Reply we show new results on the glassy phase of the FILG that clarify the controversy. Nevertheless, the structure of the equilibrium P(q) remains an open problem. [1] F. Ricci-Tersenghi, D. A. Stariolo and J. J. Arenzon, Phys. Rev. Lett. 84, 4473 (2000).

Surrogate Measures of Visual Demand while Driving

A driving simulator study involving a total of 40 participants was conducted in one dynamic and two static data collection environments: driving in the simulator, parked in the simulator and in a static test mock-up. Participants were asked to perform tasks on a navigation system, a cellular telephone and a compact disk player. Total task time was measured in all environments and lane violations were measured in the dynamic environment. Task times measured in the static environments were found to be good predictors of both dynamic task time and lane violations.

Two time scales and violation of the fluctuation-dissipation theorem in a finite dimensional model for structural glasses

We study the breakdown of fluctuation-dissipation relations between time-dependent density-density correlations and associated responses following a quench in the chemical potential in the frustrated Ising lattice gas. The corresponding slow dynamics is characterized by two well-separated time scales characterized by a constant value of the fluctuation-dissipation ratio. This result is particularly relevant since activated processes dominate the long-time dynamics of the system.

An IDDQ sensor for concurrent timing error detection

Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions during system operation are caused by transient faults, which often manifest themselves as abnormal signal delays that may result in violations of circuit element timing constraints. We present a novel complementary metal-oxide-semiconductor-based concurrent error-detection circuit that allows a flip-flop (or other timing-sensitive circuit element) to sense and signal when its data has been potentially corrupted by a setup or hold timing violation. Our circuit employs on-chip quiescent supply current evaluation to determine when the input changes in relation to a clock edge. Current through the detection circuit should be negligible while the input is stable. If the input changes too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the time of the clock transition, and an error is flagged. We have designed, fabricated, and evaluated a test chip that shows that such an approach can be used to detect setup and hold time violations effectively in clocked circuit elements.