Time-interleaved Research Articles

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs

This paper presents a fully digital background calibration method for time-interleaved (TI) analog-to-digital converters (ADCs). The timing detector employs a timing detection method based on an enhanced autocorrelation function, combined with matrix operations, to improve the accuracy of timing mismatch acquisition. The algorithm makes full use of the autocorrelation functions of each channel and proposes a more precise method for obtaining autocorrelation derivatives. Furthermore, the algorithm features a simple structure, low computational complexity, and can support timing calibration for any number of channels without requiring additional channels. The algorithm was validated using an ADC + FPGA combined system, with a 8-channel TI-ADC manufactured in 28 nm technology and a sampling rate of 20 GS/s. Results demonstrate that compared to the uncalibrated state, the algorithm significantly improves the SNDR and SFDR from 27.98 dB and 30.76 dB to 39.38 dB and 42.13 dB, respectively when the inputs are near the Nyquist frequency.

A 14-bit 1-GS/s Pipelined-SAR ADC in 28-nm CMOS with Foreground and Background Calibration

A 14-bit 1-GS/s Pipelined-Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in 28-nm CMOS is presented in this paper. In the initial phase, a pair of SAR ADCs employing the Time-Interleaved (TI) technique are employed to attain the necessary sampling rate. A multi-comparators structure is used to increase the speed and improve the mismatch. We have implemented a foreground calibration technique to address capacitor mismatch, optimizing its processing logic to enhance the chip’s speed. The interstage operational amplifier adopts a two-stage structure. Some structural changes are presented to optimize its bandwidth and phase margin. A background calibration method for gain error is implemented. In the subsequent phase, we employ four SAR ADCs utilizing the TI method. The outcomes demonstrate that the ADC delivers a Signal-to-Noise and Distortion Ratio (SNDR) of 65.58 dB and a Spurious-Free Dynamic Range (SFDR) of 72.12 dB at a 1-GS/s sampling rate without calibration, and 69.02 dB SNDR and 81.26 dB SFDR at the same 1-GS/s sampling rate with calibration. The core layout occupies an area of 0.6 mm2 and consumes 225.02 mW of power.

A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward

A noise-shaping successive approximation register (NS-SAR) ADC combines the merits of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta $</tex-math> </inline-formula> - <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Sigma $</tex-math> </inline-formula> and SAR ADC, transforming it into an emerging ADC architecture to reach high resolution with good power efficiency. The single-channel NS-SAR with high resolution, however, suffers from bandwidth (BW) limitations. The time-interleaved (TI) NS-SAR mitigates the speed bottleneck but faces challenges in obtaining high resolution and BW simultaneously due to the lack of a sharp noise transfer function (NTF). This article presents a calibration-free two-channel TI-NS-SAR with an aggressive second-order NTF for high resolution. Based on a one-time error feedback (FB) at midway, we propose a second-order error-feedforward (FF) to enhance the noise-shaping (NS) effect further meanwhile avoiding the excessive NTF peaking and dynamic range (DR) loss. A dynamic residue amplifier shared between two channels lowers the offset, which reduces the redundant bit to only one bit, thus improving the efficiency of SAR conversion. Fabricated in a 28 nm CMOS with 1 V supply, the prototype achieves 73.2 dB-signal-to-noise-and-distortion-ratio (SNDR) over 30 MHz-BW when operating at 330 MHz. It consumes 3.07 mW and exhibits a Schreier FoM (FoMs) of 173.1 dB.

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

Evaluation of ATSC 3.0 and 3GPP Rel-17 5G Broadcasting Systems for Mobile Handheld Applications

This paper provides performance evaluations of two state-of-the-art terrestrial broadcasting systems, ATSC 3.0 and 3GPP Rel-17 5G broadcast, in terms of physical layer capability, network deployment and operating costs. The physical layer performances are evaluated in the mobile broadcasting environment, considering practical implementations of the handheld terminals. Extensive simulation results demonstrate that ATSC 3.0 outperforms 5G broadcast, because of well-designed bit interleaved coded modulation (BICM) and time interleaver that can mitigate deep signal fades. The capital expenditures (CAPEX) and operating expenses (OPEX) of the two systems are analyzed based on physical layer performances. The evaluations could be used for the planning of terrestrial broadcast services to mobile handheld devices.

A Reconfigurable 8-to-10-bit 20-to-5-GS/s time-interleaved time-domain ADC

This paper presents a 16-way time-interleaved (TI) time-domain (TD) analog-to-digital converter (ADC) with full multiplexing of hardware resources and highly synchronous reconfigurable from 8-to-10-bit 20-to-5-GS/s accuracy and speed for multi-standard communication systems. A gain reconfigurable voltage-to-time converter (VTC) with high-precision RF sampling circuitry is proposed to achieve an input bandwidth greater than 18 GHz and an SFDR of 49.93 dB in 20-GS/s mode. The high-resolution, low-jitter time-to-digital converter (TDC) exploits ring-oscillation (RO) dual-channel multiplexing to mitigate inter-channel mismatch and introduces a time-amplifier (TA) based on the discharge time difference to determine the order of the rising edge corresponding to the differential signal. Fabricated in a 40-nm CMOS process, the ADC can be configured as a 5-GS/s 10-b, 10-GS/s 9-b, or 20-GS/s 8-b converter. It demonstrates the 50.81-/46.67-/36.79-dB SNDR and 56.42-/54.59-/45.77-dB SFDR at the Nyquist input frequencies corresponding to the three modes mentioned above, with the power consumption of 83.6-/103.7-/139.3-mW contributing to Walden figure-of-merit (FoMW) value of 59.0-/58.9-/123.4- fJ/conversion-step.

A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration

Time interleaving (TI) is an effective approach to higher speed conversion of current-steering digital-to-analog converters (DACs). However, achieving high linearity performance for these TI DACs is challenging during interleaving synchronization, output current summation, and parasitic capacitance control. This article exploits the design of a 6.0-GS/s 14-bit two-channel time-interleaved DAC in a 65-nm CMOS process for communication systems. A novel asymmetric current-tree summation network is proposed to reduce the current summation nonlinearity in the DAC. A differential clock phase and duty-cycle calibration scheme is also adopted while achieving low complexity. Furthermore, a current source layout optimization scheme is proposed that significantly reduces the parasitic capacitance of interleaving switches and improves the linearity. Measurement results of the fabricated DAC show 6–20-dB spurious-free dynamic range (SFDR) improvement with the proposed techniques, achieving >60-dB SFDR up to 1355 MHz and >50-dB SFDR up to the Nyquist.

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion

This paper presents a neural network-based digital calibration algorithm for high-speed and time-interleaved (TI) ADCs. In contrast with prior methods, the proposed work features joint amplitude-dependent and phase-dependent nonlinear distortion correction without prior-knowledge of ADC architecture feature. A dynamic calibration is first used to compensate for phase-dependent distortion. Two training optimizations, including a sub-range-sample-based batch schemes and a recursive foreground co-calibration flow are proposed to reduce the error and overfitting and further save hardware resources. A practical calibration engine is also investigated for interleaved ADCs with distributed weight and shared weight methods. To demonstrate the effectiveness of the method, the calibration engine is verified by two fabricated ADC prototypes, a 5 GS/s 16-way interleaved ADC and a 625 MS/s interleaving-SAR assisted pipeline ADC. Measurement results show that SFDR is improved between 16.9dB and 36.4dB before and after calibration for different frequency inputs. To trade-off between accuracy and power consumption, a quantized and pruned engine is implemented on both FPGA and 28nm CMOS technology. Experimental results show that the dedicated calibration on silicon consumes 8.64mW with 0.9V power supply at 333MHz clock rate. Measurement results show that the quantized hardware implementation has only 0.4-4 dB loss in SFDR.

A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs

This brief presents a digital background calibration technique for timing skew in time-interleaved (TI) analog-to-digital converters (ADCs). It updates the calibration step adaptively based on the detection error. This results in large update step initially, and it reduces with the calibration cycle going on. More than two times convergence time is saved compared with the conventional fixed update step method. Besides, by extending the compensation to second-order, both calibration range and accuracy are improved. To demonstrate the effectiveness of the proposed timing skew calibration, extensive simulation and measurement results are provided. It shows that after timing skew calibration, the signal-to-noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) of a two-channel prototype TI ADC are improved by 8.2 and 14.9 dB, respectively.

A 6-GHz Bandwidth Input Buffer Based on AC-Coupled Flipped Source Follower for 12-bit 8-GS/s ADC in 28-nm CMOS

This brief presents an input buffer based on AC-coupled flipped source follower (SF) for a 12-bit 8-GS/s time-interleaved (TI) ADC. The flipped SF can drive the ADC’s sampling capacitance with high linearity because the input MOS’s drain current is almost independent of the load capacitance. In addition, the inherent feedback reduces the input buffer’s output impedance, which improves the bandwidth when driving the complex wiring network of TI ADCs. The proposed AC-coupling structure enlarges the input signal range of the flipped SF extensively, making it practical to be used for high-speed ADCs. A compensation capacitor is used to compensate for the nonlinear parasitic capacitance of the input MOS to further improve the linearity. An 8-channel 12-bit 8GS/s TI ADC prototype with the proposed input buffer is implemented in a 28-nm mixed-signal CMOS process. Measured results show that the input bandwidth of the input buffer exceeds 6 GHz with 137-mW power supply. The ADC achieves SFDR of 68 dBFS and SNDR of 54.9 dB with 3.9-GHz, −1-dBFS input signal under 8-GS/s sampling rate. The total power consumption of the ADC is 1.05 W.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations

This brief presents a 12-bit successive approximation register (SAR)-based time-interleaved (TI) analog-to-digital converter (ADC) with a fully programmable interleaving factor. A total of six SAR sub-ADCs can be time-interleaved. The interleaving factor is programmable from 2 to 6, resulting in an overall sampling rate from 300 to 900MS/s. On-chip offset, gain, and timing skew background calibrations allow reducing the interleaving spurs to less than −73dBc in every configuration. In particular, the proposed difference-based skew calibration efficiently operates in any configuration, not being limited to power-of-2 interleaving factors. Fabricated in a 28-nm bulk CMOS process, the presented TI-ADC achieves a Nyquist-frequency signal-to-noise plus distortion ratio (SNDR) and a spurious-free dynamic range (SFDR) of 52.01dB and 58.82dBc at 900MS/s, respectively, with an active area occupation of 0.48 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\mathbf {2}}$ </tex-math></inline-formula> and similar metrics across all the configurations. Featuring a power dissipation of 42.96mW at 900MS/s, the Nyquist-frequency Schreier figure of merit (FoM) is 152.2dB, whereas the Walden one is 146.6fJ/Conv-step.

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With &gt;55-dBFS SNR and &gt;67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

In this article, a 3 GS/s Time-Interleaved (TI) RF Track-and-Hold (TaH) amplifier designed in a 22 nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled Front-End (FE) buffer. The measured TaH amplifier has a SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling sub-sampling. An overall system bandwidth of 4.5 GHz is achieved with a SNR above 55 dBFS. The ultra-low-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multi-tone measurements reveal a third inter-modulation and inter-band non-linearity with >72 dBFS and >82 dBFS respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode-feedback by using the bulk as an control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/-0.8 V supply.

Estimation of Broadband Time-Interleaved ADC’s Impairments and Performance Using Only Single-Tone Measurements

This paper presents a method to estimate the internal impairment parameters of broadband time-interleaved (TI) ADCs using only single-tone measurement data acquired at two different frequencies. The estimated parameters, which include the signal-independent noise power, clock jitter, nonlinearity coefficients, and all sub-ADC mismatch parameters, are further used to predict the error power breakdown and the overall SNDR of the ADC for a multi-tone signal. In this way, the underlying sources of a TI ADC’s performance limitations can be separately evaluated with standard and low-cost single-tone measurements. Accurate estimation of the ADC’s impairment parameters is helpful for iteratively improving the ADC’s performance during design, characterizing prototypes, and potentially simplifying the production test. The proposed method is verified with comprehensive simulations and hardware measurement on a 3.6-GSPS, 12-bit, 2-channel TI ADC whose SNDR for a multi-tone signal is estimated at about 1 dB of its actual value sweeping its internal parameters over a wide range of values.

A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC

This article proposes a fully dynamic, low-power, wideband, time-interleaved (TI), noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feedforward (CIFF) architecture. Both the interleaving operation and the loop filter are implemented by using the fully passive switched-capacitor circuits. The feedforward summation is realized by a multi-path dynamic comparator. The overall noise transfer function (NTF) is highly robust against process, voltage, and temperature (PVT) variations since the NTF is determined by device ratios. This allows the NTF zeros to be close to 1, with a good NS effect. Compared with a recently published TI NS SAR based on the error-feedback (EF) architecture, this work does not need a static amplifier, thus leading to the fully dynamic operation. Meanwhile, it eliminates the dependence of NTF on the PVT-sensitive amplifier gain. Implemented in a 40-nm CMOS process, the prototype ADC achieves an SNDR of 69.1 dB, a bandwidth of 50 MHz, and a power consumption of 8.5 mW under a 1.1-V supply, leading to a Walden FoM of 36.3 fJ/conv.-step.

A Timing Mismatch Background Calibration Algorithm With Improved Accuracy

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

Frequency response mismatch calibration in 2-channel time-interleaved oscilloscopes.

The time-interleaved (TI) structure has been widely implemented in high speed, wideband data acquisition systems to increase the system sampling rate. However, the frequency responses of each sub-sampling path are not identical. This is named frequency response mismatches (FRMs). In TI-based printed circuit board level systems, due to the impact of the parasitic parameters, the FRMs are more complicated than the mismatches in TI analog-to-digital converters (TIADCs), which degrade the system performance severely. Therefore, the FRM calibration in 2-channel TI acquisition systems with two features is researched. The first one is that the TI system has a larger mismatch range than in most previous research. The second one is that the channel frequency response uses the general model. The calibration structure is established by the analysis of the digital TI model, which implements the TI operation in the digital domain to reconstruct the mismatches in the time domain. Furthermore, the problem of designing an arbitrary frequency response filter is transformed to the question of designing a three-stage cascaded filter group, which gives a method to realize the arbitrary frequency response in a real system. An oscilloscope prototype is proposed to verify the calibration performance. The simulation and experiment show the following: (i) Even though it uses the general frequency response and the FRMs are significant, the proposed method is still effective. (ii) The mismatch range of magnitude and phase responses is highly suppressed, and the spurious-free dynamic range is improved by 16.26 dB after calibration of the prototype.

A 4GS/s 8‐bit time‐interleaved SAR ADC with an energy‐efficient architecture in 130 nm CMOS

AbstractThis paper presents the design, implementation, and measurements of a 4 GS/s, 8‐bit resolution, time‐interleaved (TI) analog‐to‐digital converter (ADC) comprised of 32 asynchronous successive approximation register (SAR) ADCs. The chip is fabricated in a 130 nm CMOS process. This prototype achieves the highest sampling rate and the best efficiency for a SAR TI‐ADC in the process used. An energy‐efficient hierarchical T&amp;H architecture, ranked in a 4 × 8 structure, has been used to interleave the aforementioned high number of SAR ADCs avoiding the power hungry buffers typically used in the input signal path and/or T&amp;H outputs. The sampling architecture includes programmable delay cells with up to 104 fs resolution to calibrate sampling time errors. Additionally, the input matching network uses an on‐chip inductance to mitigate the impact of the packaging on the analog bandwidth. An efficient SAR ADC implementation is achieved by an optimized comparator design, which allows for both, noise and asynchronous clock control, and includes background DC offset calibration. The test chip is the core of a measurement platform dedicated to the evaluation of mismatch calibration techniques for ADCs used in high speed digital communication systems. To enable this application, a 32Gb/s low‐voltage differential signaling interface is included to transmit the samples off‐chip without any decimation. The TI‐ADC achieves a peak 7.09 effective number of bits (ENOB) (5.47ENOB at Nyquist) and 1.3 GHz input bandwidth with a power consumption of 93 mW at 1.2 V. Each SAR ADC channel achieves a Walden figure of merit (FOM) of 123fJ/conv‐step and owing to the efficient interleaved architecture the full TI‐ADC achieves a peak FOM of 171fJ/conv‐step (526fJ/conv‐step at Nyquist).

A fast Fourier transform based method to estimate frequency response mismatches in time interleaved systems.

Time interleaving (TI) technique is widely used in acquisition systems to improve the sampling rate. However, as a parallel sampling structure, it inevitably brings in channel mismatches, such as the offset mismatch, gain mismatch, and time mismatch. Moreover, the gain mismatch and time mismatch are frequency-dependent, which means that the gain mismatch and time mismatch will be different when the signal frequency changes. This is because the gain and time mismatches are the special circumstances of frequency response mismatches. In this paper, a frequency response mismatch estimation method in TI acquisition systems is proposed and analyzed. First, the two kinds of mismatch models are compared to find the relationship between frequency response mismatches and the gain and time mismatches. Then, a mismatch estimation method that can estimate mismatches when the analog bandwidth exceeds the sampling rate of a single channel in a time interleaving analog to digital converter is proposed. Sinusoids with different frequencies are utilized to convert the question of estimating frequency response mismatches to acquiring the mismatch coefficients at a series of frequency points. Furthermore, a semi-automatic estimation technique is proposed to reduce the operation time, and a 10 GSPS eight-channel TI system is introduced. Simulations show the accuracy and effectiveness of the proposed method. At last, the frequency response mismatches are calibrated by using the estimated parameters. The calibration improves the performance of an eight-channel TI system from the original spurious free dynamic range of 27.6639 to 56.7029 dB and signal-to-noise ratio of 25.5468 to 32.7667 dB. The calibration result demonstrates the usefulness of the proposed method.

Time‐interleaving design of error‐feedback sigma‐delta modulators with infinite impulse response noise transfer function

Transceivers built to modern communication standards tend to be as digital as possible, including the radio-frequency stages. This forces the digital-to-analogue converters (DACs) in the transmitter section to have a large bandwidth. DACs based on sigma-delta (SD) modulation represent a good choice in modern digital technologies as they have a simple analogue circuitry with limited accuracy requirements. Error-feedback (EF) architectures are widely used in the realisation of SD modulators. In many applications, DAC output has a small number of bits. In that case, the noise transfer function (NTF) must be of high order (to achieve a high dynamic range) and of the infinite impulse response (IIR) type (for the sake of stability). Concerning its implementation, one of the main challenges comes from the speed limitation of the technology. In this sense, time-interleaving (TI) allows the designer a trade-off between complexity and speed. Transforming the EF architecture into its TI counterpart is not straightforward for IIR NTFs. A procedure for this transformation is proposed, and a case study is described for a third-order modulator. A method of coefficient rounding is also proposed to simplify the digital implementation of the modulator while avoiding mismatches between the parallel paths of the TI modulator.