Bottom Of Through Silicon Via Research Articles

Development of Low Temperature Double Level TSV, Hole and Seal Process for Low Pressure Zero Level MEMS Packaging

Through Silicon Via (TSV) technology is considered one of the key methods to enable heterogeneous integration at the third dimension and realize electrical interconnection between device parts. In that context, different components (MEMS, sensors, circuits etc.) can be electrically integrated in 3D manner, increasing stack density, shrinking footprint, and reducing fabrication costs. At MEMS integration, it is important to explore the packaging method that enables the optimum performance of the active MEMS component and the TSV approach to electrically connect it with the package. Herein, we present our via-last approach to integrate a zero-level packaged MEMS wafer defined by cavity SOI (C-SOI) and CMOS readout circuitry (at thermal budget <400ºC). TSV distribution and fabrication route ensures the electrical connectivity of MEMS inertial sensor and CMOS. Furthermore, a hole is added to the layout scheme and sealed afterwards to ensure low pressure encapsulation in the MEMS cavity.In our previous work related to MEMS fabrication [1], we elaborated the superiority of C-SOI start material over conventional fabrication methods (like vapor HF). In our approach, MEMS cavity structures are realized by patterning dielectrics and the moving parts by employing deep Si etch (DSiE) method (Fig 1 a-c). To enhance the dielectric surface smoothness prior bonding, a complementary HF -based clean applied. This way, bonding requirements (Rq<1nm, Rrange<10nm) are met. CMOS wafer is fabricated with a single layer of Cu damascene process in a dielectric stack to create complementary bonding medium for MEMS wafer. Selected dielectrics at MEMS (thermal oxide) and CMOS (SiCN) can perform better at low temperature fusion bonding due to their moisture blocking capability. Next, fusion bonding at room temperature is carried out using assisted force (60kN) to enhance bonding efficiency and completed by curing the wafer pair at 350˚C.In this paper, we present further work to complete the MEMS zero-level packaging through electrical connections and vacuum seal. Fabrication sequence continues on the backside of the MEMS wafer (Fig 1d-g). First the desired top membrane (cap) thickness of MEMS wafer realized by thinning bulk Si substrate down to 50µm. After SiOx deposition, a double TSV approach is carried out aiming to create the electrical interconnections between the package components, one to reach to the sensor parts in MEMS wafer and one to reach to CMOS. TSV for enabling the connection with sensor parts (12x50μm) is realized by DSiE through the top Si membrane and buried oxide (BOX) landing at Si epi layer of C-SOI. Isolation of this TSV is obtained by conformal liner deposition using SACVD SiOx (350C). Liner opening at the TSV base is assisted by a second non-conformal dielectric deposition to protect the sidewall isolation during resistless directional liner etch back at TSV bottom. Metallization of the via is carried out by sequential PVD barrier (Ta) and seed (Cu) depositions; and the TSV is filled with electroplated Cu. MEMS top surface is then cleared either by CMP or by wet and dry etching of Cu and Ta, respectively. TSV for connecting to CMOS (20x80μm) follows the same processing route with an additional DSiE through all the C-SOI MEMS stack and landing on designated plugs on CMOS. With these two TSV schemes it is ensured to bias and measure the inertial sensor, its driving circuitry, and the zero-level package (Fig. 2a)Once the two TSVs fabrication is completed, hole for the vacuum sealing can be created. First, the top dielectric on surface of MEMS wafer is etched in circular areas of diameter 10μm to define where the venting holes will be created. This is mainly to expose Si surface and reduce possible leakage paths, as well as to increase the adhesion of the deposited metallization to close the hole under vacuum. Small hole (Ø2μm) is defined in the middle of the Si circular area by lithography and etching through the top MEMS membrane (50μm) landing on the cavity of the C-SOI (Fig 1f). Vacuum seal of the zero-level package is finalized with bond pad creation which also seals the hole under vacuum. Al deposition is carried out at high vacuum PVD system; the hole is simultaneously sealed and preserve the same vacuum as the PVD chamber. Along with the chamber vacuum level, the Al thickness and power is also very important to achieve the desired seal Fig.2b.Proposed work enables zero-level MEMS hermetic packaging with integrated CMOS and developed on 200mm wafers.[1] Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging, A.Malainou, J.Visker, D.Sabuncuoglu, 21st EPTC, Singapore 2019 Figure 1

Pulse Electrodeposition of Cu through-Silicon-Via (TSV) with Surface Suppressor

In recent years, many researches have been focused on the miniaturization of the integrated circuit (IC) feature size to improve the performance of semiconductor devices. However, we are facing the problems such as physical limit of the miniaturization and then increasing processing cost. To overcome these problems the Through-Si-Via (TSV) interconnection, a kind of the 3D interconnection, is a promising technology that could achieve high density, lower energy consumption and high performance in the IC. Since the TSV filling process is costly in the entire TSV process, the TSV filling process which the Cu electrodeposition for TSV is one of key processes. The TSV bottom-up filling which the filling of Cu from the bottom to the top of via with suppressed lateral growth is the solution to ensure a void free filling in high aspect ratio TSV. The bottom-up filling could be achieved by using additives like a suppressor and an accelerator in the electrolyte. In a theoretical model, the suppression breakdown at the bottom of TSV cause the bottom-up filling of TSV. Simultaneous desorption of suppressor by high potential due to ion depletion in the via bottom leads focus of current at the via bottom. Due to adsorption/desorption behavior of the suppressor, the bottom-up TSV filling could be achieved by only using the suppressor.1-3 Furthermore, it was reported that the suppressor at the sidewall is replaced by the accelerator and then the bottom-up filling performance was degraded.3 Lu et al. introduced the nanotwin Cu thin film, which had been attained with pulse electrodeposition.4 Mechanical properties of the Cu thin film is significantly enhanced by highly dense coherent twin boundaries without the degradation of electrical conductivity. Because it could effectively block the dislocation motion without interrupting the migration of electrons.4 The mechanical property of TSV interconnection such as thermal behavior is important as well as the electrical property including electrical conductivity for improvement TSV performance. Therefore, the nanotwin Cu is proper for the TSV interconnection. In this study, nanotwin Cu was applied to fill into high aspect ratio of via (diameter = 5 µm, depth = 60 µm) with pulse current conditions. The deposition condition between direct current and pulse current was compared to observe the filling characteristics. The mechanical properties as the thermal expansion behavior, which is critical to adopting integrated devices, of nanotwin Cu were investigated. As a result, the results with pulse current condition showed obvious improved the TSV filling property than direct current condition. 1. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012). 2. T. Moffat and D. Josell, Journal of The Electrochemical Society, 159, D208 (2012). 3. L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013). 4. L. Lu, Science, 304, 422-426 (2004).

Reduction of Thermal Stress in Copper TSV due to Annealing by Low TEC Copper

Copper through-silicon via (TSV) is the key technology used in 3D packaging. During the fabrication process, copper TSV is exposed to a high temperature between 400°C and 600°C. For conventional copper TSV, we observed the cracks at the bottom of TSV after annealing at 500°C and a very high copper extrusion height, which destroys the overlying layers above the TSV. We also succeeded to prevent cracks at the bottom of the TSV and reduce the copper extrusion height by using the low thermal expansion coefficient (TEC) copper.

Bottom-up Cu Filling of through-Silicon-Via(TSV) with Single Additive

Downscaling of the Cu interconnection was one of core technologies to enhance the performance of semiconductor devices. However, the shrinkage of Cu interconnection will face the limitation due to the physical limitation of Si based semiconductor device. In order to maintain the development in semiconductor device, the 3D interconnection is emerged, and the through-Si-via(TSV) interconnection is noticed. Large integration, high efficiency and high performance could be realized by composing the 3D integrated circuit with TSV. Furthermore, hetero interconnection between the logic and memory was possible by accepting the TSV technology. The TSV filling process which plating the Cu in the TSV by electrodeposition was one of core process in TSV process due to high cost and difficulty. During the TSV filling process, bottom-up Cu filling which the Cu filled from the bottom of via to the top, should be occurred for avoiding the void formation and decreasing the processing time. In other to achieve the bottom-up filling, various additives were added in the electrolyte. The suppressor inhibited the deposition rate of Cu at the top surface and the sidewall of TSV. The accelerator promoted deposition rate of Cu at the undermost bottom of TSV. Theoretically, the bottom-up filling of TSV was initiated by suppression breakdown at the bottom of TSV.1-3 Simultaneous detachment of suppressor by high potential due to ion depletion at TSV bottom leads focus of current at bottom of TSV. Therefore, bottom-up TSV filling could be achieved by only using the suppressor. Moreover, it was reported that accelerator substitute the suppressor at the sidewall and disturbed the bottom-up filling.3 In this research, the characteristics of suppressor were systematically investigated to achieve the bottom-up Cu filling of TSV with only using the suppressor. The influence of suppressor concentration on the Cu electrodeposition was investigated by observing the CV curves and morphology of Cu deposit. The influence of suppressor concentration and current density on the bottom-up TSV filling had also been observed. Interesting changes in bottom-up TSV filling by changing experimental conditions were delicately analyzed. Finally, the bottom-up TSV filling was achieved with only using the suppressor. This leaded the perfect and fast void free filling of 60 μm deep TSV within 1000 seconds.

Interview

Dr Dingyou Zhang of GLOBALFOUNDRIES talks about her research interests and the paper ‘BMD Impact on Silicon Fin Defect at TSV Bottom’, page 954. Dr Dingyou Zhang As the semiconductor industry strived to scale according to Moore's Law, the conventional planar ICs encountered many physical, technological and economic bottlenecks. 3D integration technology, by stacking and connecting function blocks in a vertical fashion, promises to alleviate such bottlenecks and has been widely investigated in recent years. The potential benefits of 3D integration include multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. Performance improvement in 3D ICs is mainly due to reduction of interconnect length reducing interconnect delay and power consumption. Small form factor is achieved by stacking active device layers on top of one another. During my M.S. and Ph.D. I was working on several research topics related to 3D integration, including TSV thermal-mechanical reliability and a novel chip-to-wafer 3D integration approach. I joined GLOBALFOUNDRIES in 2013 and I am currently working on advanced packaging technologies in the office of the CTO, focusing on through-silicon via (TSV) technology. The TSV is an important enabling component in 3D integration; electrically connecting multiple strata of ICs using short vertical vias that pass through a thinned silicon wafer substrate in order to establish a connection between the active side and backside of the die. Compared to conventional wirebonding and flipchip stacking, TSVs enable high-performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power requirements by providing the shortest interconnect path and higher interconnect density, compactly. However, it is challenging to fabricate reliable TSVs and substantial research is being conducted on aspects including their design, processing materials, metrology development and thermal-mechanical reliability. We report a recently found silicon fin defect at TSV bottom which was identified as a killer defect. To examine the root cause of this defect, we explored different inspection options and finally developed an effective method to catch the defect post TSV deep reactive ion etch. This is compatible with inline inspection and can be easily verified by cross-sectioning the via. With this well-established inspection approach, we were able to further investigate various potential root causes of the defect, such as TSV density microloading, TSV location and photoresist residue impacts. After ruling out other effects, bulk micro defect (BMD) turned out to be a key root cause; based on both BMD simulation and experimental results. Thus a low BMD or non-BMD silicon substrate is recommended to reduce or eliminate this defect. The work provides a viable way to clear this roadblock for TSV manufacturability. This is a killer defect which is hard to detect due to its deep location at the bottom of high aspect ratio vias, it can cause yield loss and requires elimination. We have seen mechanical failures caused by this defect after assembling TSV chips. One example we show is a silicon fin defect at TSV bottom causing copper diffusion into silicon cracks in TSV vicinity, after wafer thinning and TSV backside reveal process. A desirable inspection point for using our SEM automatic process inspection is right after TSV etch. Post etch is the first step in which we found this silicon fin defect and it saves downstream manufacturing resources from processing defective TSVs. Post etch inspection results can be easily verified physically and correlated to silicon fin defects, since TSVs are not filled with metal yet. This inspection approach can be adopted after TSV etch and before photoresist ashing and clean, which has less Q time concerns than between TSV post etch clean and dielectric liner deposition. 3D integration is predicted to be a key technology to solve performance and cost problems of conventional IC fabrication in the ITRS roadmap, which will probably be based on TSV technology. Full 3D process flows have already been demonstrated with no major showstoppers from a design or process point of view. While cost reduction is still on the to-do list for high volume production, multiple equipment and material suppliers are focusing on optimising processes to lower costs. With a positive outlook for commercialisation, a strong demand for such future 3D IC applications including memories and processors is expected in the next few years.

BMD impact on silicon fin defect at TSV bottom

A new type of through-silicon via (TSV) defect, silicon fin defect, which was found after the TSV deep-reactive-ion-etching process at the TSV bottom is reported. These defects are considered killer TSV defects that may cause process or mechanical failures and have to be eliminated. A scanning electron microscope automatic process inspection approach, which is non-destructive and proven to be effective, has been established to image the fin defects at the bottom of the trench. A possible root cause of this defect is also explored. Both simulation and benchmarking test results indicate that bulk micro defects (BMDs) in the silicon substrate could serve as a micro-mask during etching and result in silicon fin defects.

A New Type of TSV Defect Caused by BMD in Silicon Substrate

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this defect is that the bulk micro defect (BMD) in silicon substrate serves as a micro-mask during etching and results in silicon fin defects at TSV bottom. These defects have to be eliminated as they are killer TSV defects for several reasons: (1) could serve as a weak point for isolation liner deposition; (2) could be a weak point for barrier/seed layer deposition; and (3) may cause mechanical failures during TSV backside reveal. Previously, silicon fin defects were removed by switching to a non-BMD silicon substrate for interposer application. However, for TSV integration with FEOL devices, the BMD layer serves as an intrinsic gettering layer for devices, therefore, it cannot be removed from the silicon substrate, which makes it challenging to get rid of silicon fin defects. In order to establish a non-destructive in-line detection method of the fin defects, scanning electron microscope (SEM) automatic process inspection (API) was set up to image the fin defects at the bottom of the trench. A special working point with high depth of focus (DoF) and contrast was created to obtain good top-down SEM imaging of the defects at the bottom of this high-aspect-ratio (HAR) structure. Three types of silicon substrates (A, B, and C) were used for this study to investigate the potential root cause. SEM API results show defect rates of 20%, 3.3% and 0% for substrates A, B, and C, respectively. This is in good agreement with both BMD simulation results and benchmarking data in which substrates A, B, and C had normalized BMD densities of 11.7, 5.74, and 1 cm-3, respectively, with a comparable BMD size of 80~90 nm and a denuded zone (DNZ) depth of 10~15 μm. The correlation between BMD density in a silicon substrate and silicon fin defect rate indicates that BMD is a key root cause for silicon fin defects. To eliminate silicon fin defects, an optimized DRIE process has been developed. On the same type of substrate, the DRIE process with a typical voltage bias results in a defect rate of 6.7%, while no silicon fin defect was detected out of 200 TSVs with a polynomial bias ramp to relatively higher final voltage bias during the last 15 μm etch. The hypothesis is that higher voltage bias is able to sputter away BMD and shows potential to get rid of the silicon fin defects at the TSV bottom. In summary, a capable inspection method, a preferred silicon substrate with BMD spec range, and a promising way for DRIE process optimization to eliminate the silicon fin defect at the TSV bottom have been identified and developed in this work. Detailed results and analysis, particularly the fin defect images, statistical inspection results, BMD benchmarking data, simulation results, and TSV profile with optimized process will be discussed in the paper.