Oxide semiconductors such as indium oxide (In2O3) offer high-electron mobility and low-temperature processability, making them promising candidates for back-end-of-line (BEOL)-compatible logic-in-memory applications. However, direct deposition of high-κ ferroelectric dielectrics (Hf0.5Zr0.5O2; HZO) on oxide channels typically degrades interfacial quality, leading to threshold voltage shifts and unstable polarization due to depolarization fields and defect states. In this work, we leverage advanced membrane transfer techniques to demonstrate a transferable ferroelectric HZO layer for interface-layer-free integration with In2O3. This approach forms a van der Waals-like junction, evidenced by an ∼0.8 nm interfacial gap, which avoids the chemical incompatibilities of conventional gate stack processing while preserving the pristine stoichiometry of the In2O3 channel. The transferred HZO exhibits a dielectric constant of 26 and low leakage current (<10-7 A cm-2 at 1 MV cm-1) while maintaining robust ferroelectric switching. Dual-gate ferroelectric In2O3 transistors achieve a large memory window and stable endurance over 109 cycles. We further integrate these devices into reconfigurable inverter circuits that dynamically switch between NOR and NAND logic functions with tunable voltage transfer characteristics. The ferroelectric thin-film transfer process is fully compatible with silicon back-end-of-line thermal budgets and scalable to wafer-level integration, offering a viable route toward high-density, multifunctional logic-in-memory architectures.

Ferroelectric field-effect transistors (FeFETs) are receiving significant attention as representative next-generation semiconductor devices for neuromorphic computing and in-memory computing. In this study, we present threshold voltage (Vth)-tunable indium gallium zinc oxide (IGZO)/hafnium zirconium oxide (HZO) FeFETs by applying interface dipole engineering using aluminum oxide (Al2O3) and lanthanum oxide (La2O3) as dipole sources. Interface dipoles were formed at the IGZO/HZO interface through thermal diffusion from the source layers, and their effects were systematically investigated through sequential analysis of capacitor and transistor characteristics. The Al-dipole produced a positive Vth shift and a wide memory window (MW) of 2.7 V attributed to trap amplification effects. The La-dipole simultaneously achieved a negative Vth shift, MW enhancement, and device performance improvement attributed to interface oxygen vacancy passivation. The reproducibility and stability of the fabrication process were statistically verified across an ensemble of 42 devices. These results demonstrate that interface dipole engineering enables bidirectional Vth modulation of more than 1.5 V, allowing the provision of various customized devices such as multilevel memory and low-power high-performance logic within a single fabrication process. This study is expected to provide high flexibility to circuit designers for neuromorphic computing and in-memory computing systems design.

Selector-only memory (SOM) based on ovonic threshold switches is a promising candidate for dense cross-point memory by integrating selector and memory functions in a single two-terminal device. However, the physical origins of off-state conduction and threshold voltage (Vth) modulation remain unclear. Here, we investigate these mechanisms in a Te-rich Ge-Sb-Se-Te:Sn SOM by correlating DC transport, low-frequency noise (LFN), and materials analyses. DC I-V characteristics analyzed using Poole-Frenkel (PF) emission and trap-assisted tunneling (TAT) models reveal identical trap energy levels across prefirst firing, low-Vth, and high-Vth states, indicating a common trap species with state-dependent spatial redistribution. LFN measurements distinguish PF- and TAT-dominated regimes and show consistent state-dependent noise behavior. Cross-sectional energy-dispersive X-ray spectroscopy reveals electric-field-polarity-dependent Te redistribution near the top electrode, while ab initio calculations identify Te-Te dimer defects as acceptor-like deep traps governing off-state conduction. These results provide a unified mechanism for Vth modulation in Te-based SOM devices.

In this study, we demonstrate that an atomic-layer-deposited Al2O3dielectric interlayer uniformly covering both the channel and contact regions effectively reduces the Schottky barrier height (SBH) of tellurium (Te) field-effect transistors (FETs), providing a facile strategy to mitigate Fermi-level pinning. An ultrathin 3 nm Al2O3interlayer inserted between the metal electrode and Te channel leads to significantly better electrical performance than that of Te FETs with channel-only Al2O3passivation. Specifically, the drain current density increases by a factor of 2.5, while the hysteresis window of the threshold voltage is reduced from 14.4 to 8.1 V. Transmission line measurements reveal a substantial decrease in contact resistance from 23.9 to 1.47 MΩ·μm, which is attributed to the reduction in SBH from 133 to 49 meV. These results highlight the importance of simultaneous channel and contact interface engineering and establish the Al2O3interlayer as an effective approach for realising reliablep-type Te FETs.

GaN vertical FinFETs have emerged as an increasingly prevalent semiconductor technology for RF and power applications. To fully exploit GaN power transistors, accurate and reliable physics-driven models have been required. An analytical model based on surface potential for vertical GaN FinFETs featuring a submicron fin channel on a GaN substrate is presented, considering the electrostatic influence of a field plate gate. A two-dimensional Poisson equation is analyzed using the parabolic estimation to characterize the electrostatic potential along the fin channel. Thereby, the surface potential model provides insight into the determination of threshold voltage, electrostatic control, and drain current. In addition, an ON-resistance model has also been derived to analyze the device performance. Then, the derived models are compared with the simulated results of a field plate-added stepped gate device obtained from TCAD. The simulated device based on this analytical model provides an ON current of 4 kA/cm2 associated with its specific ON resistance of 0.012 mΩ·cm2. This analytical approach provides a reliable platform for optimizing the electrostatic design of GaN vertical FinFET devices.

ABSTRACT The growing demand for energy-efficient building technologies has accelerated the development of adaptive smart window systems capable of regulating solar radiation and reducing cooling loads. In this study, a self-powered electro-optic smart window based on plasmonic nanomaterial-enhanced nematic liquid crystal (PNLC) was developed for adaptive thermal and optical regulation. Gold nanoparticles (AuNPs) were incorporated into the liquid crystal matrix to enhance dielectric anisotropy and electro-optic responsiveness, while an integrated thin-film photovoltaic (PV) module enabled autonomous operation. The optimised PNLC composition containing 0.05 wt% AuNPs increased dielectric anisotropy from 8.2 to 9.7, resulting in a reduced threshold voltage of approximately 2.3 V. UV – Vis – NIR spectral analysis revealed high visible transparency (~75–78%) and strong near-infrared attenuation, with average NIR transmittance decreasing from approximately 79% to 35–40%, corresponding to an attenuation efficiency of nearly 50–55%. The device exhibited rapid electro-optic switching with a minimum response time of approximately 12 ms at 5.5 Vrms. Under simulated solar irradiation (200–1000 W/m2), the integrated PV module delivered an operating voltage of approximately 3.3 V, enabling self-powered switching. Thermal evaluation showed a surface temperature reduction from 46.7°C to 30.8°C and an indoor heat gain reduction of 54.6%.

Building energy consumption, driven by the escalating demand for cooling, necessitates the development of innovative smart windows capable of dynamic solar modulation and thermal management. Polymer-dispersed liquid crystal (PDLC) devices are promising candidates but are hindered by high driving voltages and a lack of passive radiative cooling capabilities. Herein, we propose a facile strategy to fabricate multifunctional PDLC smart windows by incorporating fluorinated monomers with distinct chemical structures into the polymer matrix. Through the addition of fluorine atoms, the phase separation process was improved, and the matrix surface free energy was decreased. Consequently, the constraint on liquid crystal molecules was significantly alleviated, which led the threshold and saturation voltages to drop to one-third of the values found in the control group. Simultaneously, the strong vibrational absorption of C-F bonds within the 8-13 μm atmospheric transparency window endowed the films with exceptional mid-infrared emissivity (exceeding 0.9), enabling passive radiative cooling without external energy input. Under a solar irradiance of 500 W/m2, the film exhibited a subambient cooling performance of 1.5 °C. The results demonstrated that tailored fluorinated monomers bridge the gap between active electro-optical modulation and passive thermal management, presenting a potential strategy for sustainable building facades.

Bioelectronic devices benefit from materials that have tissue-like levels of softness and good conductive coupling to biological structures. Conventional conjugated polyelectrolyte complexes such as poly(3,4-ethylenedioxythiophene)/poly(styrenesulfonate) (PEDOT/PSS) have favorable levels of mixed ionic-electronic conductivity, but have high elastic stiffness, typically reflected in Young's moduli in the GPa range. Soft ionic conductors, such as ionogels, offer extreme deformability but generally lack the semiconducting mixed ionic-electronic transport required for signal transduction and amplification. Here, we report the first room-temperature liquid semiconducting block copolymer (L-SBCP) that functions as an organic electrochemical transistor (OECT) and enables solvent-free processing. The synthesis of L-SBCP involves the covalent linkage of two unlike polymers: a π-conjugated block bearing glycol side chains and a PEGMEMA bottlebrush acrylic block. This architecture combines mixed ionic-electronic conductivity with the mechanical properties of a viscoelastic liquid. The result is a phase-stable, free-flowing single-component material with a deformability comparable to that of biological cells (1-100 Pa) and a substrate-limited stretchability of 800%. Its liquid rheology supports direct injection and vacuum filling of microchannels without additives or thermal processing. The L-SBCP exhibits p-type accumulation-mode behavior in an organic electrochemical transistor (OECT), with a threshold voltage of +0.08 V, comparable to that of state-of-the-art soft semiconductors. Importantly, L-SBCP supports robust cell viability (>97%). The cellular compatibility opens opportunities for bioelectronic signal amplification at cell-material interfaces enabled by a semiconducting material with cell-scale softness. By uniting biorelevant softness, extreme deformability, electronic performance, and solvent-free processability, L-SBCP establishes a new material composition and form factor for semiconducting polymers and bioelectronic devices.

The electrical performance and driving capability of monolithically integrated oxide thin-film transistor (TFT)-quantum-dot light-emitting diode (QLED) pixels are strongly affected by the dielectric environment formed during backplane-emitter integration. In this study, three interdielectric configurations─single-layer Al2O3, single-layer SiO2, and an Al2O3/SiO2 bilayer─were systematically investigated to elucidate the influence of dielectric composition and interfacial chemistry on the stability of indium-tin-zinc oxide (ITZO) TFTs and QLED driving behavior. Although the Al2O3-only device exhibited the best intrinsic TFT performance, hydrogen diffused into the Al2O3/SiO2 bilayer during the plasma-enhanced chemical vapor deposition of SiO2, which generated donor-like defects in the ITZO channel and negatively shifted the threshold voltage. Nevertheless, the bilayer simultaneously provided superior current leakage suppression and compatibility with the subsequent solution-processed QLED fabrication, enabling stable pixel operation. The bilayer-based TFT achieved a mobility of 24.82 cm2 V-1 s-1, a subthreshold swing of 0.09 V dec-1, and an on/off ratio of 8.78 × 109. When used to drive InP QLEDs, the integrated pixel reached a peak luminance of 9,488.8 cd m-2, a maximum current density of 285.3 mA cm-2, and an external quantum efficiency of 7.15%, while maintaining an unchanged electroluminescence spectrum when driven by TFTs. These results demonstrate that interdielectric layer engineering, particularly the balance between hydrogen-induced voltage threshold shifts and process robustness, is critical for achieving reliable monolithic TFT-QLED operation for next-generation active-matrix display technologies.

Abstract Current-voltage (I−V) characteristics of the npn structures used in vertical GaN trench metal-insulator-semiconductor field effect transistors (MOSFETs) were measured and analyzed. The shape of the measured I−V curves was found to be similar to the reverse I−V characteristics of the GaN p-n diodes. By analyzing the results using simulations, the I−V characteristics could be explained by band-to-band tunneling and the avalanche breakdown. The estimated acceptor concentrations by comparing the measured and the simulated I−V curves were relatively high, suggesting that the low threshold voltage of the GaN trench MOSFETs is not due to insufficient activation of Mg.

Gallium nitride semiconductors are essential for advanced electronics, but realizing their potential requires robust normally-off devices. The P-GaN gate high-electron-mobility transistor is the dominant architecture, yet its threshold voltage is restricted to less than 2 volts by the low activation efficiency of magnesium acceptors. Here, we demonstrate atomically confined insertion to overcome this bottleneck. This technique creates self-terminating, two-dimensional magnesium layers within a complex heterostructure, inducing localized strain and polarity inversion. The resulting atomic-scale polarization fields increase the average effective hole concentration several-fold. When integrated into a P-GaN gate high-electron-mobility transistor, atomically confined insertion boosts the threshold voltage from 1.5 to 4.3 volts while mitigating the degradation in transconductance and output current typical of conventional methods. Furthermore, this approach substantially suppresses the current collapse effect via an efficient vertical hole injection mechanism. This work establishes atomic-scale field engineering as a viable axis for performance control and optimization in semiconductor devices.

This study presents a compact neuron device based on a PN heterojunction neuron to enable hardware-level deep neural networks (HDNNs) with improved integration density beyond the limits of complementary metal-oxide-semiconductor (CMOS) neuron circuits. By systematically analyzing the energy-band structure, diode parameters, and dominant conduction mechanisms, the physical origin of the intrinsic thresholding behavior in the PN heterojunction neuron is identified. As a hardware neuron device, the PN heterojunction neuron exhibits rectification and nonlinear activation characteristics, while the threshold voltage (Vth) is 2.49 V and the rectification ratio (RR, ratio of current at ±3 V) is 104, allowing the direct implementation of the rectified linear unit (ReLU) function at the device level. The PN heterojunction neuron reliably receives and processes summed currents from synapse devices, demonstrating accurate ReLU operation, where linear signal transmission occurs only when the total synaptic conductance (Gtot) exceeds 110 nS, while no signal is transmitted below 110 nS. Furthermore, by integrating the PN heterojunction neuron with a commercial transistor, signal propagation across multiple layers is attained, confirming compatibility with multilayer HDNNs. Owing to its simple structure, intrinsic nonlinearity, and high scalability, the PN heterojunction neuron provides an effective solution to the area and complexity challenges of CMOS-based neuron implementations and exhibits strong potential for highly integrated and energy-efficient HDNNs.

Monolithic 3D integration of oxide thin-film transistors provides an approach to continue Moore's Law. Crystalline indium oxide (In2O3) is particularly attractive owing to its high electron mobility and low contact resistance. However, its practical deployment is hindered by the difficulty of fabricating crystalline In2O3 under BEOL-compatible conditions and by the intrinsic instability of surface oxygen. In this work, we demonstrate an atomic-layer-deposition-enabled stabilization strategy that simultaneously achieves high mobility, strong electrostatic control, and exceptional stability in crystalline In2O3 transistors. The afforded devices exhibit a high electron mobility of 92.8 cm2/V·s, a positive threshold voltage of 0.67 V, a steep subthreshold swing of 64.5 mV/dec, and fairly small threshold voltage shifts of -5.6 and 18.6 mV under negative- and positive-bias stress, respectively. Furthermore, the devices show good resistance to forming gas annealing, with small threshold voltage shifts and no degradation in subthreshold swing or on-current. This work not only provides valuable insight into the origin of instability for crystalline oxide semiconductors, but also demonstrates a practical fabrication approach at CMOS BEOL-compatible temperatures to achieve both high performance and high stability for oxide transistors, thereby highlighting the high promise of indium oxide transistors for advanced M3D integration.

This paper investigates the impact of heavy ion irradiation on the inverse piezoelectric effect in p-GaN HEMT devices. Heavy ion irradiation introduces donor-type defects in the p-GaN layer and acceptor-type defects in the AlGaN barrier and at the AlGaN/GaN interface, leading to a positive shift in threshold voltage (Vth), reduced transconductance (Gm), and increased on-resistance (RDS(on)). During subsequent inverse piezoelectric stress, the pre-existing donor-type defects locally modulate the electric field distribution, resulting in a lower electric field strength acting on the barrier layer in the irradiated devices compared to the unirradiated ones. This leads to a reduction in the generation of acceptor defects during the inverse piezoelectric process, and finally the parameters variations in irradiated devices after the inverse piezoelectric test is smaller than that subjected solely to the inverse piezoelectric effect.

Multimode GaN transistors achieve multimodality by exploiting a broadly tunable and ultrawide threshold voltage (VTH) that covers both depletion-mode (D-mode) and enhancement-mode (E-mode) operation. This VTH tunability is enabled by epitaxial growth of ultrathin AlN barriers with high interface quality and strong electrostatic control, combined with tensile stress introduced by PECVD-SiN passivation. Through stress-strain-polarization coupling (SSPC), strain along [0001] approaching -4.2% was generated, which increased the 2DEG density by more than 1 order of magnitude and thus enabled an ultrawide VTH window. The evolution among background-carrier, MOS-like, and D/E-mode high-electron mobility transistor (HEMT) conduction modes under different passivation thickness (PT) was further clarified by simulations, accounting for the observed multimode behavior. SSPC was thus supported as a compact and low-damage method for etch-free tuning of polarization, carrier density, and VTH. The continuously tunable conduction modes provide multimode GaN transistors multiple functionalities, enabling applications in RF amplification, multimode neuromorphic computing, efficient power conversion, and complex circuit optimization.

In the quest for advanced resistive memory devices, the rational design of π-conjugated small molecules is increasingly recognized as an effective approach to achieving high-performance, non-volatile data storage. Herein, we report the design and synthesis of a series of D-A-D' and D-π-A-π-D' type molecules featuring dibenzothiophene sulfone as the central acceptor, marking its debut application in organic resistive memory device applications. The molecules were unsymmetrically functionalized through the incorporation of different donor units such as tert- butylphenyl, triphenylamine, and methoxyphenyl units. Furthermore, the incorporation of acetylene bridges enhanced π-conjugation and facilitated intramolecular charge transfer. Photophysical and electrochemical studies revealed intramolecular charge-transfer characteristics and band gap values in the range of 3.0-3.8eV. All fabricated devices displayed non-volatile binary WORM memory behavior with ON/OFF ratios up to 104, low threshold voltages as low as -1.52V, and substantial stability over 100 cycles with retention time of 4000s. Notably, asymmetric compounds containing triphenylamine donor exhibited superior memory performance. Density functional theory studies further validated the proposed charge transfer and charge trapping mechanism. These results establish dibenzothiophene sulfone-based donor-acceptor systems as promising candidates for next-generation organic memory technologies.

HighlightsThe present manuscript deals with the investigation of self-heating effect in sophisticated nanosheet FETs such as TreeFETs and HS TreeFETs using calibrated TCAD simulation setup.The rise in temperature adversely affects device performance by diminishing carrier mobility, altering the threshold voltage, and elevating output conductance, so impairing both DC and analog/RF performance.The proposed H-shaped channel TreeFET design enhances thermal management through improved heat dissipation.The better thermal performance alleviates the detrimental impacts of self-heating.HS TreeFET based CS amplifier has better SHE stability compared to TreeFET based Cs amplifier.

Low-invasive condition monitoring of liquid-cooled power semiconductors

In this information era, the escalating demand for memory, coupled with the emergence of three-dimensional (3D) memory architectures, has made the suppression of leakage current in high-density arrays a critical challenge. The ovonic threshold switch (OTS) is a key component of 3D phase-change memory (PCM), and Te-rich OTS materials are highly promising due to their low threshold voltage and fast switching speed. Te-rich chalcogenides are promising OTS materials due to their low threshold voltage and fast switching speed. However, using conventional atomic layer deposition (ALD) it is highly challenging to achieve sufficient atomic intermixing in these high-Te-content materials, often resulting in phase separation and compromised device performance. This study introduces a coordinated sub-cycle modulation (CSM) strategy to overcome this barrier. By synchronizing the GeTe/Te sub-cycle ratio with interfacial diffusion kinetics, we achieved the ALD of GeTe9 films with atomic-level homogeneity and an amorphous structure. The fabricated OTS devices demonstrate outstanding integrated performance: a high off-state resistance of 107 Ω, an ultra-fast switching speed of 4 ns, and excellent cycle endurance exceeding 109 cycles. This study not only provides a viable selector solution for 3D memory but also establishes CSM as a generalizable paradigm for synthesizing extreme-ratio, non-stoichiometric functional materials via ALD.

Effortless and controllable electrical amplification in single-PMOS sensor for chemical and biological sensing.