Threshold Circuits Research Articles

Realization of digital optical matrix-vector multiplication

A new matrix-vector multiplication technique is proposed where free-space optical interconnections are used. The multiplication is carried out by a convolution technique where one set of numbers (multiplicands) is represented by the on/off states of light sources and the other sets of numbers (the multiplier) are recorded in matrix form on a spatial light modulator. The partial products are recorded on a detector array which, when added by a microprocessor, yield the respective convolution coefficients. No analogue to digital conversion electronics are necessary in the proposed technique and instead only a thresholding circuit is used. Compared to other existing techniques, the processing time is also reduced in the proposed system.

Toward Massively Parallel Design of Multipliers

Current efficient multipliers have computation delays that increase as O(log n), where n is the number of bits in the inputs. In fact, this asymptotic time complexity for multiplication cannot be improved if the fan-in of the circuits is bounded above by a constant independent of n. In this paper, we study the potential gain in the speed of arithmetic computation provided by massive parallelism (i.e., unbounded fan-in/fan-out) and examine the tradeoffs between the speed and the amount of hardware in large but restricted fan-in threshold circuits. Threshold circuits are chosen because the potential speed-up in AND-OR circuits for multiplication is minimal even if the fan-in is allowed to be arbitrarily large. It is well known in complexity theory that any arbitrary fan-in AND-OR circuit for multiplication of two n-bit integers must have ω(log n/log log n) computation delays if the circuit size is bounded by a polynomial in n. Threshold circuits, on the other hand, are more powerful and we present here threshold circuits for multiplication with fan-in bounded by m, size O(2 − d/2 n 2 m 1/(2 d −1) [formula]), and depth O( d log n/log m) for every fixed integer d > 0. Similar results are also shown for symmetric functions such as the parity. With the rapid advance of VLSI technology and the promise of large scale implementations of cheap and reliable threshold gates, our results could be used for the design of massively parallel high-speed multipliers.

On the VC-dimension of depth four threshold circuits and the complexity of Boolean-valued functions

We consider the problem of determining the VC-dimension δ 3( h) of depth four n-input 1-output threshold circuits with h elements. Best known asymptotic lower bounds and upper bounds are proved, that is, when h → ∞, δ 3( h) is upper bounded by (( h 2 3 ) + nh)(log h)(1 + o(1)) and lower bounded by ( 1 2 )(( h 2 4 ) + nh)(log h)(1 − o(1)) . We also consider the problem of determining the complexity C 3( N)( c 3( N)) of Boolean functions defined on N-pointsets of vertices of n-dimensional hypercube (Boolean-valued functions defined on N-pointsets in R n , respectively), measured by the number of threshold elements, with which we can construct a depth four circuit to realize the functions. We also show the best known upper and lower bounds, that is, when N → ∞, C 3( N) is upper bounded by √32( N log N )(1 + o(1)) and lower bounded by √6( N log N )(1 − o(1)) and c 3( N) is upper bounded by √16( N log N )(1 + o(1)) + 4n 2 − 2n and lower bounded by √6( N log N )(1 − o(1)) + ( 9 4 )n 2 − ( 3 2 )n .

Monolithic integration of optoelectronicsmart pixels

An AlGaAs/GaAs layer structure, grown in a single step, and a fabrication process has been developed for the monolithic integration of cascadable optoelectronic smart pixels. Metal semiconductor field-effect transistors (MESFETs), light-emitting diodes (LEDs) and photodiodes (PDs) are used for the integration. As an example a threshold circuit consisting of a dual-photodiode input and a current balanced output containing an LED is presented. The circuit shows a switching energy of 2 pJ and a minimum switching power of 3 nW. The maximum light output of the LED is 30 mW with a contrast ratio > 1000. The overall power dissipation is 15 mW.

Approximating Threshold Circuits by Rational Functions

Motivated by the problem of understanding the limitations of threshold networks for representing boolean functions, we consider size-depth trade-offs for threshold circuits that compute the parity function. Using a fundamental result in the theory of rational approximation, we show how to approximate small threshold circuits by rational functions of low degree. We apply this result to establish an almost optimal lower bound of Ω(n2/ln2n) on the number of edges of any depth-2 threshold circuit with polynomially bounded weights that computes the parity function. We also prove that any depth-3 threshold circuit with polynomially bounded weights requires Ω(n1.2/ln5/3n) edges to compute parity. On the other hand, we give a construction of a depth d threshold circuit that computes parity with n1+1/Θ(φd) edges where φ = (1 + √5)/2 is the golden ratio. We conjecture that there are no linear size bounded depth threshold circuits for computing parity.

Depth Reduction for Circuits of Unbounded Fan-in

We prove that constant depth circuits of size nlogO(1)n over the basis AND, OR, PARITY are no more powerful than circuits of this size with depth four. Similar techniques are used to obtain several other depth reduction theorems; in particular, we show every set in AC0 can be recognized by a family of depth-three threshold circuits of size nlogO(1)n. The size bound nlogO(1)n is optimal when considering depth reduction over AND, OR, and PARITY. Most of our results hold for both the uniform and the nonuniform case.

On Optimal Depth Threshold Circuits for Multiplication and Related Problems

Let $\widehat{LT}_d$ denote the class of functions that can be computed by depth-$d$ threshold circuits with polynomial size and polynomially bounded integer weights. Using the results in [M. Goldman, J. Hastad, and A. Razborov, in Proc. 7th Annual Conference on Structure in Complexity Theory], [M. Goldman and M. Karpinski, Constructing depth d+1 majority circuits that simulate depth d threshold circuits, unpublished] we show that multiple sum is in $\widehat{LT}_2$, and multiplication and division are in $\widehat{LT}_3$. Moreover, it follows from the lower-bound results in [A. Hajnal et al., IEEE Sympos. Foundations of Comput. Sci., 28 (1987), pp. 99--110], [T. Hofmeister and P. Pudlak, Forschungbericht Nr. 477 Uni Dortmund, 1992] that these threshold circuits are optimal in circuit depth. The authors also indicate that these techniques can be applied to construct polynomial-size depth-3 threshold circuits for powering and depth-4 threshold circuits for multiple product.

Lower bounds on threshold and related circuits via communication complexity

Using communication complexity concepts and techniques, we derive linear (/spl Omega/(n)) and almost-linear (/spl Omega/(n/logn)) lower bounds on the size of circuits implementing certain functions. Our approach utilizes only basic features of the gates used, hence the bounds hold for general families of gates of which the symmetric and threshold gates are special cases. Each of the bounds derived is shown to be tight for some functions and some applications to threshold circuit complexity are indicated. The results generalize and in some cases strengthen recent results. >

Some results on uniform arithmetic circuit complexity

We introduce a natural set of arithmetic expressions and define the complexity class AE to consist of all those arithmetic functions (over the fieldsF 2n) that are described by these expressions. We show that AE coincides with the class of functions that are computable with constant depth and polynomial-size unbounded fan-in arithmetic circuits satisfying a natural uniformity constraint (DLOGTIME-uniformity). A 1-input and 1-output arithmetic function over the fieldsF2n may be identified with ann-input andn-output Boolean function when field elements are represented as bit strings. We prove that if some such representation is X-uniform (where X is P or DLOGTIME), then the arithmetic complexity of a function (measured with X-uniform unbounded fan-in arithmetic circuits) is identical to the Boolean complexity of this function (measured with X-uniform threshold circuits). We show the existence of a P-uniform representation and we give partial results concerning the existence of representations with more restrictive uniformity properties.

Cryptographic limitations on learning Boolean formulae and finite automata

In this paper, we prove the intractability of learning several classes of Boolean functions in the distribution-free model (also called the Probably Approximately Correct or PAC model) of learning from examples. These results are representation independent , in that they hold regardless of the syntactic form in which the learner chooses to represent its hypotheses. Our methods reduce the problems of cracking a number of well-known public-key cryptosystems to the learning problems. We prove that a polynomial-time learning algorithm for Boolean formulae, deterministic finite automata or constant-depth threshold circuits would have dramatic consequences for cryptography and number theory. In particular, such an algorithm could be used to break the RSA cryptosystem, factor Blum integers (composite numbers equivalent to 3 modulo 4), and detect quadratic residues. The results hold even if the learning algorithm is only required to obtain a slight advantage in prediction over random guessing. The techniques used demonstrate an interesting duality between learning and cryptography. We also apply our results to obtain strong intractability results for approximating a generalization of graph coloring.

Design of residue generators and multioperand adders modulo 3 built of multioutput threshold circuits

A generator modulo 3 (mod 3) is a circuit that generates a residue mod 3 from a binary vector. It is used to build the encoding and checking circuitry for arithmetic codes with the check base A=3, i.e. residue codes mod 3 and the 3N code, and some residue number system hardware. In this paper we propose a new approach to designing high-speed and cost-effective generators mod 3 whose special case are multioperand adders mod 3. For any number of inputs n, a family of generators mod 3 can be built of multioutput threshold circuits followed by some merging network. The new generators are shown to be the least complex and the fastest circuits currently known. They also enjoy a modular and highly regular structure composed of gates with low fan-in which makes them attractive for VLSI implementation.

The minimal test set for multioutput threshold circuits implemented as sorting networks

It is shown that an n-input sorting network (SN) can be used to implement an n-variable symmetric threshold functions using the least amount of hardware. An algorithm to derive Boolean functions implemented on any line of any n-input threshold circuit T/sup n/ implemented as a SN is given. A heuristic procedure for generating the minimal test set for any threshold circuit T/sup n/ implemented as a Batcher's SN or any other SN is presented. The number of tests required to detect all stuck-at faults in an n-input SN is determined. A highly regular structure using only one type of simple cell and a suitability for low-level pipelining are other advantages of the circuit T/sup n/. The circuit T/sup n/ can be used as a basic building block of various circuitry supporting the use of all known unidirectional error detecting codes. >

Optimal lower bounds on the depth of polynomial-size threshold circuits for some arithmetic functions

Depth 3 is necessary for threshold circuits of polynomial size to compute squaring, powering, inversion or division. These lower bounds are optimal since they match existing upper bounds.

Depth efficient neural networks for division and related problems

An artificial neural network (ANN) is commonly modeled by a threshold circuit, a network of interconnected processing units called linear threshold gates. It is shown that ANNs can be much more powerful than traditional logic circuits, assuming that each threshold gate can be built with a cost that is comparable to that of AND/OR logic gates. In particular, the main results indicate that powering and division can be computed by polynomial-size ANNs of depth 4, and multiple product can be computed by polynomial-size ANNs of depth 5. Moreover, using the techniques developed, a previous result can be improved by showing that the sorting of n n-bit numbers can be carried out in a depth-3 polynomial-size ANN. Furthermore, it is shown that the sorting network is optimal in depth. >

Limiting Negations in Constant Depth Circuits

It follows from a theorem of Markov that the minimum number of negation gates in a circuit sufficient to compute any Boolean function on n variables is $l = \lfloor {\log n} \rfloor + 1$. It can be shown that, for functions computed by families of polynomial size, $O(\log n)$ depth and bounded fan-in circuits $(NC^1 )$, the same result holds: on such circuits l negations are necessary and sufficient. In this paper it is proven that this situation changes when polynomial size circuit families of constant depth are considered: l negations are no longer sufficient. For threshold circuits it is proven that there are Boolean functions computable in constant depth $(TC^0 )$ such that no such threshold circuit containing $o(n^\epsilon )$, for all $\epsilon > 0$, negations can compute them. There is a matching upper bound: for any $\epsilon > 0$, everything computable by constant depth threshold circuits can be computed by constant depth threshold circuits using $n^\epsilon $ negations asymptotically. There are also tight bounds for constant depth, unbounded fan-in circuits $(AC^0 ):{n / {\log ^r }}n$, for any r, negations are sufficient, and $\Omega ({n / {\log ^r n}})$, for some r, are necessary.

Threshold circuits of bounded depth

We examine a powerful model of parallel computation: polynomial size threshold circuits of bounded depth (the gates compute threshold functions with polynomial weights). Lower bounds are given to separate polynomial size threshold circuits of depth 2 from polynomial size threshold circuits of depth 3 and from probabilistic polynomial size circuits of depth 2. With regard to the unreliability of bounded depth circuits, it is shown that the class of functions computed reliably with bounded depth circuits of unreliable ∨, ∧, ¬ gates is narrow. On the other hand, functions computable by bounded depth, polynomial-size threshold circuits can also be computed by such circuits of unreliable threshold gates. Furthermore we examine to what extent imprecise threshold gates (which behave unpredictably near the threshold value) can compute nontrivial functions in bounded depth and a bound is given for the permissible amount of imprecision. We also discuss threshold quantifiers and prove an undefinability result for graph connectivity.

Nω(log n) lower bounds on the size of depth-3 threshold cicuits with AND gates at the bottom

We present a function in ACC 0 such that any depth-3 threshold circuit which computes this function and has AND gates at the bottom must have size n ω(log n ).

On read-once threshold formulae and their randomized decision tree complexity

TC 0 is the class functions computable by polynomial-size, constant-depth formulae with threshold gates. Read-once TC 0 ( RO- TC 0) is the subclass of TC 0 which restricts every variable to occur exactly once in the formula. Our main result is a (tight) linear lower bound on the randomized decision tree complexity of any function in RO-TC 0. This relationship between threshold circuits and decision trees bears significance on both models of computation. Regarding decision trees, this is the first class of functions for which such a strong bound is known. Regarding threshold circuits, it may be considered as a possible first step towards proving TC 0 ≠ NC 1; generalizing our lower bound to all functions in TC 0 would establish this separation. Another structural result we obtain is that a read-once threshold formula uniquely represents the function it computes.

CMOS multiple-valued logic design. I. Circuit implementation

A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On Threshold Circuits and Polynomial Computation

A Threshold Circuit consists of an acyclic digraph of unbounded fanin, where each node computes a threshold function or its negation. This paper investigates the computational power of Threshold Circuits. A surprising relationship is uncovered between Threshold Circuits and another class of unbounded fanin circuits which are denoted Finite Field Z P ( n ) Circuits, where each node computes either multiple sums or products of integers modulo a prime P ( n ). In particular, it is proved that all functions computed by Threshold Circuits of size S ( n ) &#x2265 n and depth D(n) can also be computed by Z P(n) Circuits of size O ( S ( n ) log S ( n ) + nP ( n ) log P ( n )) and depth O ( D ( n )). Furthermore, it is shown that all functions computed by Z P ( n ) Circuits of size S ( n ) and depth D ( n ) can be computed by Threshold Circuits of size O ((1/&#x2208 2 )( S ( n ) log P ( n )) 1+&#x2208 ) and depth O ((1/&#x2208 5 ) D ( n )). These are the main results of this paper. There are many useful and quite surprising consequences of this result. For example, an integer reciprocal can be computed in size n O (1)M and depth O (1). More generally, any analytic function with a convergent rational polynomial power series (such as sine, cosine, exponentiation, square root, and logarithm) can be computed within accuracy 2 -nc , for any constant c , by Threshold Circuits of polynomial size and constant depth. In addition, integer and polynomial division, FFf, polynomial interpolation, Chinese Remaindering, all the elementary symmetric functions, banded matrix inverse, and triangular Toeplitz matrix inverse can be exactly computed by Threshold Circuits of polynomial size and constant depth. All these results and simulations hold for polytime uniform circuits. This paper also gives a corresponding simulation oflogspace uniform Z P ( n ) Circuits by logspace uniform Threshold Circuits requiring an additional multiplying factor of O (log log log P ( n ) depth. Finally, purely algebraic methods forlowerbounds for ZP(n) Circuits are developed. Using degree arguments, a Depth Hierarchy Theorem for Z P ( n ) Circuits is proved: for any S ( n ) &#x2265 n , D ( n ) = O ( S ( n ) c' ) for some constant c' P ( n ) where 6( S ( n )/ D ( n )) D ( n ) P ( n ) c' 2 n , there exist explicitly constructible functions computable by Z P ( n ) Circuits of size S ( n ) and depth D ( n ), but provably not computable by Z P ( n ) Circuits of size S ( n ) c and depth o D ( n )) for any constant c &#x2265 1.