Thread Management Research Articles

Automatic Parallelism Management

On any modern computer architecture today, parallelism comes with a modest cost, born from the creation and management of threads or tasks. Today, programmers battle this cost by manually optimizing/tuning their codes to minimize the cost of parallelism without harming its benefit, performance. This is a difficult battle: programmers must reason about architectural constant factors hidden behind layers of software abstractions, including thread schedulers and memory managers, and their impact on performance, also at scale. In languages that support higher-order functions, the battle hardens: higher order functions can make it difficult, if not impossible, to reason about the cost and benefits of parallelism. Motivated by these challenges and the numerous advantages of high-level languages, we believe that it has become essential to manage parallelism automatically so as to minimize its cost and maximize its benefit. This is a challenging problem, even when considered on a case-by-case, application-specific basis. But if a solution were possible, then it could combine the many correctness benefits of high-level languages with performance by managing parallelism without the programmer effort needed to ensure performance. This paper proposes techniques for such automatic management of parallelism by combining static (compilation) and run-time techniques. Specifically, we consider the Parallel ML language with task parallelism, and describe a compiler pipeline that embeds "potential parallelism" directly into the call-stack and avoids the cost of task creation by default. We then pair this compilation pipeline with a run-time system that dynamically converts potential parallelism into actual parallel tasks. Together, the compiler and run-time system guarantee that the cost of parallelism remains low without losing its benefit. We prove that our techniques have no asymptotic impact on the work and span of parallel programs and thus preserve their asymptotic properties. We implement the proposed techniques by extending the MPL compiler for Parallel ML and show that it can eliminate the burden of manual optimization while delivering good practical performance.

ChamelIoT: a tightly- and loosely-coupled hardware-assisted OS framework for low-end IoT devices

The evergrowing Internet of Things (IoT) ecosystem continues to impose new requirements and constraints on every device. At the edge, low-end devices are getting pressured by increasing workloads and stricter timing deadlines while simultaneously are desired to minimize their power consumption, form factor, and memory footprint. Field-Programmable Gate Arrays (FPGAs) emerge as a possible solution for the increasing demands of the IoT. Reconfigurable IoT platforms enable the offloading of software tasks to hardware, enhancing their performance and determinism. This paper presents ChamelIoT, an agnostic hardware operating systems (OSes) framework for reconfigurable IoT devices. The framework provides hardware acceleration for kernel services of different IoT OSes by leveraging the RISC-V open-source instruction set architecture (ISA). The ChamelIoT hardware accelerator can be deployed in a tightly- or loosely-coupled approach and implements the following kernel services: thread management, scheduling, synchronization mechanisms, and inter-process communication (IPC). ChamelIoT allows developers to run unmodified applications of three well-established OSes, RIOT, Zephyr, and FreeRTOS. The experiments conducted on both coupling approaches consisted of microbenchmarks to measure the API latency, the Thread Metric benchmark suite to evaluated the system performance, and tests to the FPGA resource consumption. The results show that the latency can be reduced up to 92.65% and 89.14% for the tightly- and loosely-coupled approaches, respectively, the jitter removed, and the execution performance increased by 199.49% and 184.85% for both approaches.

Performance analysis of parallel programming models for C++

As multicore processors become more common in today’s computing systems and parallel programming models are enriched, programmers must consider how to choose the appropriate and parallel programming model when writing parallel code. The purpose of this paper is to compare and analyze the performance gap between different C++ parallel programming models, such as C++ standard library threads, OpenMP and Pthreads, in terms of matrix operations. The experiments use different libraries to implement matrix multiplication separately and then analyze their performance. The experimental data show that the data size has a significant impact on the performance of the different models. For very small matrices of size magnitude less than or close to the number of threads, the performance of parallel implementations is much lower than that of serial implementations. For small matrices with magnitudes larger than the number of threads, the C++ standard library threads outperforms Pthreads and OpenMP due to its lightweight thread performance on relatively small matrices. pthreads shows the best performance on very large matrices due to its fine-grained control over thread management, communication, and synchronization operations. openMP’s is not as stable as the other two libraries, especially for smaller matrices. This paper provides a comparative analysis that can help programmers choose the most appropriate library for their specific computational needs.

NoC-based hardware software co-design framework for dataflow thread management

Applications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In a dataflow execution environment, a thread can run only if all its required inputs are available. While the potential benefits are large, it is not trivial to improve resource utilization and energy efficiency by focusing on dataflow thread execution models (i.e., the ways specifying how the threads adhering to a dataflow model of computation execute on a given compute/communication architecture). This paper proposes and implements a hardware-software co-design-based dataflow threads management framework. It works at the Network-on-Chip (NoC) level and consists of three stages. The first stage focuses on a fast and effective thread distribution policy. The next stage proposes an approach that adds reconfigurability to a 2D mesh NoC via customized instructions to manage the dataflow thread distribution. Finally, a 2D mesh and ring-based hybrid NoC is proposed for better scalability and higher performance. This work can be considered a primary reference framework from which extensions can be carried out.

Privacy-Preserving Content-Based Similarity Detection Over in-the-Cloud Middleboxes

It is increasingly popular for cloud providers to offer middlebox service that supports content-based similarity detection for enterprises. However, redirecting network traffic to the cloud for such service raises security concerns. While trusted execution environments such as Intel SGX have emerged as a pragmatic solution for designing secure in-the-cloud middleboxes, it remains challenging to practically support content-based similarity detection. In this paper, we design a secure in-the-cloud middlebox system that can detect content-based similar flows in encrypted traffic dynamically. To cope with the constrained enclave memory, we adopt the caching technique and devise a compact index to increase the cache hit rate for effective similarity detection inside the enclave. We also present a parallel algorithm for performance speedup, with an efficient enclave thread management mechanism. Extensive evaluations demonstrate that the overhead of our system compared to native processing (without SGX) is limited to 2.1 <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex>$\times$</tex></formula> . Meanwhile, our tailored design can achieve up to <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex>$14.4\times$</tex></formula> better computational efficiency compared to simply moving the target functionality to the SGX enclave via existing popular library operating systems like Graphene-SGX and Occlum. Our secure system can achieve a normalized similarity detection precision of about 90%.

Proposing the application of a deep learning model to detect the malicious IP address of botnet in the computer network

Abstract— Malware in general and botnets in particular are big threats to cybersecurity. They have many sophisticated methods to bypass security systems to infect computers and perform attacks, sabotage, or spying activities. Botnet detection solutions are always focused on and solved by scientists and cybersecurity specialists. The DGA botnet is a group of common botnet families that share the same mechanism of needing to connect back to the C&amp;C server via DNS to receive commands to operate. Many studies that propose algorithms for detecting and classifying DGA botnets have been proposed and tested with high results. In this study, we approach by using the above solutions to detect malicious IP addresses and botnet malware families. First, we evaluate the efficiency of two deep learning models LA_Bin07 and LA_Mul07 on a new specialized dataset, UTL_DGA22. Next, we extended the experiment with the ISCX-Bot-2014 dataset. The results show that LA_Bin07 and LA_Mul07 models both get high accuracy on the new dataset, with 0.98 and 0.86 correspondingly. Experimenting on the reality dataset also gives positive results, helping network administrators to localize malicious IP addresses for deeper investigation. The proposed solution is effective enough to be applied as a module in cybersecurity solutions such as firewalls, intrusion detection, and prevention systems or unified thread management - UTM.

CUDA implementation of the antlion optimization algorithm

A parallel version of Ant Lion Optimizer algorithm using the CUDA platform is introduced in this paper. Efficient kernel, memory and thread management approaches have been developed to maximize its performance. The new algorithm was tested against the canonical algorithm on 15 scalable problems of different sizes, with a total of 172 experiments. The solution costs and the execution times were compared using relative percentage difference and significance tests. The results showed the CUDA antlion algorithm significantly improves upon the execution time, while retaining the same solution quality.

Symbiotic Organisms Search Optimization to Predict Optimal Thread Count for Multi-threaded Applications

Multicore systems have emerged as a cost-effective option for the growing demands for high-performance, low-energy computing. Thread management has long been a source of concern for developers, as overheads associated with it reduce the overall throughput of the multicore processor systems. One of the most complex problems with multicore processors is determining the optimal number of threads for the execution of multithreaded programs. To address this issue, this paper proposes a novel solution based on a modified symbiotic organism search (MSOS) algorithm which is a bio-inspired algorithm used for optimization in various engineering domains. This technique uses mutualism, commensalism and parasitism behaviours seen in organisms for searching the optimal solutions in the available search space. The algorithm is simulated on the NVIDIA DGX Intel-Xeon E5-2698-v4 server with PARSEC 3.0 benchmark suit. The results show that keeping the thread count equal to the number of processors available in the system is not necessarily the best strategy to get maximum speedup when running multithreaded programs. It was also observed that when programs are run with the optimal thread count, the execution time is substantially decreased, resulting in energy savings due to the use of fewer processors than are available in the system.

GPU-Based Real-Time Software Coincidence Processing for Digital PET System

In some modern digital positron emission tomography (PET) systems, the coincidence pairs are extracted by software coincidence processing (SCP) for reconstruction. The SCP is typically implemented on central processing units (CPUs) and then it is accelerated by CPU multithreading technology. However, the more detection modules a PET system has, the more CPU threads are used in acquisition and the fewer threads are available in coincidence processing when the number of threads is fixed. This phenomenon results in reduced processing performance of CPU-based SCP, which limits the application of SCP. In this article, we propose low-cost GPU-based real-time SCP (GPU-SCP) methods to solve the limited CPU thread problem. The proposed processing architecture simplifies the management of threads between acquisition and coincidence processing, leading to the decouple of acquisition and coincidence, accelerates the coincidence processing by GPU multiple threads, and finally realizes the online coincidence processing in high-sensitivity digital PET systems with 20 basic detection modules (BDMs). To evaluate the performance of the proposed GPU-based SCP approaches, we adapted them to the home-made PET systems with different architectures. The speedup experimental results show that the proposed sorting-based GPU-SCP achieves up to ~15 times average speedup on GTX1070 compared with serial CPU algorithms, which is comparable to the parallel CPU algorithm with 30 threads. Besides, the proposed combination-based GPU-SCP is superior to the sorting-based GPU-SCP for a specific system architecture. Besides, the image quality experiments indicate the reconstruction images processed by GPU-SCPs are almost the same as the ground truth (differences ~1% in the image domain).

MMEDD: Multithreading Model for an Efficient Data Delivery in wireless sensor networks

Nowadays, the use of Wireless Sensor Networks (WSNs) is increasingly growing as they allow a large number of applications. In a large scale sensor network, communication among sensors is achieved by using a multihop communication. However, since the sensor is limited by its resources, sensors' operating systems are developed in order to optimize the management of these resources, especially the power consumption. Therefore, the hybrid operating system Contiki uses a low consumption layer called Rime which allows sensors to perform multihop sending with a low energy cost. This is favored by the implementation of lightweight processes called protothreads. These processes have a good efficiency/consumption ratio for monolithic tasks, but the management of several tasks remains a problem. In order to enable multitasking, Contiki provides to users a preemptive multithreading module that allows the management of multiple threads. However, it usually causes greater energy wastage. To improve multithreading in sensor networks, a Multithreading Model for an Efficient Data Delivery (MMEDD) using protothreads is proposed in this paper. Intensive experiments have been conducted on COOJA simulator that is integrated in Contiki. The results show that MMEDD provides better ratio message reception rate/energy consumption than other architectures.

ИССЛЕДОВАНИЕ АЛГОРИТМА РАСПАРАЛЛЕЛИВАНИЯ ОПРЕДЕЛЕНИЯ ПУТЕЙ В ЗАДАЧЕ ГРУППОВОГО УПРАВЛЕНИЯ РОБОТАМИ

The work is about development and study of the implementation of a multithreaded flow manager in computing systems for the transport problem of controlling a heterogeneous group of robots. The aim of the work is to study the parameters of the thread manager in order to find a suboptimal configuration for solving the task of managing compu-tation resources and formulating practical recommendations for configuration the developed software as well. In the work, a series of experiments were carried out on the thread manager, experimental dependences of the computing system performance on the manager's configuration parameters were established. In the course of the experiments was established that it is possible to find the suboptimal configuration of the thread manager on the basis of the pa-rameters, such as: the number of logical threads, the size of the batch of subtasks for computation, the number of the subtasks. The results will be used in when the creating of a subsystem for managing computational threads of the general problem, and can be used in other applied problems together with a portable software in the software of the routes computation threads manager.

Hybrid emulation for bypassing anti-reversing techniques and analyzing malware

Malware uses a variety of anti-reverse engineering techniques, which makes its analysis difficult. Dynamic analysis tools, e.g., debuggers, DBI (Dynamic Binary Instrumentation), and CPU emulators, do not provide both accuracy and convenience when analyzing complex malware, which utilizes diverse anti-reversing techniques. Debuggers are convenient, but are easily detected by anti-debugging techniques. DBI tools are better for bypassing anti-reversing techniques than debuggers, but cannot execute complex programs correctly. Emulators are not designed for precise malware analysis. To address the problem fundamentally, we developed a new approach completely different from the previous works. We present a new dynamic analysis scheme for malware, which includes automatic detection and evasion of various anti-reversing techniques. This approach combines a CPU simulator and actual code execution, i.e., machine instructions are simulated with the CPU simulator, whereas API functions are directly executed when they are called. In this method, the CPU simulator can precisely execute code without modifying the code chunks for trampolines. Moreover, our method takes advantage of the OS functionalities, including thread management or interrupt handling. We conducted experiments on 16 widely used protectors, which show that our method outperforms conventional tools: Pin, DynamoRIO, Apate, and OllyAdvanced. Our scheme can unpack 15 protectors and bypass the anti-debugging techniques associated with them.

Parallelized Implementation of the Finite Particle Method for Explicit Dynamics in GPU

As a novel kind of particle method for explicit dynamics, the finite particle method (FPM) does not require the formation or solution of global matrices, and the evaluations of the element equivalent forces and particle displacements are decoupled in nature, thus making this method suitable for parallelization. The FPM also requires an acceleration strategy to overcome the heavy computational burden of its explicit framework for time-dependent dynamic analysis. To this end, a GPU-accelerated parallel strategy for the FPM is proposed in this paper. By taking advantage of the independence of each step of the FPM workflow, a generic parallelized computational framework for multiple types of analysis is established. Using the Compute Unified Device Architecture (CUDA), the GPU implementations of the main tasks of the FPM, such as evaluating and assembling the element equivalent forces and solving the kinematic equations for particles, are elaborated through careful thread management and memory optimization. Performance tests show that speedup ratios of 8, 25 and 48 are achieved for beams, hexahedral solids and triangular shells, respectively. For examples consisting of explicit dynamic analyses of shells and solids, comparisons with Abaqus using 1 to 8 CPU cores validate the accuracy of the results and demonstrate a maximum speed improvement of a factor of 11.2.

Modeling the behavior of threads in the PREEMPT_RT Linux kernel using automata

This article proposes an automata-based model for describing and verifying the behavior of thread management code in the Linux PREEMPT_RT kernel, on a single-core system. The automata model defines the events that influence the timing behavior of the execution of threads, and the relations among them. This article also presents the extension of the Linux trace features that enable the trace of such events in a real system. Finally, one example is presented of how the presented model and tracing tool helped catching an inefficiency bug in the scheduler code and ultimately led to improving the kernel.

IOT Based Omni Directional Robot Control by Using ARM-Series

On this research, controlling the omni directional mobile robot is divided by two controls, high level control which covers positioning and path tracking, also the low-level control which covers omnidirectional kinematic, speed control, heading lock and communication. This also covers thread management, priority fixation and stack memory fixation. Program is divided into several main threads, i.e., IMU, speed controller, communication and motion thread (kinematic). Stack memory configuration for the above threads can be allotted as IMU thread with 1024 bytes of stack memory, speed control with 512 bytes, motion management with 512 bytes, communication with 128 bytes. IMU execution time lapses for 5.6uS, speed control elapses for 19.7uS, whereas motion elapses for 11uS and communication elapses for 1.2mS. Robot’s low-level control which includes robot movement kinematic (e.g., heading lock, speed control etc) is required to support the predefined system and enhance the robot sensor’s response in navigation.

Методи автоматизованого комп'ютерного проектування цифрового пристрою локального управління

The work is devoted to the issues of improving the reliability of logical control systems in supply systems. The presented method of computer-aided computer design of a digital device for local control (regulation). Based on a simplified algorithm for the functioning of the system, represented by GSA, an automaton model in the form of the transition graph of the Mile finite automaton consists. The transition graph is presented in the VHDL hardware description language in the form of a dual-process automaton pattern. According to the transition graph, an algorithm for diagnosing the control device is constructed according to the strategy of bypassing all the arcs of the graph, which guarantees its completeness. Based on the diagnostic algorithm, the VHDL model of the hardware diagnostic device is built. To diagnose the control finite state machine, it was proposed to conduct a “non-destructive” diagnostic experiment on traversing all vertices (arcs) of state diagram using synchronization sequences. The verification of the model of the diagnostics device developed is performed using the Active-HDL simulation system. Synthesis of control device and device diagnostics is performed using.To reduce the additional hardware costs for a device diagnosing in computer-aided design of digital control systems, methods of test-based design and built-in diagnostics should be used. The scientific novelty of the work consists in the further development of computer-aided computer-aided design of a digital local control device. The practical value of the results is in analyzing the circuit implementation (synthesis) of HDL models of the control device (control machine) and diagnostic hardware (diagnostic machine - the diagnostic device allows you to estimate the amount of additional equipment costs using Quine's criterion and analyzing the additional equipment costs and showed that they can be compared to the hardware costs of the control device itself, on the one hand, this increases the hardware costs of the digital system Thread management in general, but on the other hand, the implementation of management systems on an FPGA, SoC, as a rule, there is an untapped programmable logic, which can be used by diagnostic equipment.

C++11 for Hedge Fund Traders and Investment Bankers: Concurrency and Multithreading With C++11 for Thread Management &amp;amp; Data Sharing Between Threads (Presentation Slides)

This C++11 Research Note advances applied understanding about ‘Real’ Multi-threading & Concurrency Control (M&C) for C++ and Reasons for its Adoption particularly in the context of latency minimization needs of Hedge Funds, Investment Banks, and, Trading Desks. The Research Note provides a background into the advancement of the New Paradigm of the C++11 Standard beyond C++ and explains how the 'New Paradigm' is relevant to the needs of Hedge Funds, Investment Banks, and, Trading Desks. From a Systems Programming perspective, it focuses on How the C++11 Standard addresses Multi-threading & Concurrency Control and related constraints of the C++ programming language. Specifically, it provides an overview of the C++11 Multi-threading & Concurrency Control Thread Management Capabilities as well as Data Sharing Capabilities. Motivated by the underlying Boost Thread Library that underpinned the C++11 advancement, it shares specific C++11 M&C capabilities as documented by the key initiator and keeper of that library who also serves on multiple C++ and related standards committees. In addition, it also provides some perspective from other key innovators who have contributed to the original C++ programming language as well as to the C++11 advancements.

Challenges on applying genetic improvement in JavaScript using a high-performance computer

Genetic Improvement is an area of Search Based Software Engineering that aims to apply evolutionary computing operators to the software source code to improve it according to one or more quality metrics. This article describes challenges related to experimental studies using Genetic Improvement in JavaScript (an interpreted and non-typed language). It describes our experience on performing a study with fifteen projects submitted to genetic improvement with the use of a supercomputer. The construction of specific software infrastructure to support such an experimentation environment reveals peculiarities (parallelization problems, management of threads, etc.) that must be carefully considered to avoid future research threats to validity such as dead-ends, which make it impossible to observe relevant phenomena (code transformation) to the understanding of software improvements and evolution.

An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

SummaryA parallel program needs to manage the trade‐off between the time spent in synchronisation and computation. This trade‐off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well‐mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time.

Enabling Massive Multi-Threading with Fast Hashing

The next generation of high-performance computers is expected to execute threads in orders of magnitude higher than today’s systems. Improper management of such huge amount of threads can create resource contention, leading to overall degraded system performance. By leveraging more practical approaches to distribute threads on the available resources, execution models and manycore chips are expected to overcome limitations of current systems. Here, we present DELTA—a Data-Enabled muLti-Threaded Architecture, where a producer-consumer scheme is used to execute threads via complete distributed thread management mechanism. We consider a manycore tiled-chip architecture where Network-on-Chip (NoC) routers are extended to support our execution model. The proposed extension is analysed, while simulation results confirm that DELTA can manage a large number of simultaneous threads, relying on a simple hardware structure.