Thin Ge Buffer Layer Research Articles

Effects of phosphorous and antimony doping on thin Ge layers grown on Si

Suppression of threading dislocations (TDs) in thin germanium (Ge) layers grown on silicon (Si) substrates has been critical for realizing high-performance Si-based optoelectronic and electronic devices. An advanced growth strategy is desired to minimize the TD density within a thin Ge buffer layer in Ge-on-Si systems. In this work, we investigate the impact of P dopants in 500-nm thin Ge layers, with doping concentrations from 1 to 50 × 1018 cm−3. The introduction of P dopants has efficiently promoted TD reduction, whose potential mechanism has been explored by comparing it to the well-established Sb-doped Ge-on-Si system. P and Sb dopants reveal different defect-suppression mechanisms in Ge-on-Si samples, inspiring a novel co-doping technique by exploiting the advantages of both dopants. The surface TDD of the Ge buffer has been further reduced by the co-doping technique to the order of 107 cm−2 with a thin Ge layer (of only 500 nm), which could provide a high-quality platform for high-performance Si-based semiconductor devices.

All-MBE grown InAs/GaAs quantum dot lasers with thin Ge buffer layer on Si substrates

A high-performance III–V quantum-dot (QD) laser monolithically grown on Si is one of the most promising candidates for commercially viable Si-based lasers. Great efforts have been made to overcome the challenges due to the heteroepitaxial growth, including threading dislocations and anti-phase boundaries, by growing a more than 2 µm thick III–V buffer layer. However, this relatively thick III–V buffer layer causes the formation of thermal cracks in III–V epi-layers, and hence a low yield of Si-based optoelectronic devices. In this paper, we demonstrate a usage of thin Ge buffer layer to replace the initial part of GaAs buffer layer on Si to reduce the overall thickness of the structure, while maintaining a low density of defects in III–V layers and hence the performance of the InAs/GaAs QD laser. A very high operating temperature of 130 °C has been demonstrated for an InAs/GaAs QD laser by this approach.

Mediation effect of sub‐monolayer carbon on interfacial mixing in Ge growth on Si(100)

AbstractThe mediation effect of carbon (C) on interfacial mixing in Ge growth was studied using C‐covered Si surface (Ge/C/Si) and C over thin Ge buffer layer (Ge/C/Ge/Si) systems. The samples were prepared by solid‐source molecular beam epitaxy system with electron beam gun for C sublimation and K‐cell for Ge evaporation. The interdiffusion at the interface and deterioration in crystallinity of Ge layer was evaluated by Raman spectroscopy and X‐ray diffraction, respectively. In the case of Ge/C/Si system, the interdiffusion of Si and Ge atoms was suppressed by more than 0.3 monolayer (ML)‐C depositions while crystallinity of Ge layer was deteriorates by the formation of Si‐C at the Si surface and the incorporation of C atoms in Ge layer. In the case of Ge/C/Ge/Si system, the crystallinity of Ge layer was maintained even at C coverage of a few MLs, however, the amount of C to suppress the Ge/Si interdiffusion was more than 3 ML. From the correlation between Ge crystallinity and surface roughness, Ge/C/Ge/Si structure is considered to be more effective to take advantage of C mediation. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Thermal stability investigation of SiGe virtual substrate with a thin Ge buffer layer grown on Si substrate

We present the study of the thermal stability of SiGe virtual substrates with a thin Ge interlayer on Si substrate grown at low temperature. Thermal annealing under different temperatures was carried out, and the thermal stability of the virtual substrate was discussed in detail. From the investigation it is found that annealing could only affect the strain relaxation of the virtual substrate at 600°C. When the sample is annealed at 800°C, the structure of this virtual substrate becomes unstable. A Ge segregation layer at the SiGe/Si interface will be formed. When the sample was annealed above the melting point of Ge (1000°C), the bottom Si-buffer layer could easily diffuse into the low temperature Ge layer (LT-Ge), also forming a Ge rich layer at the SiGe/Si interface. The results obtained from this investigation provide us important information about the stability of SiGe virtual substrate with a LT-Ge interlayer.

Taper-Free and Vertically Oriented Ge Nanowires on Ge/Si Substrates Grown by a Two-Temperature Process

Taper-free and vertically oriented Ge nanowires were grown on Si (111) substrates by chemical vapor deposition with Au nanoparticle catalysts. To achieve vertical nanowire growth on the highly lattice mismatched Si substrate, a thin Ge buffer layer was first deposited, and to achieve taper-free nanowire growth, a two-temperature process was employed. The two-temperature process consisted of a brief initial base growth step at high temperature followed by prolonged growth at lower temperature. Taper-free and defect-free Ge nanowires grew successfully even at 270 °C, which is 90 °C lower than the bulk eutectic temperature. The yield of vertical and taper-free nanowires is over 90%, comparable to that of vertical but tapered nanowires grown by the conventional one-temperature process. This method is of practical importance and can be reliably used to develop novel nanowire-based devices on relatively cheap Si substrates. Additionally, we observed that the activation energy of Ge nanowire growth by the two-te...

Selective Area Growth of InP and Defect Elimination on Si (001) Substrates

We report the selective area growth of InP layers in submicron trenches on Si (001) substrates by using a thin Ge buffer layer. The antiphase domain boundaries in InP layers are suppressed by engineering the local Ge surface profile. The mechanism of atomic step formation and the corresponding method for step density control are presented. We discuss the impact of the surface profile of the Ge buffer layer on the formation of antiphase domain boundaries as well as on InP nucleation. A minimum step density of 0.25 nm−1 is required to avoid antiphase domain boundaries while a higher step density substantially reduces the stacking faults and twins in the InP nucleation layer. By employing the threading dislocation necking effect and the properly controlled Ge surface profile, high-quality InP layers have been obtained in submicron trenches.

Selective Epitaxial Growth of InP in STI Trenches on Off-Axis Si (001) Substrates

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2.

Selective area growth of high quality InP on Si (001) substrates

In this work, we demonstrate the selective area growth of high quality InP layers in submicron trenches on exactly (001) oriented Si substrates by using a thin Ge buffer layer. Antiphase domain boundaries were avoided by annealing at the Ge surface roughening temperature to create additional atomic steps on the Ge buffer layer. The mechanism of Ge surface atomic step formation and the corresponding step density control method are illustrated. The elimination of antiphase boundaries from the optimized Ge buffer layer, together with the defect necking effect, yield defect-free top InP layers inside the trenches.

Growth of high quality InP layers in STI trenches on miscut Si (0 0 1) substrates

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [1̄ 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [1̄ 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2.

Vertically oriented epitaxial germanium nanowires on silicon substrates using thingermanium buffer layers

We demonstrate a method to realize vertically oriented Ge nanowires on Si(111) substrates.Ge nanowires were grown by chemical vapor deposition using Au nanoparticles to seednanowire growth via a vapor–liquid–solid growth mechanism. Rapid oxidation of Si during Aunanoparticle application inhibits the growth of vertically oriented Ge nanowires directly onSi. The present method employs thin Ge buffer layers grown at low temperature less than600 °C tocircumvent the oxidation problem. By using a thin Ge buffer layer with root-mean-square roughnessof ∼ 2 nm, the yield of vertically oriented Ge nanowires is as high as 96.3%. This yield iscomparable to that of homoepitaxial Ge nanowires. Furthermore, branched Ge nanowirescould be successfully grown on these vertically oriented Ge nanowires by a secondaryseeding technique. Since the buffer layers are grown under moderate conditions without anyhigh temperature processing steps, this method has a wide process window highly suitablefor Si-based microelectronics.

Thermal stability of SiGe films on an ultra thin Ge buffer layer on Si grown at low temperature

The thermal stability of SiGe films on an ultra thin Ge buffer layer on Si fabricated at low temperature has been studied. The microstructure and morphology of the samples were investigated by high-resolution X-ray diffraction, Raman spectra and atomic force microscopy, and using a diluted Secco etchant to reveal dislocation content. After thermal annealing processing, it is observed that undulated surface, threading dislocations (TDs) and stacking faults (SFs) appeared at the strained SiGe layer, which developed from the propagation of a misfit dislocation (MD) during thermal annealing, and no SFs but only TDs formed in strain-relaxed sample. And it is found that the SiGe films on the Ge layer grown at 300 °C has crosshatch-free surface and is more stable than others, with a root mean square surface roughness of less than 2 nm and the threading dislocation densities as low as ∼10 5 cm −2. The results show that the thermal stability of the SiGe films is associated with the Ge buffer layer, the relaxation extent and morphology of the SiGe layer.

MBE Growth of GaAs on Si through Direct Ge Buffers

AbstractThe result of GaAs growth on Si using a thin Ge buffer layer (about 0.5μm thick) is presented in this paper. A two-step method with a high temperature anneal between two steps is used to grow the Ge buffer layer. Single phase GaAs is grown on Ge by controlling the growth temperature, substrate miscut and the prelayers. No APD defect is observed by the XTEM and the threading dislocation density of GaAs grown using this method is about 5˜10×107cm-2. The PL intensity of GaAs is 10× less on Si substrate than on GaAs substrates.

Use of germanium interfacial layer for the hetero-epitaxial growth of CdTe on Si substrates

Epitaxial (100) CdTe layers have been grown by atmospheric pressure organometallic vapor phase epitaxy (OMVPE) on Si(100) substrates misoriented 9° towards the (110) direction. A thin Ge buffer layer grown at low temperature followed by an interfacial layer of ZnTe was used to get high quality (100) CdTe. The layers were characterized by X-ray diffraction and optical microscopy. X-ray rocking curve with FWHM of about 260 arc sec has been obtained for a 4 μm thick CdTe layer. The results presented demonstrate a novel technique to grow high quality CdTe on Si in a single OMVPE reactor.

Growth of CDTE on GaAs and Si Substrates by Organometallic Vapor Phase Epitaxy

ABSTRACTEpitaxial (100) CdTe layers have been grown by organometallic vapor phase epitaxy (OMVPE) on GaAs and Si substrates. A thin layer of CdTe was first grown by atomic layer epitaxy (ALE) on GaAs substrates followed by thicker CdTe layer by conventional organometallic vapor phase epitaxy (OMVPE). This process resulted in high quality (100) CdTe on GaAs substrates. On Si substrates, direct growth of CdTe resulted in only polycrystalline layers. Hence, a thin Ge buffer layer grown at low temperature followed by an interfacial layer of ZnTe was used to get high quality (100) CdTe on Si. The process developed here eliminates the high temperature (>850°C) deoxidation step generally required when Si substrates are used. The CdTe layers were characterized by X-ray diffraction and optical microscopy. X-ray rocking curve with full width at half maximum (FWHM) of about 260 arcsec has been obtained for a 4 um thick CdTe layer. The results presented demonstrate novel techniques to control the hetero-interfaces in order to grow high quality CdTe on GaAs and Si substrates.

Heteroepitaxy of Ge films on Si(100) surface

Structural and electrical properties of epitaxial Ge films on a Si(100)-2x1 surface have been studied by means of low-energy-electron diffraction (LEED), Auger-electron spectroscopy (AES), X-ray diffraction, Raman scattering and Hall measurements. We found that a thickness of more than 1000 Å is required to grow high quality epitaxial Ge films on the Si substrate at elevated temperature. This is due to island formation at the initial stage of Ge deposition. Thus, special efforts were devoted to elucidate the role of a thin Ge buffer layer fabricated at substrate temperatures below 200 °C used to grow thinner epitaxial Ge films by suppressing island formation. It was found that the thin amorphous buffer layers remained poorly crystallized during the rapid increase in substrate temperature up to 400–500 °C, prior to subsequent Ge deposition on the buffer layer. Consequently, relatively thin single crystal Ge films grew in such a way that the underlying buffer layers accommodate the strain or misfit dislocations near the Si-Ge interface.