Thin-film Transistor Devices Research Articles

Amorphous Doped Indium Tin Oxide Thin‐Films by Atomic Layer Deposition.Insights into Their Structural, Electronic and Device Reliability

AbstractThin semiconducting films of magnesium doped indium‐ and tin oxide are prepared by thermal atomic layer deposition (ALD). The metal oxide films are deposited at 200 °C from the precursors trimethylindium, tetrakis(dimethylamido)tin, bis(ethylcyclopentadienyl)magnesium and water as oxidant. These thin‐films are observed to be amorphous by electron microscopy and X‐ray diffraction. However, they exhibited a near‐range atomic order with correlation lengths of up to 10 Å, as demonstrated by high energy total scattering at grazing incidence employing synchrotron radiation. Even minor alterations in composition reveal a significant impact on the thin‐film transistor (TFT) device parameters, due to magnesium's high oxygen binding capability and its ability to inhibit the formation of oxygen vacancies, resulting in a decrease of free charge carriers in the material. Stability tests indicate a device degradation after storage in ambient conditions due to water adsorption on the surface, which could be reversed by an additional annealing step which qualify the films as robust. This studie demonstrate the possibility of employing minor amounts of high band gap oxides such as MgO to manipulate and control the electric behavior of the active channel layer performance in inorganic TFT devices.

Effect of Deposition Temperature on Zn Interstitials and Oxygen Vacancies in RF-Sputtered ZnO Thin Films and Thin Film-Transistors.

ZnO thin films were deposited using RF sputtering by varying the argon:oxygen gas flow rates and substrate temperatures. Structural, optical and electrical characterization of ZnO thin films were systematically carried out using X-Ray diffraction (XRD), scanning electron microscopy (SEM), UV-visible spectroscopy, X-Ray photoelectron spectroscopy (XPS) and Hall measurements. Film deposited at room temperature and annealed at 300 °C exhibited low O2 incorporation with localized defects and a high percentage of Zn interstitials. A large crystalline size and fewer grain boundaries resulted in a high Hall mobility of 46.09 cm2/V-s Deposition at higher substrate temperatures resulted in improvement in O2 incorporation through the annihilation of localized defects and decrease in oxygen vacancies and Zn interstitials. Urbach tails within the bandgap were identified using the absorption spectrum and compared with the % defects from XPS. Bottom-gate thin-film transistors were subsequently fabricated on a SiO2/p-Si substrate using the combination of RF sputtering, wet etching and photolithography. Variation in the substrate temperature showed performance enhancement in terms of the leakage current, threshold voltage, sub-threshold swing and ION/IOFF ratio. Thin-film transistor (TFT) devices deposited at 300 °C resulted in an O2-rich surface through chemisorption, which led to a reduction in the leakage current of up to 10-12 A and a 10-fold reduction in the sub-threshold swing (SS) from 30 V to 2.8 V. Further TFT optimization was carried out by reducing the ZnO thickness to 50 nm, which resulted in a field-effect mobility of 1.1 cm2/V-s and ION/IOFF ratio of 105.

Improving the photoswitching performance of a transistor with amorphous metal oxide semiconductor thin film by a gradient annealing approach

Metal oxides are attracting attention as electronic mate rials in research and industry. Thin films of amorphous indium gallium zinc oxide (a-IGZO) exhibit low absorbance in the visible spectrum, making them ideal components in transparent electronics. To widen the scope of use for thin film transistor (TFT) devices based on a-IGZO in on-chip sensing applications, photoresponsive behavior has been achieved by proper engineering of the active layers by either introducing a photosensitive top layer or using a method to generate localized states inside the band gap. In this paper, we propose a bilayer structured with the use of thermal annealing of a-IGZO film at different temperatures. Thermal annealing has been shown to improve the electrical performance of the TFT devices because of the improved film quality but negatively affects the photoresponsivity by removing tarp sites that play an important role in both charge generation and photomultiplication via the photogating effect. Therefore, here we propose an a-IGZO film with a high temperature-annealed bottom layer and pristine top layer. The bottom layer plays a vital role in the charge transport behavior, resulting in a low threshold voltage and subthreshold swing similar to the device with a fully annealed film, while the photoresponse of the device is driven by the higher density of gap states in the pristine top layer. This proposed method is advantageous to previously published procedures due to the simplicity of using no additional materials and complex steps to introduce trap sites into the photoactive layer, but only differential annealing temperature.

A study on the high mobility and improved reliability of pr-doped indium zinc oxide thin film transistors

Abstract It is generally accepted that there is a trade-off relationship between mobility and stability for oxide thin film transistor (TFT) devices. Different doping ratios of Ln praseodymium (Pr) into indium (In) zinc (Zn) oxide have been employed as the active layer to get 1# and 2# amorphous oxide semiconductor (AOS) TFTs in this work. The 1#-based TFTs exhibited a high mobility of 49.84 cm2 V−1 s−1 due to the increased concentration of In. By further elevating the Pr doping ratio and adjusting In/Zn ratio of the film, the 2#-based TFT obtained both a good mobility of 26.65 cm2 V−1 s−1, and a promising stability, showing a positive-bias temperature stress stability of ΔV TH = 1.56 V and a negative-bias temperature illumination stress stability of ΔV TH = −1.47 V. It was revealed that the low energy charge transfer state of Pr in 2# film absorbs the visible light, leading to suppressed photo-induced carriers and thus a good illumination reliability of the 2#-based TFTs. In practice, the LCD panel based 2# ACT TFT shows a well stable performance even under 10 000-nit illumination. The result indicates a promising strategy to accelerate the commercialization of AOS TFTs to large-panel display production.

Fabrication of carbon nanotube neuromorphic thin film transistor arrays and their applications for flexible olfactory-visual multisensory synergy recognition

Abstract Artificial multisensory devices play a key role for the human-computer interaction in the field of artificial intelligence (AI). In this work, we have designed and constructed a novel olfactory-visual bimodal neuromorphic carbon nanotube thin film transistor (TFT) arrays for artificial olfactory-visual multisensory synergy recognition with the ultralow single-pulse power consumption of 25 aJ, employing semiconducting single-walled carbon nanotubes (sc-SWCNTs) as channel materials and gas sensitive materials, and poly[[4,8-bis[5-(2-ethylhexyl)-2-thienyl]benzo[1,2-b:4,5-b0]dithiophene-2,6-diyl]-2,5-thiophenediyl-[5,7-bis(2-ethylhexyl)-4,8-dioxo-4H,8H-benzo[1,2-c:4,5-c0]dithio-phene-1,3-diyl]] (PBDB-T) as the photosensitive material. It is noted that it is the first time to realize the simulation of olfactory and visual senses (from 280 nm to 650 nm) with the wide operating temperature range (0-150 °C) in a single SWCNT TFT device and successfully simulate the recovery of olfactory senses after COVID-19 by olfactory-visual synergy. Furthermore, our SWCNT neuromorphic TFT devices with high Ion/Ioff ratio (up to 106) at a low operating voltage (-2-0.5 V) can mimic not only the basic biological synaptic functions of olfaction and vision (such as paired-pulse facilitation, short-term plasticity, and long-term plasticity), but also optical wireless communication by Morse code. The proposed multisensory, broadband light-responsive, low-power synaptic devices provide great potential for developing AI robots to face complex external environments.

Formation Mechanism and Prevention of Cu Undercut Defects in the Photoresist Stripping Process of MoNb/Cu Stacked Electrodes

The Cu undercut is a recently discovered new defect generated in the wet stripping process of MoNb/Cu gate stacked electrodes for thin-film transistors (TFTs). The formation mechanism and preventive strategy of this defect were identified and investigated in this paper. The impact of stripper concentration and stripping times on the morphology and the corrosion potential (Ecorr) of Cu and MoNb were studied. It is observed that the undercut is Cu tip-deficient, not the theoretical MoNb indentation, and the undercut becomes severer with the increase in stripping times. The in-depth mechanism analysis revealed that the abnormal Cu undercut was not ascribed to the galvanic corrosion between MoNb and Cu but to the local crevice corrosion caused by the corrosive medium intruding along the MoNb/Cu interface. Based on this newly found knowledge, three possible prevention schemes (MoNiTi (abbreviated as Mo technology development (MTD) layer/Cu), MoNb/Cu/MTD, and MoNb/Cu/MoNb) were proposed. The experimental validation shows that the Cu undercut can only be completely eliminated in the MoNb/Cu/MTD triple-stacked structure with the top MTD layer as a sacrificial anode. This work provides an effective and economical method to avoid the Cu undercut defect. The obtained results can help ensure TFT yield and improve the performance of TFT devices.

Thermal atomic layer deposition-processed InHfZnO thin film transistors with excellent stability

In recent years, the downscaling of transistors has sparked considerable interest in the advancement of amorphous oxide semiconductors, particularly indium-hafnium-zinc oxide (IHZO) has remarkable potential in applications such as high-resolution displays and 3D NAND. For the first time, we propose the fabrication of IHZO thin film transistors (TFTs) via thermal atomic layer deposition (TH-ALD). The preparation, electrical properties, and stability of IHZO TFTs are investigated. The performance of TFT deposited at 250 °C and annealed in N2 atmosphere at 300 °C exhibits a high field-effect mobility (μ) of 22.53 cm2/Vs, a high Ion/Ioff of ∼107, a low threshold voltage (Vth) of 0.15 V, and a minimum subthreshold swing (SS) of 0.24 V/decade. Furthermore, the threshold voltage shifts (ΔVth) in TFTs annealed in N2 and O2 are 0.31 and 0.16 V, respectively. These enhancements are attributed to the defects suppression and remaining ionized oxygen vacancies result in increased electron concentration in N2-annealed films. In comparison, O2 annealing causes a reduction in field effect mobility but concurrently enhances stability due to the direct passivation of defects, which leads to fewer oxygen vacancies. Additionally, Hf content can also impact the performance of TFT devices, even a small addition of Hf also results in the effective reduction of the carrier concentration. These findings provide valuable insights into the device mechanism of IHZO TFTs, presenting a novel avenue for comprehending and augmenting their overall performance.

Improving TFT Device Performance by Changing the Thickness of the LZTO/ZTO Dual Active Layer.

The primary objective of this research paper is to explore strategies for enhancing the electrical performance of dual active layer thin film transistors (TFTs) utilizing LZTO/ZTO as the bilayer architecture. By systematically adjusting the thickness of the active layers, we achieved significant improvements in the performance of the LZTO/ZTO TFTs. An XPS analysis was performed to elucidate the impact of the varying O2 element distribution ratio within the LZTO/ZTO bilayer thin film on the TFTs performance, which was directly influenced by the modification in the active layer thickness. Furthermore, we utilized atomic force microscopy to analyze the effect of altering the active layer thickness on the surface roughness of the LZTO/ZTO bilayer film and the impact of this roughness on the TFTs electrical performance. Through the optimization of the ZTO active layer thickness, the LZTO/ZTO TFT exhibited an mobility of 10.26 cm2 V-1 s-1 and a switching current ratio of 5.7 × 107, thus highlighting the effectiveness of our approach in enhancing the electrical characteristics of the TFT device.

Ion migration in p-type perovskite MAPbI3 films under an electric field and thin-film transistor device failure.

This study demonstrated a dynamic analysis to investigate the ion migration in p-type perovskite MAPbI3 films under an electric field, revealing its detrimental effects on the electrical performance of MAPbI3-based devices. An additive strategy was proposed to suppress ion migration, thereby facilitating the fabrication of high-performance MAPbI3-based devices.

Solution-processed high-k photopatternable polymers for low-voltage electronics.

High dielectric constant (k) polymers have been widely explored for flexible, low-power-consumption electronic devices. In this work, solution-processable high-k polymers were designed and synthesized by ultraviolet (UV) triggered crosslinking at a low temperature (60 °C). The highly crosslinked network allows for high resistance to organic solvents and high breakdown strength over 2 MV cm-1. The UV-crosslinking capability of the polymers enables them to achieve a high-resolution pattern with a feature size down to 1 μm. Further investigation suggests that the polar cyano pendants in side chains are responsible for increasing the dielectric constant up to 10 in a large-area device array, thereby contributing to a low driving voltage of 5 V and high field-effect mobility exceeding 20 cm2 V-1 s-1 in indium gallium zinc oxide (IGZO) thin-film transistors (TFTs). In addition, the solution-processable high-k dielectric polymers were utilized to fabricate flexible low-voltage organic TFTs, which show highly reliable and reproducible mechanical stability at a bending radius of 5 mm after 1000 cycles. And also, the high radiation stability of the dielectric polymers was observed in a UV-sensitive TFT device, thereby achieving highly reproducible pattern recognition, which is promising for artificial optic nerve circuits.

Three-dimensional integrated metal-oxide transistors

AbstractThe monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the development of scalable processes for integrating three-dimensional TFT devices is challenging. Here, we report the monolithic three-dimensional integration of indium oxide (In2O3) TFTs on a silicon/silicon dioxide (Si/SiO2) substrate at room temperature. We use an approach that is compatible with complementary metal–oxide–semiconductor (CMOS) processes to stack ten n-channel In2O3 TFTs. Different architectures—including bottom-, top- and dual-gate TFTs—can be fabricated at different layers in the stack. Our dual-gate devices exhibit enhanced electrical performance with a maximum field-effect mobility of 15 cm2 V−1 s−1, a subthreshold swing of 0.4 V dec−1 and a current on/off ratio of 108. By monolithically integrating dual-gate In2O3 TFTs at different locations in the stack, we created unipolar invertor circuits with a signal gain of around 50 and wide noise margins. The dual-gate devices also allow fine-tuning of the invertors to achieve symmetric voltage-transfer characteristics and optimal noise margins.

P‐15: The Back‐channel Effect in Low Temperature Poly‐Si Thin Film Transistors

This paper addresses the mechanism of the back‐channel effect on TFTs (Thin Film Transistors) and proposes novel methods for characterizing and improving the stability of driving TFT devices, including back‐channel and back‐voltage testing. In comparison to routine sticking image and negative bias temperature stress testing, our methods aim to minimize the impact of intrinsic material fluctuations, allowing for independent measurement of the back‐channel effect on TFT device electrical characteristics. We also offer an enhanced option (N2 Plasma treatment of PI surface), that have been used for better the performance of products.

P‐31: Investigation on driving backboard of electronic paper based on low‐temperature polycrystalline silicon

In this work, we report a systematic investigation of low‐temperature polycrystalline silicon (LTPS)‐based driving backboard of electronic paper. Firstly, LTPS‐based thin film transistors (TFTs) with extremely low off‐state leakage current at a large gate‐source voltage (VGS) of 30 V were obtained through detailed explorations of low‐temperature polycrystalline silicon technology. Meanwhile, the high on‐state current of LTPS‐TFTs also meet the requirements of fast signal writing to the storage capacitor due to their extremely high field‐effect mobility (~100 cm2 /V*s), making it possible to fabricate TFT devices with relatively small width/length ratios (W/L) to minimize feed‐through to the full extent.

Effects of Laser Treatment of Terbium-Doped Indium Oxide Thin Films and Transistors.

In this study, a KrF excimer laser with a high-absorption coefficient in metal oxide films and a wavelength of 248 nm was selected for the post-processing of a film and metal oxide thin film transistor (MOTFT). Due to the poor negative bias illumination stress (NBIS) stability of indium gallium zinc oxide thin film transistor (IGZO-TFT) devices, terbium-doped Tb:In2O3 material was selected as the target of this study. The XPS test revealed the presence of both Tb3+ and Tb4+ ions in the Tb:In2O3 film. It was hypothesized that the peak of the laser thermal effect was reduced and the action time was prolonged by the f-f jump of Tb3+ ions and the C-T jump of Tb4+ ions during the laser treatment. Studies related to the treatment of Tb:In2O3 films with different laser energy densities have been carried out. It is shown that as the laser energy density increases, the film density increases, the thickness decreases, the carrier concentration increases, and the optical band gap widens. Terbium has a low electronegativity (1.1 eV) and a high Tb-O dissociation energy (707 kJ/mol), which brings about a large lattice distortion. The Tb:In2O3 films did not show significant crystallization even under laser energy density treatment of up to 250 mJ/cm2. Compared with pure In2O3-TFT, the doping of Tb ions effectively reduces the off-state current (1.16 × 10-11 A vs. 1.66 × 10-12 A), improves the switching current ratio (1.63 × 106 vs. 1.34 × 107) and improves the NBIS stability (ΔVON = -10.4 V vs. 6.4 V) and positive bias illumination stress (PBIS) stability (ΔVON = 8 V vs. 1.6 V).

A ternary gate-connected threshold switching thin-film transistor

Multi-valued logic has been a significant focus of research in various fields with the advancement of information technology. One approach to realizing ternary logic is integrating of a threshold switching (TS) device with a transistor, but this method often entails a complex fabrication process. This work suggests a ternary gate-connected threshold switching thin-film transistor (TS-TFT) by serially connecting the TS device with a bottom-gate thin-film transistor (TFT). The fabrication process is simplified with a structure that shares electrodes and insulators. Different threshold voltages from TS and TFT devices produce stable multiple states. The Pt/HfO2/TiN TS device has an electronic trapping/detrapping switching mechanism that exhibits low power consumption and high reliability. With the superior electrical performance of an amorphous indium gallium zinc oxide TFT, the TS-TFT has stable endurance. Furthermore, pulse switching and ternary inverter are demonstrated from the practical point of view.

High‐Performance Nd: AIZO/Al2O3 Dual Active Layer Design Without Thermal Annealing: High‐Speed Electron Transport and Defect Modification in Thin Film Transistors

Flexible wearable electronics have been developing rapidly in recent years, and one of its core devices, thin‐film transistor (TFT), is also attracting attention. Current TFT preparation processes usually require high annealing temperatures (>350 °C), which is not conducive to their application on most flexible substrates (PET, PEN, nanopaper, etc.). In this article, a strategy for the room temperature preparation of Nd:AIZO/Al2O3 dual‐layer TFT devices is proposed, which has appreciable electrical properties without additional annealing treatment. Taguchi orthogonal experimental methods are used to investigate the effects of three essential process parameters on the performance of the films and devices. As Nd:AIZO deposition time decreases and Al2O3 oxygen percentage and time during deposition increase, the μsat and SS of TFT devices are improved. With the preferred combination of parameters applied to the device preparation, the device exhibits a saturation mobility μsat of 24.3 cm2 V−1 s−1, a threshold voltage Vth of −1.4 V, a subthreshold swing SS of 0.21 V decade−1 and an Ion/Ioff ratio of 4.26 × 108. The ultra‐thin Al2O3 layer act as defect modification and form high‐speed electron transport in channel layer. The room temperature preparation of the dual‐layer TFT process proposed in this article is compatible with large‐size low‐cost flexible substrates. It has great potential for application in green flexible wearable electronics.

Active-matrix digital microfluidics design for field programmable high-throughput digitalized liquid handling

Digital liquid sample handling is an enabling tool for cutting-edge life-sciences research. We present here an active-matrix thin-film transistor (TFT) based digital microfluidics system, referred to as Field Programmable Droplet Array (FPDA). The system contains 256×256 pixels in an active area of 10.65cm2, which can manipulate thousands of addressable liquid droplets simultaneously. By leveraging a novel TFT device and circuits design solution, we manage to programmatically manipulate droplets at single-pixel level. The minimum achievable droplet volume is around 0.5 nL, which is two orders of magnitude smaller than the smallest droplet ever reported on active-matrix digital microfluidics. The movement of droplets can be either pre-programmed or controlled in real-time. The FPDA system shows great potential of the ubiquitous thin-film electronics technology in digital liquid handling. These efforts will make it possible to create a true programmable lab-on-a-chip device to enable great advances in life science research.

Research on correlation between metal oxide semiconductor target and magnetron sputtered film based on TFT application

The research on the intrinsic relationship between target quality and TFT (thin film transistor) performance is not perfect for magnetron sputtering processes. The systematic analysis of target-film-device still needs to be improved. This paper studied the internal relationship between metal oxide semiconductor targets, thin films, and TFT devices for the deterioration problem of device performance caused by the failure of the aging target. The experimental results showed that the target surface with a long cumulative sputtering time had apparent macroscopic concave, related to the electromagnetic field distribution. The concave region was the primary source of thin film composition, so the research object of this work was mainly the concave region. A multi-oxide target was used in this work, and its selective sputtering phenomenon was serious, mainly reflected in the sputtering rate of In2O3 grains with higher electrical conductivity than other components. There were many failure sites on the surface of the target, including nodules, holes, coating layers, and cracks. The failure sites would hinder the normal sputtering process and eventually form a vicious circle, failing the target. Due to the decline of target quality, sputtering particles would be in a state of insufficient kinetic energy, resulting in particle agglomeration, element segregation, weak M-O (metal-oxide) bonds, loose accumulation, and surface or block defects. Ultimately, the TFT performance with the aging target showed lower mobility, larger subthreshold swing, increased off-state current, and poorer stability. Clarifying the relationship between target quality and device performance is beneficial for the development of electronic devices.

Intense pulsed light annealing of solution-based indium–gallium–zinc–oxide semiconductors with printed Ag source and drain electrodes for bottom gate thin film transistors

In this study, an intense pulsed light (IPL) annealing process for a printed multi-layered indium–gallium–zinc–oxide (IGZO) and silver (Ag) electrode structure was developed for a high performance all-printed inorganic thin film transistor (TFT). Through a solution process using IGZO precursor and Ag ink, the bottom gate structure TFT was fabricated. The spin coating method was used to form the IGZO semiconductor layer on a heavily-doped silicon wafer covered with thermally grown silicon dioxide. The annealing process of the IGZO layer utilized an optimized IPL irradiation process. The Ag inks were printed on the IGZO layer by screen printing to form the source and drain (S/D) pattern. This S/D pattern was dried by near infrared radiation (NIR) and the dried S/D pattern was sintered with intense pulsed light by varying the irradiation energy. The performances of the all-printed TFT such as the field effect mobility and on–off ratio electrical transfer properties were measured by a parameter analyzer. The interfacial analysis including the contact resistance and cross-sectional microstructure analysis is essential because diffusion phenomenon can occur during the annealing and sintering process. Consequently, this TFT device showed noteworthy performance (field effect mobility: 7.96 cm2/V s, on/off ratio: 107). This is similar performance compared to a conventional TFT, which is expected to open a new path in the printed metal oxide-based TFT field.

Electrical performance of La-doped In2O3 thin-film transistors prepared using a solution method for low-voltage driving.

In this paper, La-doped In2O3 thin-film transistors (TFTs) were prepared by using a solution method, and the effects of La doping on the structure, surface morphology, optics, and performance of In2O3 thin films and TFTs were systematically investigated. The oxygen defects concentration decreased from 27.54% to 17.93% when La doping was increased to 10 mol%, and La served as a carrier suppressor, effectively passivating defects such as oxygen defects. In fact, the trap density at the dielectric/channel interface and within the active layer can be effectively reduced using this approach. With the increase of La concentration, the mobility of LaInO TFTs decreases gradually; the threshold voltage is shifted in the positive direction, and the TFT devices are operated in the enhanced mode. The TFT device achieved a subthreshold swing (SS) as low as 0.84 V dec-1, a mobility (μ) of 14.22 cm2 V-1 s-1, a threshold voltage (VTH) of 2.16 V, and a current switching ratio of Ion/Ioff of 105 at a low operating voltage of 1 V. Therefore, regulating the doping concentration of La can greatly enhance the performance of TFT devices, which promotes the application of such devices in high-performance, large-scale, and low-power electronic systems.