Thick SOI Research Articles

Downsizing Effects on Micro and Nano Comb Drives

Downscaling has been a focal task of Electronics and Electromechanics in the last few decades, and a great engine for technological progress as well. Nevertheless, a scaling operation affects device physics, functioning and performance. The present paper investigates about the impact of scaling on a test case compliant electrostatic micro or nano actuator that is under development with two preferred micro fabrication methods, namely, thick SOI and thin amorphous silicon. A series of numerical trials on materials strength, electro-mechanical characteristics, sensitivity and overall actuation performance have been carried out at different grades of down-scaling and of aspect ratio. This gave rise to new design charts that we propose here as a predictive and friendly guide to select the most appropriate micro fabrication method.

Highly Scaled, High Endurance, Ω-Gate, Nanowire Ferroelectric FET Memory Transistors

In this work, we demonstrate highly scaled, non-volatile memory transistors with ferroelectric Zr-doped HfO2(HZO) as gate insulator. ${\Omega }$ -gate transistors with gate length ~30 nm and width ~85 nm were fabricated on ~20 nm thick SOI. We demonstrate robust memory operation with ≤100 ns program and erase speed at ±5 V, projected memory retention time up to 10 years at 85 °C, and ~0.5 V memory window after 108 endurance cycles. The impact of ${V} _{\text {D}}$ on erase speed provides insights into the importance of holes on memory operation.

Ultra-broadband nanophotonic phase shifter based on subwavelength metamaterial waveguides

Optical phase shifters are extensively used in integrated optics not only for telecom and datacom applications but also for sensors and quantum computing. While various active solutions have been demonstrated, progress in passive phase shifters is still lacking. Here we present a new type of ultra-broadband 90° phase shifter, which exploits the anisotropy and dispersion engineering in subwavelength metamaterial waveguides. Our Floquet–Bloch calculations predict a phase-shift error below ± 1.7 ° over an unprecedented operation range from 1.35 to 1.75 μm, i.e., 400 nm bandwidth covering the E, S, C, L, and U telecommunication bands. The flat spectral response of our phase shifter is maintained even in the presence of fabrication errors up to ± 20 nm , showing greater robustness than conventional structures. Our device was experimentally demonstrated using standard 220 nm thick SOI wafers, showing a fourfold reduction in the phase variation compared to conventional phase shifters within the 145 nm wavelength range of our measurement setup. The proposed subwavelength engineered phase shifter paves the way for novel photonic integrated circuits with an ultra-broadband performance.

Advanced barrier and seed layer deposition enabling multiple type of TSVs integration

TSV integration is a key technology allowing heterogeneous devices 3D integration. However, depending on the targeted application, various TSV sizes and integration schemes exist, all requesting very high aspect ratio. The most common integration is the Mid-process TSV for which aspect ratio is required to be higher than 10:1 whatever application. In the case of large interposers, silicon thickness has to be increased to limit the deformation of the substrate due to highly stressed devices. Same requirements are made by photonic interposers which use thick SOI substrate leading to high warpage during integration. In the opposite, imagers requires to save silicon surface thus reduce TSV size and keep out zone. Silicon thickness has to be kept in the 100 μm range leading then the aspect ratio of the TSV to increase. Recently, Hybrid bonding progresses allowed a new type of TSV to be introduced : High Density TSVs for imagers. In this application, micrometer range TSV have to be filled with a Silicon thickness reduction limited to 10 μm by grinding process control. In order to allow the metal filling of all those type of structures, we have developed a highly conformal barrier and seed layer processes using standard materials for easier integration. The process is based on the use of MOCVD TiN as a barrier. This material is deposited using TDMAT precursor which allows low temperature deposition (200 °C)[1] which extends also the polyvalence of the process toward polymer bonded integrations. The very high step coverage of this process, reported at more than 30% in 20:1 aspect ratio coupled to high resistance to copper diffusion allows as thin as 20 nm barrier thickness which appears relevant economically (for deposition and CMP) and for stress consideration, compared to the well known but thicker PVD TaN process. Considering seed layer, the eG3D process[2] was brought to a high maturity allowing it to be integrated in an applied material raider tool coupled to TSV filling reactors. This process, based on electrografting of copper has already proved a step coverage of more than 50% in 12:1 aspect ratio structures. The presented work shows that the same process requires only deposition parameters change to be able to fully cover 10×150 μm Mid-process TSV as well as 1×10 μm High density ones. The excellent step coverage of this process allowed as thin as 200 nm (for 10×120 μm TSVs) and 100 nm (for (1×10 μm ones) deposited thicknesses to ensure perfect coverage of the structures. eG3D process also has the ability to be used as a repair process for non-continuous widely used PVD Cu seed layers but also be deposited directly on the barrier material. These 2 layers were evaluated together in a 300mm TSV integration schemes of both 10×120 mid process and 1×10 μm High Density structures and qualified electrically. The paper will discuss the deposition process development leading to simultaneously allow copper filling of the very wide range of TSVs on the same process equipment and using the same chemicals. We will then present integration results as well as electrical test of TSV daisy chains of both mid and High density TSVs showing excellent yield for all TSV size and integration schemes.

A differential Hall effect measurement method with sub-nanometre resolution for active dopant concentration profiling in ultrathin doped Si1-x Ge x and Si layers.

In this paper, we present an enhanced differential Hall effect measurement method (DHE) for ultrathin Si and SiGe layers for the investigation of dopant activation in the surface region with sub-nanometre resolution. In the case of SiGe, which constitutes the most challenging process, we show the reliability of the SC1 chemical solution (NH4OH/H2O2/H2O) with its slow etch rate, stoichiometry conservation and low roughness generation. The reliability of a complete DHE procedure, with an etching step as small as 0.5 nm, is demonstrated on a dedicated 20 nm thick SiGe test structure fabricated by CVD and uniformly doped in situ during growth. The developed method is finally applied to the investigation of dopant activation achieved by advanced annealing methods (including millisecond and nanosecond laser annealing) in two material systems: 6 nm thick SiGeOI and 11 nm thick SOI. In both cases, DHE is shown to be a uniquely sensitive characterisation technique for a detailed investigation of dopant activation in ultrashallow layers, providing sub-nanometre resolution for both dopant concentration and carrier mobility depth profiles.

Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption

The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the poss...

Piezoresistive silicon nanowire resonators as embedded building blocks in thick SOI

The use of silicon nanowire resonators in nanoelectromechanical systems for new-generation sensing and communication devices faces integration challenges with higher-order structures. Monolithic and deterministic integration of such nanowires with the surrounding microscale architecture within the same thick crystal is a critical aspect for the improvement of throughput, reliability and device functionality. A monolithic and IC-compatible technology based on a tuned combination of etching and protection processes was recently introduced yielding silicon nanowires within a 10 m-thick device layer. Motivated by its success, the implications of the technology regarding the electromechanical resonance are studied within a particular setting, where the resonator is co-fabricated with all terminals and tuning electrodes. Frequency response is measured via piezoresistive readout with frequency down-mixing. Measurements indicate mechanical resonance with frequencies as high as 100 MHz exhibiting a Lorentzian behavior with proper transition to nonlinearity, while Allan deviation on the order of 3–8 ppm is achieved. Enabling the fabrication of silicon nanowires in thick silicon crystals using conventional semiconductor manufacturing, the present study thus demonstrates an alternative pathway to bottom-up and thin silicon-on-insulator approaches for silicon nanowire resonators.

Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond

In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate length. We propose a U-channel fully depleted silicon on insulator architecture that starts off with a thicker SOI (8–11 nm) and has a U-shaped channel enabled by a recessed metal gate. This device improves the electrostatics by increasing the overall gate length at fixed metal gate opening, mitigating drain field coupling to the source due to the recessed metal gate region and having thin SOI below the center of the device (4–5 nm). Modeling shows that good electrostatics can be maintained at small metal gate opening to enable pitch scaling. This device provides lower cost options for mobile and IOT technologies.

A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

Experimental Study on Deformation Potential (<inline-formula> <tex-math notation="LaTeX">${D}_{{{ac}}}$ </tex-math> </inline-formula>) in MOSFETs: Demonstration of Increased <inline-formula> <tex-math notation="LaTeX">${D}_{{{ac}}}$ </tex-math> </inline-formula> at MOS Interfaces and Its Impact on Electron Mobility

Deformation potential ( $D_{ac}$ ), which is one of the most important parameters determining the rate of electron–acoustic phonon scattering, in Si around MOS interfaces is thoroughly studied with regard to the dependences on surface carrier densities, back-gate biases, and device structures. It is demonstrated that $D_{ac}$ increases sharply at the MOS interface. To investigate the impact of the increased $D_{ac}$ on $\mu _{e}$ , thick body-channel SOI MOSFETs, where drain current flows in the entire SOI layers, was fabricated. The carrier transport experiments reveal that $\mu _{e}$ of greater than 1100 cm $^{2}\text{V}^{-1}\text{s}^{-1}$ is obtained in body-channel SOI MOSFETs with the SOI thickness of greater than 70 nm. By taking into account the $D_{ac}$ profile around the MOS interface, experimental $\mu _{e}$ of SOI MOSFETs is numerically reproduced over a wide range of SOI thicknesses. $\mu _{e}$ of the body-channel SOI MOSFETs is also well reproduced using the same $D_{ac}$ profile. Thus, it is concluded that $D_{ac}$ increases sharply at the Si/SiO2 interface. The accurate modeling of the increased $D_{ac}$ around the Si/SiO2 interface is indispensable for designing high-performance and/or low-power 3-D MOSFETs including FinFETs, extremely thin SOI MOSFETs, and nanowire MOSFETs, because these types of MOSFETs have greater interface-to-volume ratios.

Modal spectrum engineering of multilayer optical waveguides: towards digital vertical multimode interference couplers

A new technique is proposed for improving the coupling efficiency of vertical multimode interference couplers. The technique replaces conventional multimode waveguides with multilayer waveguides (MLWs) in the design of these couplers. The separation between the high refractive index layers of the MLWs is modulated to fit the propagation constants of their guided modes to the ideal parabolic profile required for perfect coupling. Numerical computations of the proposed couplers demonstrate the ability to transfer 86 % of optical power between 220-nm thick SOI waveguides at a vertical separation of 2.3 μm.

Test beam results of a depleted monolithic active pixel sensor using an HV-SOI process for the LH-LHC upgrade

A Depleted Monolithic Active Pixel Sensor (DMAPS) on thick film SOI technology is being extensively investigated as a possible candidate for the outer layers of the ATLAS Inner Tracker in the HL-LHC upgrade. Its radiation hardness to TID (Total Ionizing Dose) and the absence of back gate effect for a dose of up to 700 Mrad was proven. Its charge collection properties have been characterized with radioactive sources and with eTCT (edge Transient Current Technique) measurements for both, unirradiated and irradiated devices. This article presents the first test beam results on this DMAPS on thick film SOI technology. The charge collection properties, charge sharing between pixel cells, spatial resolution and tracking efficiency are presented as a function of the applied bias voltage and different selection criteria.

Charge collection properties of a depleted monolithic active pixel sensor using a HV-SOI process

New pixel detector concepts, based on commercial high voltage and/or high resistivity CMOS processes, are being investigated as a possible candidate to the inner and outer layers of the ATLAS Inner Tracker in the HL-LHC upgrade. A depleted monolithic active pixel sensor on thick film SOI technology is being extensively investigated for that purpose. This particular technology provides a double well structure, which shields the thin gate oxide transistors from the Buried Oxide (BOX). In addition, the distance between transistors and BOX is one order of magnitude bigger than conventional SOI technologies, making the technology promising against its main limitations, as radiation hardness or back gate effects. Its radiation hardness to Total Ionizing Dose (TID) and the absence of back gate effect up to 700 Mrad has been measured and published [1]. The process allows the use of high voltages (up to 300V) which are used to partially deplete the substrate. The process allows fabrication in higher resistivity, therefore a fully depleted substrate could be achieved after thinning. This article shows the results on charge collection properties of the silicon bulk below the BOX by different techniques, in a laboratory with radioactive sources and by edge Transient Current Technique, for unirradiated and irradiated samples.

200-V High-side thick-layer SOI field p-channel LDMOS with multiple field plates

A high-voltage thick layer SOI field p-channel LDMOS (pLDMOS) with multiple field plates based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. Multiple field plates constructed by polysilicon and metal layer are adopted to modulate electric field distribution of the depleted drift region. The SOI field pLDMOS with off-state breakdown voltage (BV) of −240 V is experimentally realized, which can be widely used for simplifying the design of level shifting.

Hot-carrier-induced linear drain current and threshold voltage degradation for thin layer silicon-on-insulator field P-channel lateral double-diffused metal-oxide-semiconductor

Hot-carrier-induced linear drain current (Idlin) and threshold voltage (Vth) degradations for the thin layer SOI field p-channel lateral double-diffused MOS (pLDMOS) are investigated. Two competition degradation mechanisms are revealed and the hot-carrier conductance modulation model is proposed. In the channel, hot-hole injection induced positive oxide trapped charge and interface trap gives rise to the Vth increasing and the channel conductance (Gch) decreasing, then reduces Idlin. In the p-drift region, hot-electron injection induced negative oxide trapped charge enhances the conductance of drift doping resistance (Gd), and then increases Idlin. Consequently, the eventual Idlin degradation is controlled by the competition of the two mechanisms due to conductance modulation in the both regions. Based on the model, it is explained that the measured Idlin anomalously increases while the Vth is increasing with power law. The thin layer field pLDMOS exhibits more severe Vth instability compared with thick SOI layer structure; as a result, it should be seriously evaluated in actual application in switching circuit.

Two-port multimode interference reflectors based on aluminium mirrors in a thick SOI platform.

Multimode interference reflectors (MIRs) were recently introduced as a new type of photonic integrated devices for on-chip, broadband light reflection. In the original proposal, different MIRs were demonstrated based on total internal reflection mirrors made of two deep-etched facets. Although simpler to fabricate, this approach imposes certain limits on the shape of the field pattern at the reflecting facets, which in turn restricts the types of MIRs that can be implemented. In this work, we propose and experimentally demonstrate the use of aluminium-based mirrors for the design of 2-port MIRs with variable reflectivity. These mirrors do not impose any restrictions on the incident field, and thus give more flexibility at the design stage. Devices with different reflectivities in the range between 0 and 0.5 were fabricated in a 3 um thick SOI platform, and characterization of multiple dies was performed to extract statistical data about their performance. Our measurements show that, on average, losses both in the aluminium mirror and in the access waveguides reduce the reflectivities to about 79% of their target value. Moreover, standard deviations lower than ±5% are obtained over a 20 nm wavelength range (1540-1560 nm). We also provide a theoretical model of the aluminium mirror based on the effective index method and Fresnel equations in multilayer thin films, which shows good agreement with FDTD simulations.

An analytical model for the resonance frequency of square perforated Lamé-mode resonators

In this work, simple analytical models based on the concept of an equivalent material are used to describe the mechanical behavior of resonators perforated by a regular array of square holes, a common occurrence in several MEMS devices and sensors. This description is applied to the determination of the resonance frequency of Lamé-mode square resonators, which are frequently pursued as high-Q MEMS resonators. The models predictions are compared with FEM simulations and experimental data both from the literature and from measurements obtained by the authors on thick SOI MEMS resonators. The models predictions are in good accordance both with FEM results and with experimental data.

(Invited) Special Memory Mechanisms in SOI Devices

While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a technology barrier. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. Several floating-body 1T-DRAM variants with planar or multi-gate configuration have been proposed. We will show that 1T-DRAMs are also compatible with the ’unified memory’ paradigm: combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We will focus on our novel concepts, by addressing the device architecture, operating mechanisms, and scaling issues. MSDRAM – The device is based on the MSD hysteresis effect. The back channel is biased in moderate inversion and the front gate in strong accumulation such as to trigger B2BT that rapidly fills the body with holes (state ‘1’: high current). If B2BT is inhibited, there is no current flowing (state ‘0’). A wide memory window is obtained and the current ratio I1/I0exceeds 6 orders of magnitude. Specific source and drain architectures and ultrathin BOX allow enhancing the retention time while reducing the programming voltage, back-gate bias and power consumption. We present recent experiments in small-area MOSFETs that confirm the key assets of the MSDRAM. ARAM FAMILY – The ARAM concept consists in adding a middle oxide (MOX) in the body. The upper semi-body serves for hole storage and the lower semi-body for electron current sensing. To write ‘1’, excess holes are generated by impact ionization or B2BT in the upper semi-body. These holes induce a dynamic increase of the upper semi-body potential, which allows an electron current to flow in the lower semi-body via electrostatic coupling. If no holes are stored, the lower semi-body is fully depleted and no current flows (state '0'). The A2RAM has the body composed of a fully depleted P-layer on top of a thin N+layer, without MOX. Encouraging results have recently been obtained on thin and thick SOI structures. A(2)RAM principles are also applicable in DG MOSFETs and FinFETs. Z2-RAM – The Z2-FET is a forward-biased PIN diode, where the fully depleted body is only partially covered by the gate. At low drain voltage the diode is initially blocked because the front and back gates are biased to form potential barriers that prevent the injection of electrons and holes from the N and P contacts, respectively. This gate biasing emulates a PNPN thyristor configuration, but without any body doping. To program the ‘1’ or ‘0’ states, holes are stored or not under the negatively biased gate. Memory readout consists in discharging the stored charge that turns on the Z2-FET. In ‘0’ state, there is no discharge current and the diode remains blocked. UNIFIED MEMORY – The URAM combines non-volatile memory (NVM) and DRAM functionalities in a single transistor. A NVM charge trapping layer (ONO) is added to the 1T-DRAM structure. Electrons injected and trapped in the silicon nitride layer by Fowler Nordheim or hot carrier mechanisms, modify the MOSFET threshold voltage. Simultaneously, the floating body is used as a storage volume for the 1T-DRAM function. Our results demonstrate the feasibility of URAM in FinFETs with ONO BOX. In conclusion, the floating-body capacitorless DRAM is a very attractive memory device. There are several competing 1T-DRAM options among which the technologists and circuit designers will make the selection. B2BT is efficient for ‘1’ state programming, whereas capacitive coupling is suitable for ‘0’ state. 1T-DRAM volatile memory capability can be enriched by adding nonvolatile charge storage.

Demonstration of a Hybrid Opto-Electronic Transmitter on SoI for Access Networks

We present a hybrid integrated transmitter comprised of an InP/InGaAsP electro-absorption modulated laser (EML) electrically driven by a BiCMOS SiGe electronic circuit on 4- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex> </formula> SoI substrate. The EML includes an electro-absorption modulator integrated together with a distributed feedback laser and a spot-size expander. The modulator driver is fabricated using the SiGe BiCMOS approach with 2.5 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{\rm p\hbox{-}p}$</tex></formula> nominal output swing. Both elements have been flip-chip mounted on a thick SoI board using 14- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\rm m}$</tex></formula> gold-tin bumps and employing a high accuracy flip-chip bonder. The photonic chip has a footprint of 7 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm mm}^{2}$</tex></formula> and consumes a power of 0.8 W. We test the device optically and electrically demonstrating error-free operation at 10 and 20 Gb/s.

Demonstration of a vertical pin Ge-on-Si photo-detector on a wet-etched Si recess

In this paper, we demonstrate a vertical pin Ge-on-Si photo-detector on a wet-etched Si recess on a SOI wafer. A 120 nm-deep Si recess is etched on the SOI wafer with a 340 nm-thick top Si layer by the TMAH solution. The measured results show that the responsivity is more than 0.60 A/W for TE polarization and is more than 0.65 A/W for TM polarization at 1550 nm wavelength. Compared to the photo-detector without the Si recess, the responsivities for both TE and TM polarizations are improved by ~10%. A low dark current of 170 nA is achieved at a bias voltage of -1 V. And, the 3 dB-bandwidth at a bias voltage of -3 V is 21.5 GHz. This approach can be used to improve the coupling and absorption for high responsivity of photo-detector while maintain its high speed on a thick SOI platform based on the simulation results.