Path Delay Fault Testing Research Articles

On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis

We propose a method to estimate fault efficiency of test patterns for path delay faults. In path delay fault testing, fault coverage of test patterns is usually very low, because circuits have not only a lot of paths but also a lot of untestable paths. Although fault efficiency would be better metric to evaluate test patterns rather than fault coverage, it is too difficult to compute it exactly, if we do not compute the total number of untestable paths exactly. The proposed method samples a part of paths after untestable path analysis, and estimate fault efficiency based on the percentage of untestable paths in the sample paths. Through our experimental results, we show that the proposed method can accurately estimate fault efficiency of test patterns in a reasonable time. Also, since the accuracy of fault efficiency estimated with the proposed method depends on how to sample the paths, we look into the influence of path sampling methods to the accuracy in the experiments.

On-chip embedding mechanisms for large sets of vectors for delay test

On-chip embedding of deterministic patterns is used for built-in test-pattern generation of large sets of vector pairs for path delay fault testing. A hardware efficient two-phase synthesis procedure is proposed to synthesize the test-pattern generator. Acceptable test-cycle requirements are met using a recent method, which reduces the test embedding problem to that of embedding the first vector in each pair. The approach is generalized to implement a hardware efficient on-chip pattern generator to test the embedded cores of a system on chip. The hardware overhead of the proposed method is reduced at a controllable increase on the number of test cycles.

Delay Fault Testing of Processor Cores in Functional Mode

This paper proposes an efficient methodology of delay fault testing of processor cores using their instruction sets. These test vectors can be applied in the functional mode of operation, hence, self-testing of processor core becomes possible for path delay fault testing. The proposed approach uses a graph theoretic model (represented as an Instruction Execution Graph) of the datapath and a finite state machine model of the controller for the elimination of functionally untestable paths at the early stage without looking into the circuit details and extraction of constraints for the paths that can potentially be tested. Parwan and DLX processors are used to demonstrate the effectiveness of our method.

Efficient identification of (critical) testable path delay faults using decision diagrams

We present a novel framework to identify all the testable and untestable path delay faults (PDFs) in a circuit. The method uses a combination of decision diagrams for manipulating PDFs as well as Boolean functions. The approach benefits from processing partial paths or fanout-free segments in the circuit rather than the entire path. The methodology is modified to identify all testable critical PDFs under the bounded delay fault model. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology outperforms any existing method for identifying testable PDFs. Its scalability by focusing on critical PDFs is demonstrated by experimenting on very path-intensive benchmarks.

Efficient identification of (critical) testable path delay faults using decision diagrams

We present a novel framework to identify all the testable and untestable path delay faults (PDFs) in a circuit. The method uses a combination of decision diagrams for manipulating PDFs as well as Boolean functions. The approach benefits from processing partial paths or fanout-free segments in the circuit rather than the entire path. The methodology is modified to identify all testable critical PDFs under the bounded delay fault model. The effectiveness of the proposed framework is demonstrated experimentally. It is observed that the methodology outperforms any existing method for identifying testable PDFs. Its scalability by focusing on critical PDFs is demonstrated by experimenting on very path-intensive benchmarks.

A new classification of path-delay fault testability in terms of stuck-at faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.

Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged.

Path delay fault testing of multiplexer-based shifters

In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are not single path propagating hazard free robustly testable (SPP-HFRT) and we present a path selection method such that all the selected paths are SPP-HFRT by (Olog2 n) test-vector pairs, where n is the length of the shifter's operand. The propagation delay along all other paths is a function of the delays along the selected paths. This is the first work addressing the problem of shifter path delay fault testing.

Path delay fault diagnosis and coverage-a metric and an estimation technique

Published research on path delay fault (PDF) testing has largely focused on the PDF classification and test-vector generation problems. Little attention has been paid to the diagnosis of delay faults and in defining realistic metrics for delay-fault coverage, We present a statistical diagnosis framework to detect which parts of the circuit are likely to have caused a chip failure for a set of delay-fault tests. Under a model where distributed fabrication-process perturbations contribute to the occurrence of delay faults, we also find the associated likely fabrication-process parameter deviations from their nominal values as part of the diagnosis framework. We present results of experiments performed on some International Symposium on Circuits and Systems 1989 (ISCAS'89) benchmark circuits and also relate the slack of a path segment to its probability of contributing to the circuit failure. We also quantify the diagnosability of a PDF for a test and develop a methodology based on our statistical diagnosis framework to determine the diagnosability of each PDF detected by a given test set. We apply this approach to find the diagnosability of robust PDFs for the ISCAS'89 benchmark circuits. Furthermore, we propose a new and realistic definition of delay-fault coverage based on the percentage of fabricated faulty chips that can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay-fault sizes caused by the chip manufacturing process as opposed to previously defined metrics that have been based primarily on the percentage of faults tested. We present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of PDFs caused by distributed fabrication-process variations. We use the results for the ISCAS'89 benchmark circuits to demonstrate wide discrepancies between PDF coverage estimates for robust test sets obtained using our realistic definition and the ones obtained by using the traditional notion of coverage as the percentage of paths tested.

Testable Path Delay Fault Cover for Sequential Circuits

We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently affect the performance of the circuit, or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is a smaller fault set and possibly a smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or do not have to be examined for delay defects.

A probabilistic model for path delay fault testing

Testing path delay faults (PDFs) in VLSI circuits is becoming an important issue as we enter the deep submicron age. However, it is difficult in general since the number of faults is normally very large and most faults are either hard to sensitize or are untestable. In this paper, we propose a probabilistic PDF model. We investigate probability functions for the wire and path delay size to model the fault effect in the circuit under test. In our approach, the delay fault size is assumed to be randomly distributed. An analytical model is proposed to evaluate the PDF coverage. We show that the delay sizes of the untested paths are actually reduced if these paths are conjoined with other tested good paths. Therefore, using our approach, path selection and synthesis of PDF testable circuits can be done more accurately. Also, given a test set, more accurate fault coverage can be predicted by calculating the mean delay of the paths.

Synthesis of symmetric functions for path-delay fault testability

A new technique of synthesizing totally symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit can be made robustly path-delay fault testable, if the constituent unate functions are synthesized as two-level irredundant circuits. Nonconsecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The circuit cost of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results shows that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn, reduces testing time, as compared to those of the best-known earlier methods.

Functionally testable path delay faults on a microprocessor

The impact of delay defects on these functionally untestable paths on overall circuit performance involves identification of such paths determining the achievable path delay fault coverage and reducing the subsequent test generation effort. The experimental results for two microprocessors (Parwan and DLX) indicate that a significant percentage of structurally testable paths are functionally untestable.

A fast nonenumerative automatic test pattern generator for path delay faults

This paper presents a nonenumerative automatic test pattern generator for robustly testable path delay faults. In contrast to earlier work by I. Pomeranz, et al. (see IEEE Trans. Computer-Aided Design, vol. 14, p. 1505-15, Dec. 1995), the pattern generator takes into consideration the conditions for robust propagation while sensitizing sets of paths. This increases the probability of testing them robustly with a single test. Novel algorithms are described which identify sets that contain many such potentially compatible paths. The number of detected faults is estimated using a simple and fast method. The approach compares favorably to that of Pomeranz et al. in both fault detection and time performance.

Maximum weighted independent sets on transitive graphs and applications

We present a polynomial-time algorithm that finds the maximum weighted independent set of a transitive graph. The studied problem finds applications in a variety of VLSI contexts, including path delay fault testing, scheduling in high-level synthesis, and channel routing in physical design automation. The algorithm has been implemented and incorporated in a CAD tool for path delay fault testing. We experimentally verify its impact in the latter context.

Design-for-testability for path delay faults in large combinational circuits using test points

We present a method for test-point insertion in large combinational circuits, to increase their path delay fault testability. Using an appropriate test application scheme with multiple clock periods, a test point on a line g divides the set of paths through g for testing purposes into a subset of paths from the primary inputs up to g, and a subset of paths from g to the primary outputs. Each one of these subsets can be tested separately. The number of paths that need to be tested directly is thus reduced. In addition, by breaking an untestable path into two or more testable subpaths, it is possible to obtain a fully testable circuit. Test-point insertion is done to reduce the number of paths, using a time-efficient procedure. Indirectly, it also reduces the number of tests and renders untestable paths testable. When the number of paths is sufficiently small, and if the test generation procedure to be used for the circuit is known, a procedure is given to perform test-point insertion directly targeting the path delay faults that are still untestable. Experimental results are presented to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits, and to demonstrate the overheads involved.

Functional test generation for delay faults in combinational circuits

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults

A new simulation-based method uses single-input change (SIC) vectors to derive tests efficiently for singly testable (ST) path-delay faults (PDFs). A PDF is ST if there exists a delay test that guarantees its detection when it is the only PDF in the circuit. It is known that an ST PDF must have a single-input change test. We utilize this result and present a fault simulator that is specifically tuned to simulate single-input change vectors efficiently. We assign random values to all inputs, and then propagate rising and falling transitions from each input while all other inputs are held steady. We present a 16-valued algebra with which rising and falling PDF's from all inputs are concurrently simulated. Using a suitable encoding for signal values, gates are evaluated directly through Boolean operations, and all computation stages use machine word parallelism. Results on the ISCAS'85 and '89 benchmarks show that the approach is superior to another published method in terms of both fault coverage and execution time.

Deriving logic systems for path delay test generation

We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for rated-clock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.

Partial-scan delay fault testing of asynchronous circuits

Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. Previous work has shown that full-scan delay-fault testing of asynchronous circuits is feasible. In this work, we tackle the problem of partial-scan testing, which requires test-pattern generation on a sequential circuit. We show how this problem can be effectively reduced to a classical problem of stuck-at test-pattern generation for a related combinational circuit. The reduction is done in three steps. The first step reduces testing of an asynchronous sequential circuit, by using a partial-scan approach, to testing an object called an asynchronous net, in which feedback is allowed only inside asynchronous memory elements. We then decompose the problem of testing asynchronous nets into that of initializing memory elements (the second step), followed by robust path delay fault testing (the third step). We provide effective procedures to solve both the initialization and the test-pattern generation problem. The technique is complete, automated, and requires only partial scan of some memory element outputs.