Path Delay Fault Testing Research Articles

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Applying ROBDDs for Logical Circuit Delay Testing

Increasing frequency of functioning and decreasing transistor sizes in high performance logical circuits may result in illegal capacities, inductivities, resistances, and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits within the path delay fault (PDF) model. In this paper, facilities of enhancing PDF test sequence quality based on application of Reduced Ordered Binary Decision Diagrams (ROBDDs) that compactly represent all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is established that using of these ROBDDs cut the lengths of test sequences by more than 1/3 in comparison with traditional scan test sequences simultaneously enhancing test sequence quality. In particular, we derive test sequences for robust testable PDFs of sequential circuits decreasing their power consumption and peak power values.

Finding Test Pairs for PDFs in Logic Circuits Based on Using Operations on ROBDDs

A method of finding all test pairs for robust testable Path Delay Faults (PDFs) is suggested. In foreign literature, the authors find only one or several subsets of the test pairs. In this paper, the test pairs are formed from sequential sets and represented compactly by the Reduced Ordered Binary Decision Diagram (ROBDD). In this paper, the test pairs are formed from adjacent test patterns. All such test pairs are compactly represented by the ROBDD. Having got all test pairs for a path, we may derive a test sequence detecting the robust PDFs of the path in sequential circuits without using Scan techniques. In addition, having got the above-mentioned ROBDDs for a set of paths, we may find compact test sets for the Scan techniques oriented to decreased power consumption during testing. Finding all test pairs is reduced to deriving a Boolean difference for the path considered. The Boolean difference is obtained by applying operations on ROBDDs involved from the combinational part fragments of a sequential circuit. The Boolean difference is also represented by the ROBDD.

Path delay test generation at functional level

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults

We present a symbolic-event-propagation-based scheme to generate hazard-free tests for robust path delay faults. This approach identifies all robustly testable paths in a circuit and the corresponding complete set of test vectors. We address the problem of finding a minimal set of test vectors that covers all robustly testable paths. We propose greedy and simulated-annealing-based algorithms to find the same. Results on ISCAS89 benchmark circuits show a considerable reduction in test vectors for covering all robustly testable paths.

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

Power supply noise and crosstalk are the two major noise sources that are pattern dependent and negatively impact signal integrity in digital integrated circuits. These noise sources play a greater role in sub-65nm technologies and may cause timing failures and reliability problems in a design; thus must be carefully taken into consideration during test pattern generation and validation. In this paper, we propose a novel method to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. It quantifies the noises with a pattern quality value (Q) using the activated aggressor gates and nets information. The proposed method offers design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. By evaluating the failed test pattern, the proposed method can be used to help identify the root cause during failure analysis. Simulation results demonstrate the efficiency and effectiveness of the pattern grading procedure.

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

The significance of redundant technologies for improving dependability and delay fault testability are growing. So, delay fault testing on two-rail logic circuits well known as a class of redundant technologies will become important. Two-rail logic circuits can be efficiently tested by noncodeword vector pairs. However, noncodeword vector pairs may sensitize some faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with noncodeword vector pairs may be overtesting. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the overtesting. The amounts of test data for the proposed test sets are, on average, 28.2 percent less than those for the test sets, which are obtained by the existing construction for unate circuits and lead to the overtesting.

Sizes of test sets for path delay faults using strong and weak non-robust tests

The trade-off between strong and weak non-robust tests for path delay faults considering test quality, test set size and fault coverage is discussed. It is noted that strong non-robust tests detect more combinations of delay defects. However, weak non-robust tests result in smaller test sets, and more path delay faults are detectable by weak non-robust tests. A test generation strategy that mixes strong and weak non-robust tests based on this trade-off is described. Under the proposed strategy, test generation starts by generating strong non-robust tests. When the number of faults detected by each additional test drops below a certain level, indicating that low levels of compaction are achieved, test generation switches to weak non-robust tests. The authors study appropriate switching points experimentally by using a test selection procedure to construct mixed test sets. They also consider the effects of adding power constraints on the mix of strong and weak non-robust tests.

Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture

Scan architecture is one of designs for tests (DFTs). In scan architecture, some or all of flip-flops (FFs) in a circuit are serially connected and form a scan chain. The Chiba-scan is one of scan architectures facilitating delay testing. The Chiba-scan has many advantages such as small area overhead comparable to that of the standard scan architecture and complete fault coverage for robust testable path delay faults. However, its test volume is much larger than that of other scan architectures. This paper presents a test volume reduction method for robust path delay fault testing on the Chiba-scan. In this method, scan FFs are reordered. The experimental results give evidence that the proposed method reduces the number of test vectors by 18.4% for ISCAS89 benchmark circuits. Furthermore, the proposed method enables testing with 16.8% shorter test application time (TAT) and 18.3% lower required memory size for automatic test equipment (ATE) compared with those for the enhanced scan architecture.

Chiba Scan Delay Fault Testing with Short Test Application Time

Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits, the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition, in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift (LoS) testing with the same TAT.

Diagnosis of path delay faults based on low-coverage tests

Fault diagnosis processes consider the fact that a circuit fails a test as carrying more information than if the circuit passes a test. As a result, tests that detect smaller numbers of faults are likely to result in more accurate fault diagnosis. We study the existence of low-coverage tests, which detect small numbers of faults, for stuck-at faults, transition faults and path delay faults. The study shows that such tests are prevalent for path delay faults. We discuss the use of low-coverage tests for diagnosis of path delay faults, and describe a procedure for generating low-coverage tests for path delay faults.

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits

The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding

This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test

The peak power dissipated in nonscan logic during fast capture cycles of scan-based two-pattern tests for path delay faults is considered. It is first demonstrated that the peak-power dissipation for an enhanced-scan test set, which has the smallest peak-power dissipation, is lower than that for a skewed-load test set and that the peak-power dissipation for a skewed-load test set, which has the smallest peak-power dissipation, is typically (but not always) lower than that for a broadside test set. Test sets that consist of more than one type of tests are then considered. Skewed-load and broadside tests may be used together to improve the fault coverage when this is permissible by a standard scan design. It is demonstrated that using both types of tests can sometimes reduce the peak-power dissipation. Results are also presented of an experiment where an arbitrary test set of one type is modified to reduce the peak power without reducing the fault coverage by introducing tests of another type.

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

A new framework for generating test sets with high test efficiency for path delay faults (PDFs) is presented. The proposed method is based on a data structure that can implicitly represent all sens...

Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects

We propose a new path delay fault model called the transition path delay fault model. This model addresses the following issue. The path delay fault model captures small extra delays, such that each one by itself will not cause the circuit to fail, but their cumulative effect along a path from inputs to outputs can result in faulty behavior. However, non-robust tests for path delay faults may not detect situations where the cumulative effect of small extra delays is sufficient to cause faulty behavior after any number of extra delays are accumulated along a subpath. Under the new path delay fault model, a path delay fault is detected when all the single transition faults along the path are detected by the same test. This ensures that if the accumulation of small extra delays along a subpath is sufficient to cause faulty behavior, the faulty behavior will be detected due to the detection of a transition fault at the end of the subpath. We discuss the new model and present experimental results to demonstrate its viability as an alternative to the standard path delay fault model. We describe an efficient fault simulation procedure for this model. We also describe test generation procedures. An efficient test generation procedure we discuss combines tests for transition faults along the target paths in order to obtain tests that satisfy the requirements of the new model.

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors

Aggressive processor design methodology using high-speed clock and deep submicrometer technology is necessitating the use of at-speed delay fault testing. Although nearly all modern processors use pipelined architecture, no method has been proposed in literature to model these for the purpose of test generation. This paper proposes a graph theoretic model of pipelined processors and develops a systematic approach to path delay fault testing of such processor cores using the processor instruction set. The proposed methodology generates test vectors under the extracted architectural constraints. These test vectors can be applied in functional mode of operation, hence, self-test becomes possible. Self-test in a functional mode can also be used for online periodic testing. Our approach uses a graph model for architectural constraint extraction and path classification. Test vectors are generated using constrained automatic test pattern generation (ATPG) under the extracted constraints. Finally, a test program consisting of an instruction sequence is generated for the application of generated test vectors. We applied our method to two example processors, namely a 16-bit 5-stage VPRO pipelined processor and a 32-bit pipelined DLX processor, to demonstrate the effectiveness of our methodology

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability

A technique for implementing totally symmetric Boolean functions using hierarchical modules is presented. First, a simple cellular module is designed for synthesizing unate symmetric functions. The structure is universal, admits a recursive design, and uses only 2-input AND-OR gates. A universal test set of size (n2/8 + 3n/4) for detecting all single stuck-at faults can be easily determined for an n-input module, where n = 2k, k � 3. General symmetric functions are then realized following a unate decomposition method. The synthesis procedure guarantees full robust path-delay fault testability in the circuit. Experimental results on several symmetric functions reveal that the hardware cost of the proposed design is low, and the number of paths in the circuit is reduced significantly compared to those of earlier designs. Results on circuit area and delay for a few benchmark examples are also reported.

Layout-aware scan chain synthesis for improved path delay fault coverage

Path delay fault testing has become increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have disregarded the scan wirelength overhead. In this paper we propose a layout-aware coverage-driven scan chain ordering methodology and give exact and heuristic algorithms for computing the achievable tradeoffs between path delay fault coverage and both dummy flip-flop and wirelength costs. Experimental results show that our scan chain ordering methodology yields significant improvements in path delay coverage with a very small increase in wirelength overhead compared to previous layout-driven approaches, and similar coverage with up to 25 times improvement in wirelength compared to previous layout-oblivious coverage-driven approaches.