Test Generation Algorithm Research Articles

Test Generators Need to be Modified to Handle CMOS Designs

CMOS designs have some unique properties that prevent existing test generators from computing a test vector for a fault when one might exist. The problem lies in the premises laid out on what it takes to detect a stuck‐at fault. The basic premise that states that it is required to set a line to 0(1) in order to detect a stuck‐at 1(0) fault, and then propagate the error to an observable point, needs to be re‐examined. This is due to the existence of indeterminate states throughout the logic. The paper distinguishes between the traditional test vector (here called a hard-detect), and a potential test vector (here called a soft-detect). Our proposed test set is the union of hard and soft‐detects. We also re‐examine the issue of redundancy and show that it needs to be re‐defined in order to comply with CMOS technology behavior.This paper shows several examples to illustrate the problem; describes what it takes in order to remedy it; proposes possible enhancements to existing test generation algorithms, and outlines the risks faced in the event that no correcting steps are taken.

Forecasting the efficiency of test generation algorithms for combinational circuits

In this era of VLSI circuits, testability is truly a very crucial issue. To generate a test set for a given circuit, choice of an algorithm from a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the Genetic Algorithm is used in order to construct an accurate model for some existing test generation algorithms that are being used everywhere in the world. Some objective quantitative measures are used as an effective tool in making such choice. Such measures are so important to the analysis of algorithms that they become one of the subjects of this work.

Bridging Faults in Pipelined Circuits

This paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and Iddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case.

Parallel VLSI test in a shared-memory multiprocessor

This paper presents three parallel procedures implemented in a shared-memory multiprocessor to generate the patterns that allow the testing of digital circuits. The implementation of these procedures in a multiprocessor uses the system memory better than in a distributed-memory multicomputer, since it is not necessary to store the circuit structure in the local memory of each processor, besides other common structures. The parallel test generation procedures are based on a new sequential algorithm which mixes both the Boolean difference and digital spectral techniques. It is thus different from other methods proposed that deal with the parallelization of test generation algorithms that carry out an implicit enumeration of the input pattern space. The first procedure distributes the set of faults using a backtracking procedure starting from a primary output and allocating a similar number of lines to each processor. The second procedure distributes the set of faults among the processors taking into account the distance from each line to its nearest primary output; it then applies the algorithm to generate the test pattern with some modifications. The third procedure uses a circuit partitioning procedure which allows similar sized parts of the circuit to be assigned to each processor while communications between processors are minimized. The experimental results obtained when the procedures are applied to the usual benchmark circuits (the ISCAS set) show figures for speedup better than in a multicomputer, although fewer processors are used. Copyright © 2000 John Wiley & Sons, Ltd.

An RTL Abstraction Technique for Processor MicroarchitectureValidation and Test Generation

Design validation is becoming more and more a bottleneck in the microprocessor design process. The difficulty of validation stems from the complexity of the design, which requires searching an enormous space to check correctness. This is exacerbated by features for enhancing performance, such as pipelines, which are becoming common in most microprocessors. This paper describes a new abstraction technique to handle this problem. Our solution is a novel method to identify the control states automatically from the processor HDL description and to extract an abstract finite state machine model which preserves the behaviors of the design accurate to the clock cycle, so that the state space to be analyzed is drastically reduced. This model is used to evaluate microarchitecture-level coverage of validation tests. We also present validation test generation algorithm for traversing state transition paths and covering snapshot and temporal events. These abstract paths with a finite length, along with information about the instruction set, are used to generate system-level tests. Results on example microprocessor models show the technique is efficient in finding bugs that other verification methods miss.

Quality of service enforcement for distributed objects

As the number of industrial organisations that adopt the use of shared distributed objects as the vehicle for implementing large software systems increases, new quality issues arise. Four algorithms are presented that are designed to enforce different quality of service criteria for shared distributed objects that have been tested using a previously introduced test generation algorithm. Empirical assessments of these algorithms for three large systems are also presented. These assessments are made in terms of the simulated performance of each system on average loads selected from operational distributions collected during beta release and field use, assuming both Poisson and bursty arrival processes. Heavy loads designed to cause the overall CPU utilisation rates to exceed 90% of capacity were also run.

Dynamic NOR-NOR PLA design with IDDQ testability

Certain logic functions such as the control units of VLSI processors are difficult to be implemented by random logic. Since the programmable logic arrays (PLAs) can implement almost any Boolean function, they have become popular devices in the realization of both combinational and sequential circuits. Besides, due to high quality demand in the semiconductor market, the testing of PLAs becomes an important issue. Because the structure of the PLAs is basically arrays of transistors or gates, the traditional test generation algorithms for stuck-at faults are hard to be employed. Thus, many test-generation approaches and designs for PLA testability have been developed. The IDDQ test is one of the effective techniques of detecting both bridge faults and open faults in CMOS integrated circuits. We present a testability configuration of PLAs which will be transformed into inverters in the test mode so that the IDDQ testing with only two test vectors and low overhead circuitry for the detection of all the bridge faults and most of the open faults can be realized.

Sequential test generators: past, present and future

With the growth in complexity of very large scale integration (VLSI) circuits, test generation for sequential circuits is becoming increasingly difficult and time consuming. Even though the computing power and resources have multiplied dramatically over last few decades, an increasing number of memory elements in VLSI circuits require more effective and powerful sequential test generators. In this paper, we describe and illustrate the working of existing sequential circuit test generation algorithms for the VLSI circuits. We also categorize all sequential testing algorithms, and summarize their relative advantages and disadvantages. The research issues and future directions in the sequential circuit testing area are also discussed.

Partial scan design methods based on internally balanced structure

In this paper, we theoretically and experimentally show the effectiveness of partial scan design based on internally balanced structure, which is a sequential circuit capable of generating tests with a combinational test generation algorithm. Moreover, we introduce a method of extended partial scan design, which replaces part of not only flip-flops by scan flip-flops but also wires by bypass flip-flops in a sequential circuit, and propose a method of extended partial scan design based on internally balanced structure. Experimental results for benchmark circuits show that the proposed partial scan design and extended partial scan design can be implemented with low area overhead.

A rated-clock test method for path delay faults

Current test generation algorithms for path delay faults assume a variable-clock methodology for test application. Two-vector test sequences assume that the combinational logic reaches a steady state following the first vector before the second vector is applied. While such tests may be acceptable for combinational circuits, their use for nonscan sequential circuit testing is impractical. A rated-clock path delay simulator shows a large drop in coverage for vectors obtained from existing test generators that assume a variable clock. A new test generation algorithm provides valid tests for uniform rated-clock test application. In this algorithm, signals are represented for three-vector sequences. The test generation procedure activates a target path from input to output using the three-vector algebra. For an effective backward justification, we derive an optimal 41-valued algebra. This is the first time, rated-clock tests for large circuits are obtained. Results for ISCAS-89 benchmarks show that rated-clock tests cover some longest, or close to longest, paths.

Fast fault translation

Test generator algorithms may be classified by the level of circuit description they utilize. Algorithms based on a logic-gate level description of the circuit under test (CUT) are the most common. Functional algorithms utilize a functional description of the CUT. Functional test generation techniques may provide better defect coverages than do purely logic-level techniques. Multilevel test generation algorithms attempt to realize the advantages of both approaches by utilizing fault translation. Here, gate-level faults are translated to functional faults and test generation is performed at the functional level. In this paper, we develop and present new techniques for fast efficient fault translation from the logic to the functional level. These techniques are implemented in a multilevel sequential circuit test generation system. The performance of the system is investigated on benchmark circuits.

Redundancy removal and test generation for circuits with non-Boolean primitives

Production VLSI circuits typically consist of primitives like tristate buffers, bidirectional buffers, and bus configurations that assume non-Boolean values like the high-impedance state. We describe a systematic methodology for extending test generation algorithms that work on combinational circuits with only Boolean primitives to full-scan production circuits. Key features of the methodology are illustrated using the energy minimization based test generation algorithm for combinational circuits. The main features of our methodology that make the test generation algorithm practical for large production circuits are: (1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure; (2) the function of non-Boolean primitives is separated into Boolean and non-Boolean components with energy functions required only for the Boolean component; and (3) non-Boolean components are implicitly considered in the energy minimization procedure. In this process, no new energy functions other than the normal Boolean gate energy functions are needed. We give a method for identifying and removing redundancies in production circuits using energy minimization. The formulation is also applicable to Boolean satisfactorily and BDD methods. We first use the test generation algorithm for identifying undetectable faults and then relax specific constraints in the original test generation problem by ignoring the non-Boolean components. We show that undetectability in the relaxed formulation implies redundancy. We report redundancy removal results for production VLSI circuits, ISCAS 85, and full-scan versions of the ISCAS 89 benchmark circuits.

Design for hierarchical testability of RTL circuits obtained by behavioral synthesis

In recent years, there has been growing interest in behavioral (high-level) synthesis for testability. This is due to the fact that testability features, such as scan or the built-in self-test, may incur large overheads if introduced during logic synthesis in the later phase of the design cycle. Related previous work attempted to generate system-level test sets using hierarchical testability during behavioral synthesis. There, the test generation scheme is independent of bit width and is, therefore, capable of handling complex controller/data path circuits with large data path bit widths (e.g., 32), which has posed a serious challenge to logic-level sequential test generators. However, this previous work is not applicable when another high-level synthesis system is used. In this paper, we present techniques that add minimal test hardware to a given register-transfer level (RTL) circuit obtained by behavioral synthesis in order to ensure that the embedded elements in the circuit are hierarchically testable. An important byproduct of our design for testability (DFT) procedure is a system-level test set that delivers precomputed test sets to each element in the RTL circuit. This eliminates the need to apply gate-level sequential test generation to the combined controller/data path. We performed extensive experiments with several complex controller/data path circuits synthesized by three different high-level synthesis systems which do not target testability. The key advantages of our method, illustrated by these experiments, include: 1) the area, delay, and power overheads incurred for testability are very low (the average area, delay, and power overheads for a large number of benchmarks are 3.5, 0.5, and 3.4%, respectively), 2) both the DFT hardware addition and test generation algorithms are independent of the data path bit width.

Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We present a longest path theorem at the module level of abstraction which specifies the requirements for path selection during delay testing. Based on this theorem, we propose a path selection procedure in module-level circuits and report efficient algorithms for delay test generation. MODET has been tested against a number of hierarchical circuits with impressive speedups in relation to gate-level test generation.

Conformance testing with labelled transition systems: Implementation relations and test generation

This paper studies testing based on labelled transition systems, presenting two test generation algorithms with their corresponding implementation relations. The first algorithm assumes that implementations communicate with their environment via symmetric, synchronous interactions. It is based on the theory of testing equivalence and preorder, as is most of the testing theory for labelled transition systems, and it is found in the literature in some slightly different variations. The second algorithm is based on the assumption that implementations communicate with their environment via inputs and outputs. Such implementations are formalized by restricting the class of labelled transition systems to those systems that can always accept input actions. For these implementations a testing theory is developed, analogous to the theory of testing equivalence and preorder. It consists of implementation relations formalizing the notion of conformance of these implementations with respect to labelled transition system specifications, test cases and test suites, test execution, the notion of passing a test suite, and the test generation algorithm, which is proved to produce sound test suites for one of the implementation relations.

The methodology of testability prediction for sequential circuits

Increasingly, test generation algorithms are being developed with the continuous creations of incredibly sophisticated computing systems. Of all the developments of testable as well as reliable designs for computing systems, the test generation for sequential circuits is usually viewed as one of the hard nuts to be solved for its complexity and time-consuming issue. Although dozens of algorithms have been proposed to cope with this issue, it still remains much to be desired in solving such problems as to determine 1) which of the existing test generation algorithms could be the most efficient for some particular circuits (by efficiency, we mean the Fault Coverage the algorithm offers, CPU time when executing, the number of test patterns to be applied, etc.) since different algorithms would be preferable for different circuits; 2) which parameters (such as the number of gates, flip-flops and loops, etc., in the circuit) will have the most or least influences on test generation so that the designers of circuits can have a global understanding during the stage of designing for testability.

FIRE: a fault-independent combinational redundancy identification algorithm

FIRE is a novel Fault-Independent algorithm for combinational REdundancy identification. The algorithm is based on a simple concept that a fault which requires a conflict as a necessary condition for its detection is undetectable and hence redundant. FIRE does not use the backtracking-based exhaustive search performed by fault-oriented automatic test generation algorithms, and identifies redundant faults without any search. Our results on benchmark and real circuits indicate that we find a large number of redundancies (about 80% of the combinational redundancies in benchmark circuits), much faster than a test-generation-based approach for redundancy identification. However, FIRE is not guaranteed to identify all redundancies in a circuit.

A method for automatic design error location and correction in combinational logic circuits

We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits. Three hypotheses are considered, that cover all single gate replacement and insertion errors. Diagnosis-oriented test patterns are generated in order to rapidly reduce the suspected area where the error lies. The originality of our method is the use of patterns which do not detect the error, in addition to detecting patterns. A theorem shows that, in favourable cases, only two patterns suffice to get a correction. We have implemented the test generation and diagnosis algorithms. Results obtained on benchmarks show that the error is always found, after the application of a small number of test patterns, with an execution time proportional to the circuit size.

Combinational test generation using satisfiability

We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set characteristic equation using straightforward but powerful greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point. For difficult faults, the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization. Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is ten times faster for those networks which have been completed by previous algorithms. Our implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms. TEGUS combines the advantages of the elegant organization of SAT-based algorithms with the efficiency of structural algorithms.

Automatic test generation algorithms for analogue circuits

The author reviews the recently published automatic test generation algorithms for analogue circuits, focusing on their applicability to specific circuit classes, limitations in more general applications and possible improvements. Selected new test generation paradigms, involving design-for-test and BIST techniques, are also discussed to indicate future directions in test generation.