Terms Of DC Research Articles

Joint Mechanism (Tunneling and Thermionic Emission) for Improved Performance of a Dielectric Modulated Transistor Biosensor

The manuscript deals with a novel biosensor structure and reports the effects of including thermionic emission in an electrically doped Tunnel FET. It comprises a comparative analysis between two biosensors based on a pure tunnelling transistor and a transistor which combines the tunnelling and thermionic emission carrier transport in the same device. The manuscript first discusses the physics of Tunnel FET when vertical thermionic emission is included with horizontal tunnelling through an additional electron source (AES). Subsequently, the biosensor is designed using the combined mechanism structure a comparative analysis of biosensors is done in terms of various DC and RF parameters for different biomolecules of proteins. Moreover, workfunction engineering is implemented to the combined mechanism biosensor and sensitivity is analyzed by drain current and transconductance.

Charging Stations for Large-Scale Deployment of Electric Vehicles

The large-scale adoption of electric vehicles will require a charging infrastructure that meets the new needs that will arise. Currently, the charging infrastructure for electric vehicles is still in the early stages of development, not least because of the low number of electric vehicles in use. However, there are still many questions to be answered when it comes to standardization in terms of connectors, DC or AC charging, and power, as well as both operational and economic issues. Although this topic has been the subject of numerous studies over the last ten years, there are still gaps to be filled, particularly with regard to the mix of different recharging strategies (normal, accelerated, fast, induction-track, etc.), as well as the economic and operational aspects. Moreover, the relationship between users and private cars is changing rapidly, and charging behaviors are not yet well established.

Analysis on the impact of interface Trap distributions on SOI DMG FinFETs: Overlap/underlap configurations

This paper investigates the significance of interface trap charges (ITCs) distribution by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator on dual-material gate (DMG) FinFETs in gate Overlap and Underlap configurations in terms of DC and analog/RF parameters. Different charge density profiles like Uniform and Gaussian distribution of traps are considered at different energy levels for both donor and acceptor ITCs to evaluate the devices reliability. It is observed that the donor traps mainly affects the OFF-state current (IOFF) by insignificantly, while, acceptor traps mainly impacts ON state current significantly. The impact of Acceptor ITCs on various parameters such as transfer characteristics, electron density, conduction band energy, transconductance (gm), total gate capacitance (Cgg), device efficiency (gm/ID), and cut-off frequency (fT), for DMG FinFETs have been comprehensively analysed at trap concentration N0=1×1013 and compared with no traps among the three devices. An acceptor trap charges with Gaussian distribution has larger impact on devices performance. It degrades the ON state-current by 36.09 %, 25.72 %, and 41.9 % for conventional, Overlap, and Underlap configurations, respectively. It is evident from the results DMG underlap configuration is more vulnerable to ITCs, attributed to its larger interface charge region due to the increase in effective channel length while, the overlap configuration is more immune towards ITCs as, lesser electrons get trapped. Thus, the overlap configuration is the most reliable among underlap and conventional configurations.

Powering Implanted Devices Wirelessly Using Spider-Web Coil

Implantable biomedical (IBM) systems and biomedical sensors can improve life quality, identify sickness, monitor biological signs, and replace the function of malfunctioning organs. However, these devices compel continuous battery power, which can be limited by the battery's capacity and lifetime, reducing the device's effectiveness. The wireless power transfer (WPT) technique, specifically magnetic resonator coupling (MRC), was utilized to address the limited battery capacity of IBMs. By using WPT–MRC, the device can obtain power wirelessly, thereby reducing the need for frequent battery replacements and increasing the device's potential. In this research, spider-web coil (S-WC) based MRC–WPT was conceived and carried out experimentally to enhance low-power IBM's rechargeable battery usage time. The presented S-WC–MRC–WPT design uses series–parallel (S–P) configuration to power the IBM. Both transmitter and receiver coils exhibit an operating oscillation frequency of 6.78 MHz. The paper reports on experiments performed in the laboratory to assess the performance of the proposed design in terms of output DC at three different resistive loads and transmission distances with alignment conditions among the receiver and the transmitter coils. Various transfer distances ranging from 10 to 100 mm were investigated to analyze the DC output current (Idc). Specifically, under a 30 V voltage source (VS) and a transfer distance of 20 mm, the DC output current was observed to be 330, 321, and 313 mA at resistive loads of 50, 100, and 150 Ω, respectively.

Reliability study of nano ribbon FET with temperature variation including interface trap charges

The nano ribbon FET (NR-FET) is an emerging device as multigate structure can be designed on a single substrate, which leads to improvement in device performance. However, the presence of multiple gate oxide and semiconductor interface creates a number of interface trap charges (ITCs), which leads to variation in device performance. In this paper, the assessment of reliability for NR-FET is performed under the impact of ITCs for different polarity. We have incorporated the ITCs along with wide variations in temperature from 200 to 500 K to study the DC, RF/analog, and linearity performance of NR-FET. It is seen that the increase in amount of positive ITCs (PITCs) leads to improvement in ON state current and less gate voltage is required to turn on the device. Also, the cut-off frequency and speed of the device can be improved through increasing the PITCs in NR-FET. The degradation in OFF state current and device efficiency (gm/ID) is observed with increased in temperature from 200 to 500 K. However, the linearity characteristics is improved at high temperature for different polarity in ITCs. This device provides ION = 9.77 × 10−4 A, IOFF = 6.23 × 10−13 A, maximum transconductance of 1.4 mS, maximum transconductance generation factor of 36.56 V−1, maximum cut-off frequency of 4.36 × 1012 Hz, delay of 39.6 ps, threshold voltage of 0.4301 V at trap level concentration of 1012 Ccm−2. It is also seen that NR-FET outperforms in terms of DC and RF/analog characteristics with the variation in temperature from 200 to 500 K. The temperature sensitivity is 150 (80) under PITC (NITC) for this NRFET. Due to its improved behaviour in wide range of temperature 200–500 K, this NR-FET can be applicable for defense and space applications.

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source and drain regions. Due to its doping-less structure, the proposed CP-ITSM-DLTFET is immune to random dopant fluctuations and does not require an expensive thermal annealing technique. This makes the proposed device’s fabrication easier and more efficient. The proposed CP-ITSM-DLTFET comprises an inverted T-shaped source metal (sandwiched between the Si-channel) and creates gate-to-source overlap and increases the tunneling area vertically on both sides of the Si-channel. The vertical line-tunneling area in the proposed structure makes the device able to be aggressively scaled compared to conventional TFETs for future technology. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. The switching performance (like high ION = 31.88 uA um−1, steeper AVSS = 23.42 mV dec−1 (over 12-order of drain current), and high ION/IOFF ratio of 1.6 × 1013) and the RF performance (like transconductance (gm) = 0.37 mS, Cut-off frequency (fT) = 90.18 GHz, and Gain Bandwidth product (GBW) = 32.3 GHz) of the proposed CP-ITSM-DLTFET are superior to almost all pre-existing Si, SiGe, and Ge based doping-less TFETs. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter has also been comprehensively studied in the paper, showing a good noise margin NMH = 0.198 V (39.8% of VDD) and NML = 0.206 V (41.2% of VDD) with a high voltage gain of 30.25 at VDD = 0.5 V, suggesting great potential for future low power applications.

Effect of Field Plate on Device Performance of Wide Bandgap HEMT

Background: Devices with field plates have gained much popularity in high power and high voltage applications. The work done in this paper is related to designing and studying the different DC and RF characteristics of a field plated GaN HEMT. The results obtained were compared with that of non-field plated GaN HEMT. This comparison and study reported the effect of field plate on device performance. Methods: A GaN HEMT device with and without a field plate was designed and simulated in the SILVACO ATLAS TCAD tool. The performance of both the devices was compared in terms of the exhibited DC and RF characteristics in order to study the effect of the field plate on the device. We have also studied the variation in the cut-off frequency and maximum frequency of both the field plate and without field plate GaN HEMT with respect to gate-source voltage. We have further investigated the device performance by varying the length of the field plate from 0 to 2.5 μm. Results: The study reflects the advantageous feature of GaN HEMT with field plate by exhibiting high breakdown voltage of 292 V in comparison to GaN HEMT without field plate which exhibits a breakdown voltage of 98 V. As a result of using field plate in the GaN HEMT structure, a rise in the Cgs and Cgd capacitances are witnessed. This in turn affects the other RF characteristics of the GaN HEMT with field plate even though the GaN HEMT with and without field plate exhibits nearly same DC characteristics. The field plated GaN HEMT exhibits a reduced cut-off frequency and maximum frequency of 7 GHz and 20 GHz, respectively, in comparison to the GaN HEMT without field plate’s cut-off frequency and maximum frequency of 10 GHz and 25 GHz, respectively. Conclusion: The study reports that using a field plate helps in enhancing the breakdown voltage but at the cost of reduced frequency performance. We have compared our proposed field plated device with different non-field plated devices and concluded that our device exhibits much higher breakdown voltage in spite of reduced device dimension. With the attainment of higher breakdown voltage our proposed GaN HEMT device can be used for high power applications. From the study, it is reported that while increasing the length of the field plate the breakdown voltage also increases. For a particular set of device dimensions, an optimum field plate length provides the highest breakdown voltage but increasing the length of the field plate beyond the optimum value results in reduction in breakdown voltage.

Spacer Engineering on Nanosheet FETs towards Device and Circuit Perspective

The Nanosheet FET (NS FET) has proven to be a potential candidate for sub-5-nm nodes. For the first time, in this manuscript, the NS FET performance is demonstrated by incorporating various device engineering at both device and circuit levels. Various device topologies like lightly doped drain/source, underlap, single and dual-k spacer are explored and the performance is compared with conventional NS FET. The NS FET with dual-k spacer is able to reduce the off current by 13.6× compared to the traditional NS FET. Further, the analog/RF figures of merit (FOMs) are assessed for various device configurations. Though the dual-k spacer outperforms in terms of DC and analog metrics, the conventional NS FET can offer better RF metrics owing to the high current. The crucial circuits for IC design such as inverter, ring oscillator, and common source (CS) amplifier are designed and evaluated the performance. The NS FET with dual-k spacer offers a gain of 1.815 for the CS amplifier and an oscillation frequency of 34.09 GHz for the 3-stage ring oscillator. The results will give insights into the performance of NS FET with various device architectures.

Optimized Artificial Intelligent Model to Boost the Efficiency of Saline Wastewater Treatment Based on Hunger Games Search Algorithm and ANFIS

Chemical oxygen demand (COD) and total organic carbon (TOC) removal efficiencies of saline wastewater treatment indicate the efficiency of the electrochemical oxidation process. Therefore, the main target of this paper is to simultaneously increase COD and TOC removal efficiencies using artificial intelligence and modern optimization. Firstly, an accurate model based on ANFIS was established to simulate the electrochemical oxidation process in terms of reaction time, pH, salt concentration, and DC applied voltage. Compared with ANOVA, thanks to ANFIS modelling, the RMSE values are decreased by 84% and 86%, respectively, for COD and TOC models. Additionally, the coefficient of determination values increased by 3.26% and 7.87% for COD and TOC models, respectively. Secondly, the optimal reaction time values, pH, salt concentration, and applied voltage were determined using the hunger games search algorithm (HGSA). To prove the effectiveness of the HGSA, a comparison with a slime mold algorithm, sine cosine algorithm, and Harris’s hawks optimization was conducted. The optimal values were found at a pH of 8, a reaction time of 36.6 min, a salt concentration of 29.7 g/L, and a DC applied voltage of 9 V. Under this condition, the maximum COD and TOC removal values were 97.6% and 69.4%, respectively. The overall efficiency increased from 76.75% to 83.5% (increased by 6.75%).

Effects of Oxygen Flow Rate on Metal-to-Insulator Transition Characteristics in NbOx-Based Selectors.

In this work, NbOx-based selector devices were fabricated by sputtering deposition systems. Metal-to-insulator transition characteristics of the device samples were investigated depending on the oxygen flow rate (3.5, 4.5, and 5.5 sccm) and the deposition time. The device stack was scanned by transmission electron microscopy (TEM) and energy-dispersive X-ray spectroscopy (EDS). The yields, including MIT, nonlinear, and Ohmic, in working devices with different deposition conditions were also evaluated. Moreover, we observed the trend in yield values as a function of selectivity. In addition, the current-voltage (I-V) curves were characterized in terms of DC and pulse endurance. Finally, the switching speed and operating energies were obtained by applying a triangular pulse on the devices, and the recovery time and drift-free characteristics were obtained by the paired pulses.

Application of harmonic included CPL‐QPHD model of GaN device for broadband PA design

In this work, a harmonic included canonical piecewise linear (CPL) function based quadratic poly-harmonic distortion (QPHD) model is presented. The proposed model employs the framework of the standard QPHD model, making use of the CPL functions for interpolation of the amplitude of the dominant input signal. Compared with the standard QPHD model, the model described in this work is able to predict transistor behavior at different levels of input powers with one single set of model coefficients. The harmonic information has also been added in this model to make it more complete. The model is validated in terms of both DC and RF behavior through simulated data of a 10 W gallium nitride (GaN) high-electron-mobility transistor (HEMT) over a wide range of load conditions and power levels. In addition, the model is implemented in advanced design system (ADS) with frequency-defined device (FDD), and applied for a broadband power amplifier (PA) design. Chebyshev low-pass topology is used for both input and output matching network design. Finally, a broadband PA is implemented with an average power added efficiency of 66.23%, an average power of 41.09 dBm, and an average gain of 13.09 dB across the operating frequency range from 0.6 to 1.7 GHz. The simulation results of the harmonic included CPL-QPHD model are highly matched with the measurement results of the designed PA, demonstrating the feasibility of applying the proposed model for broadband PA design.

DC and RF/analog performances of split source horizontal pocket and hetero stack TFETs considering interface trap charges: A simulation study

This work investigates the impact of different types of interface trap charges (ITCs) on electrical parameters of split source horizontal pocket Z shape TFET (ZHP-TFET) and Hetero Stack TFET (HS-TFET) using TCAD simulator. The acceptor type Uniform/Gaussian ITCs are considered at the oxide and semiconductor material interface. The effect of ITCs on transfer characteristics, energy band diagram (at ON, OFF, and ambipolar states), electron density, electron velocity, recombination rate, and electric field are reported for both the TFETs. Furthermore, the various RF/analog parameters like transconductance (gm), gate capacitance (CGG), cut-off frequency (fT), transconductance generation factor (TGF), and transconductance frequency product (TFP) are highlighted in the presence of ITCs for both the structures of TFET. Finally, the linearity parameters like VIP2, VIP3, IIP3, and IMD3 are extracted considering ITCs for both the structures. Simulation result reveals that the various DC, RF/analog, and linearity parameters in ZHP-TFET are more immunes towards different types of ITCs than HS-TFET. It is seen that ZHP-TFET is favorable in terms of DC and RF/analog performances compared to HS-TFET, even in the presence of ITCs. Moreover, a comparative study of various Figure of Merits (FoMs) for ZHP-TFET with existing literature is presented.

Mathematical modelling of endovascular drug delivery: Balloons versus stents

The most common treatment for obstructive coronary artery disease (CAD) is the implantation of a permanent drug-eluting stent (DES). Not only has this permanency been associated with delayed healing of the artery, but it also poses challenges when treating subsequent re-narrowing due to in-stent restenosis (ISR). Drug-coated balloons (DCBs) provide a potential solution to each of these issues. While their use has been primarily limited to treating ISR, in recent years, DCBs have emerged as an attractive potential alternative to DESs for the treatment of certain de novo lesions. However, there remain a number of concerns related to the safety and efficacy of these devices. Firstly, unlike DESs, DCBs necessitate a very short drug delivery window, favouring a higher drug loading. Secondly, while the majority of coronary DCBs in Europe are coated with paclitaxel, the potential mortality signal raised with paclitaxel DCBs in peripheral interventions has shifted efforts towards the development of limus-eluting balloons. The purpose of this paper is to provide a computational model that allows drug delivery from DCBs and DESs to be investigated and compared. We present a comprehensive computational framework that employs a 2D-axisymmetric geometry, incorporates two nonlinear phases of drug binding (specific and non-specific) and includes the influence of diffusion and advection, within a multilayer arterial wall. We utilise this framework to (i) simulate drug delivery from different types of balloon platform; (ii) explore the influence of DCB application time; (iii) elucidate the importance on release kinetics of elevated pressure during DCB application; (iv) compare DCB delivery of two different drugs (sirolimus and paclitaxel) and; (v) compare simulations of DESs versus DCBs. Key measures of comparison are related to safety (drug content in tissue, DC) and efficacy (specific binding site saturation, %SBSS) markers. Our results highlight the pros and cons of each device in terms of DC and %SBSS levels achieved and, moreover, indicate the potential for designing a DCB that gives rise to sufficiently similar safety and efficacy indicators as current commercial DESs.

Mixed Ionic–Electronic Conduction and Magnetoelectric Coupling in Li0.5Fe2.5–xCrxO4(x= 1.0, 1.1, 1.3, 1.5, and 1.6) Involving Magnetization Compensation Phenomenon

The correlations between the crystal structural, magnetic, and electrical properties of Li0.5Fe2.5–xCrxO4 (x = 1.0, 1.1, 1.3, 1.5, and 1.6) have been investigated by neutron diffraction, DC magnetization, and impedance spectroscopy. Crystal structural analysis reveals mixed cation (Li, Fe, and Cr) distributions over both tetrahedral and octahedral crystallographic sites and an enhancement of the site disorder with increasing Cr concentration. The magnetization study yields ferrimagnetic ordering for all the compounds below the respective TC (640 K for x = 1.0 to 470 K for x = 1.6), and magnetization compensation at the respective TComp (540 K for x = 1.0 to 290 K for x = 1.6). The comprehensive analyses of the frequency and temperature-dependent impedance data in terms of DC and AC conductivities reveal the presence of mixed ionic and electronic conductions. The ionic conduction in the compounds is anticipated due to the presence of Li+ ions over the tetrahedral and octahedral crystallographic sites, whereas electron migration through a small polaron hopping mechanism is responsible for electronic conductivity. The relative contributions of electronic and ionic conductions are determined by charge transference number analysis. Almost equal fractions of the ionic and electronic conductivities for the composition x = 1.5 over the entire temperature range of 300 to 600 K reveal the character of a nearly ideal mixed conductor. We have shown highly tunable relative contributions of the ionic and electronic conductions with Cr substitution at room temperature. In addition, a strong coupling between magnetic and electric degrees of freedoms has been demonstrated by the changes in the slopes of the temperature-dependent DC and AC conductivities at both the ferrimagnetic ordering temperature TC and at the magnetization compensation temperature TComp. The role of cation distributions over the tetrahedral and octahedral sites on the conduction as well as magnetic properties has been discussed.

An Adaptive Algorithm for Battery Charge Monitoring based on Frequency Domain Analysis

With technological advancement, the automobile industry is undergoing a design evolution. There has been an increase in the use of electrically actuated systems; electronics-based control systems, along with an increase in average power consumption. But such increased incorporation has been one of the main causes of roadside breakdowns. However, through the help of modelling and simulation manufacturers can evaluate vehicle operation; reduce their cost while achieving a competitive advantage in the automotive market. Here an automotive electrical system has been discussed. Its architecture consists of a battery, alternator, starter solenoid, and starter motor. Detailed modelling and simulation based on Simulink have been developed. Here charge level of automobile battery and its effect on the operational characteristics of an automobile has been considered and simulated in a MATLAB Simulink environment. First, a time-domain analysis has been made of the current response recorded from its maximum, minimum value, and slope characteristics. The response characteristics hence obtained are also analysed in the frequency domain through FFT analysis to obtain data characteristics in the frequency domain. A detailed analysis has been done at different levels of battery charge degradation to obtain a continuous data set for different states. The result shows significant changes both in time and frequency domain displaying discrimination in terms of DC and frequency components along with relative harmonics distortions enabling battery charge monitoring from starting transients. This method of response characteristics analysis helps in easier computation and in designing a system that can help with vehicle diagnosis and quality control.

Complete hemispheric exposure vs. superior sagittal sinus sparing craniectomy: incidence of shear-bleeding and shunt-dependency

PurposeDecompressive hemicraniectomy (DC) has been established as a standard therapeutical procedure for raised intracranial pressure. However, the size of the DC remains unspecified. The aim of this study was to analyze size related complications following DC.MethodsBetween 2013 and 2019, 306 patients underwent DC for elevated intracranial pressure at author´s institution. Anteroposterior and craniocaudal DC size was measured according to the postoperative CT scans. Patients were divided into two groups with (1) exposed superior sagittal sinus (SE) and (2) without superior sagittal sinus exposure (SC). DC related complications e.g. shear-bleeding at the margins of craniectomy and secondary hydrocephalus were evaluated and compared.ResultsCraniectomy size according to anteroposterior diameter and surface was larger in the SE group; 14.1 ± 1 cm vs. 13.7 ± 1.2 cm, p = 0.003, resp. 222.5 ± 40 cm2 vs. 182.7 ± 36.9 cm2, p < 0.0001. The SE group had significantly lower rates of shear-bleeding: 20/176 patients; (11%), compared to patients of the SC group; 36/130 patients (27%), p = 0.0003, OR 2.9, 95% CI 1.6–5.5.There was no significant difference in the incidence of shunt-dependent hydrocephalus; 19/130 patients (14.6%) vs. 24/176 patients (13.6%), p = 0.9.ConclusionsComplete hemispheric exposure in terms of DC with SE was associated with significantly lower levels of iatrogenic shear-bleedings compared to a SC-surgical regime. Although we did not find significant outcome difference, our findings suggest aggressive craniectomy regimes including SE to constitute the surgical treatment strategy of choice for malignant intracranial pressure.

Design and Performance Assessment of Dielectrically Modulated Nanotube TFET Biosensor

The manuscript proposes a novel charge plasma-based junctionless silicon dual cavity nanotube tunnel field-effect transistor (DC-NT-TFET) based biosensor for the detection of neutral and charged biomolecules. For improved sensing ability, the nanogap cavity is introduced in the inner as well as the outer portion of the NT-TFET. Also, the vertical orientation of the device enhances the even distribution of the biomolecules within the cavity area. The inner cavity provides more space for immobilization of the biomolecules and utilizes the advantages of material solubility. In this manuscript sensitivity of the proposed biosensor is Investigated for four neutral biomolecules of dielectric constant, streptavidin (k =.1), biotin (k = 2.63), 3-aminopropyl-triethoxysilane (APTES) (k = 3.57), and protein (k = 8). Also, charged biomolecule, deoxyribonucleic acid (DNA) with a specific dielectric constant of k = 6 is examined for different positive as well as negative charge density. The sensing capability of the device is analyzed in terms of various DC and RF performance parameters. Also, outer cavity length optimization and on various biomolecules are analyzed in the manuscript.

A New Cabled Stabilizer for the Nb3Sn React&amp;Wind DEMO Conductor Prototype

A Nb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> Sn based, React&Wind flat cable, named RW2, was developed in the past three years at the Swiss Plasma Center in the scope of the EUROfusion conceptual studies for DEMO. The test results presented earlier proved an excellent DC performance, but large eddy currents loss in the segregated copper. Here we present the results of a prototype conductor assembled in late 2019 from an older section of RW2 cable and a novel stabilizer, made by two Rutherford cables of thick, high RRR copper wires extruded with a cladding of high resistivity CuNi alloy. The results of the test in SULTAN of the new prototype are discussed in terms of DC and AC loss performance. The AC loss is measured in both orientations, for sinusoidal and trapezoidal field pulses. The test is carried out at both 4.5 K and 20 K operating temperature, allowing separating the contribution of the eddy currents in the segregated copper from the other sources of ac loss, hysteresis and coupling loss. The goal of reducing the eddy currents to a level comparable to the coupling current loss is achieved with the cabled stabilizer, which is now retained as baseline for the React&Wind DEMO conductor.

Temperature dependence of analogue/RF performance, linearity and harmonic distortion for dual‐material gate‐oxide‐stack double‐gate TFET

This article presents an investigation report of the effects of temperature variation in the range of 300 to 480 K on electrical performance parameters of conventional dual-material double-gate tunnel field effect transistor (DMDG-TFET) and dual-material gate-oxide-stack double-gate tunnel field effect transistor (DMGOSDG-TFET). This report shows an analysis and comparison of the impacts of operating temperature variation on both the devices in terms of DC, analogue/RF, linearity and harmonic distortion parameters with the help of simulation results obtained using a numerical device simulator. It could be stated that DMGOSDG-TFET is more insensitive with respect to temperature variation in terms of DC, analogue/RF and linearity performances as compared to conventional DMDG-TFET. Moreover, in terms of harmonic distortion characteristics DMGOSDG-TFET is found to be more stable with temperature variation as compared to DMDG-TFET.

Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor

To overcome the fabrication complexity and achieve a better switching ratio is a major grave concern for applications in semiconductor devices. In this regards, a novel stack gate-oxide junctionless double-gate tunnel field effect transistor with low work-function livestrip (LWLS-SGO-JL-TFET) has been investigated in this manuscript. This structure serves as an alternative solution to improve the performance of device. For this, device structure has comprised of two isolated gates such as polarity gate and control gate with the platinum (work-function = 5.93 eV) and hafnium (work-function = 4.3 eV) respectively, over the N+-type doped silicon substrate for the formation of Tunnel Field Effect Transistor as a like doped conventional TFETs (Tunnel Field Effect Transistors) to overcome fabrication complexity. Since ON state current plays important role in switching ratio and subthreshold swing. Therefore, a dual layer oxide (stack) has introduced in junctionless TFETs to get further improvement in ON state current due to the better capacitive coupling between gate and substrate. Under this condition, the performance improvement is still required of dual oxide juntionless TFETs. Hence, a live strip has inserted at the source side in dual oxide layer to improve the ON state current which helps in gain of device and design of analogue and RF circuits. Moreover, we have also examined the impact of low work-function of live strip on dual oxide Junctionless TFETs in terms of DC, analog/RF and linearity figures of merit (FOMs) of the device. All simulation have been carried out using the technology computer aided design (TCAD) tool. This study shows that proposed device is an appropriate for ultra low power high frequency applications.