Termination Scheme Research Articles

Enhanced belief propagation decoding of polar codes by adapting the parity-check matrix

Though the performance of belief propagation (BP) decoder for polar codes is comparable with the successive cancellation (SC) decoder, it has significant performance gap when compared with the improved SC decoders, such as SC list (SCL) decoding. In this paper, we propose an improved BP decoding for polar codes with good performance by adapting their parity-check matrices. The decoding process is iterative and consists of two parts. Firstly, the parity-check matrix of polar codes is adjusted such that one of its submatrices corresponding to less reliable bits is in a sparse nature. Secondly, the BP decoding is applied to the adjusted parity-check matrix. Simulation results show that the proposed decoder, when accompanied with the early termination scheme, provides significant performance gains over the original polar BP decoder under a relatively low decoding complexity and even competes with the cyclic redundancy check (CRC)-aided SCL (CRC-SCL) decoder only by increasing a tolerate complexity.

Robust Trench Buried-Guard-Ring-Based Termination for Charge Balanced Devices

A major limitation on the performance of high-voltage power semiconductor is the edge termination of the device. It is critical to maintain the breakdown voltage of the device without compromising the reliability of the device by controlling the surface electric field. A good termination structure is critical to the reliability of the power semiconductor device. The proposed termination uses a novel trench MOS with buried guard ring structure to completely eliminate high surface electric field in the silicon region of the termination. The proposed termination scheme was applied toward a 1350-V fast recovery diode and showed excellent results. It achieved 98% of parallel plane breakdown voltage, with low leakage and no shifts after high-temperature reverse bias testing due to mobile ion contamination from packaging mold compound.

Early search termination for fast motion estimation

This paper proposes a novel method for early termination of a motion search. It first introduces an estimator of the sum of absolute difference (SAD) between the current block and a search point. After analyzing the SAD estimator, it proposes the SAD condition to decide whether the current search point is around a minimum point or not. The counter condition is used to evaluate the current search point as an early search termination cue. After the current search point is considered as a minimum point, the search is stopped immediately. The proposed algorithm can easily be combined with most existing fast motion estimation algorithms to further reduce computational cost. While previous thresholding techniques have focused on the correlation of SAD values between a current block and its neighboring blocks, the proposed algorithm studies its own characteristics to predict the threshold. Hence, the proposed termination scheme can complement the previous early search termination techniques by merging the termination methods together, in order to further reduce computational cost. Experimental results demonstrate that the proposed algorithm successfully reduces the computational cost by combining the previous early search termination techniques.

Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems

The reliability of NAND Flash memory deteriorates due to multi-level cell technique and advanced manufacturing technology. To deal with more errors, LDPC codes show superior performance to conventional BCH codes as ECC of NAND Flash memory systems. However, LDPC codec for NAND Flash memory systems faces problems of high redesign effort, high on-chip memory cost and high-throughput demand. This paper presents a byte-reconfigurable cost-effective high-throughput QC-LDPC codec design for NAND Flash memory systems. Reconfigurable codec design is proposed to support various QC-LDPC codes for different Flash memories. To save on-chip memory cost, shared-memory architecture and rescheduling architecture are presented for encoder and decoder, respectively. The shared-memory architecture can save 23% area cost of the encoder and the rescheduling architecture reduces 15% area cost of decoder. In addition, the proposed sub-iteration based early termination (SIB-ET) scheme reduces 29.6% decoding iteration counts compare with the state-of-the-art early termination scheme when raw BER of Flash memory is $3\times 10^{-3}$ . Finally, the QC-LDPC codec for NAND Flash memory systems is implemented in TSMC 90 nm technology. The post-layout result shows that the core size is only 6.72 ${\rm mm}^{2}$ at 222 MHz operating frequency.

Spin Polarization Inversion at Benzene-Absorbed Fe4N Surface.

We report a first-principle study on electronic structure and simulation of the spin-polarized scanning tunneling microscopy graphic of a benzene/Fe4N interface. Fe4N is a compound ferromagnet suitable for many spintronic applications. We found that, depending on the particular termination schemes and interface configurations, the spin polarization on the benzene surface shows a rich variety of properties ranging from cosine-type oscillation to polarization inversion. Spin-polarization inversion above benzene is resulting from the hybridizations between C pz and the out-of-plane d orbitals of Fe atom.

Stopping criteria for MAPLS-AW, a hybrid multi-objective evolutionary algorithm

Evolutionary algorithms are widely used to solve multi-objective optimization problems effectively by performing global search over the solution space to find better solutions. Hybrid evolutionary algorithms have been introduced to enhance the quality of solutions obtained. One such hybrid algorithm is memetic algorithm with preferential local search using adaptive weights (MAPLS-AW) (Bhuvana and Aravindan in Soft Comput, doi:10.1007/s00500-015-1593-9, 2015). MAPLS-AW, a variant of NSGA-II algorithm, recognizes the elite solutions of the population and preferences are given to them for local search during the evolution. This paper proposes a termination scheme derived from the features of MAPLS-AW. The objective of the proposed scheme is to detect convergence of population without compromising quality of solutions generated by MAPLS-AW. The proposed termination scheme consists of five stopping measures, among which two are newly proposed in this paper to predict the convergence of the population. Experimental study has been carried out to analyze the performance of the proposed termination scheme and to compare with existing termination schemes. Several constrained and unconstrained multi-objective benchmark test problems are used for this comparison. Additionally, a real-time application economic emission and load dispatch has also been used to check the performance of the proposed scheme. The results show that the proposed scheme identifies convergence of population much earlier than the existing stopping schemes without compromising the quality of solutions.

Fast HEVC Encoding Decisions Using Data Mining

The High Efficiency Video Coding standard provides improved compression ratio in comparison with its predecessors at the cost of large increases in the encoding computational complexity. An important share of this increase is due to the new flexible partitioning structures, namely the coding trees, the prediction units, and the residual quadtrees, with the best configurations decided through an exhaustive rate-distortion optimization (RDO) process. In this paper, we propose a set of procedures for deciding whether the partition structure optimization algorithm should be terminated early or run to the end of an exhaustive search for the best configuration. The proposed schemes are based on decision trees obtained through data mining techniques. By extracting intermediate data, such as encoding variables from a training set of video sequences, three sets of decision trees are built and implemented to avoid running the RDO algorithm to its full extent. When separately implemented, these schemes achieve average computational complexity reductions (CCRs) of up to 50% at a negligible cost of 0.56% in terms of Bjontegaard Delta (BD) rate increase. When the schemes are jointly implemented, an average CCR of up to 65% is achieved, with a small BD-rate increase of 1.36%. Extensive experiments and comparisons with similar works demonstrate that the proposed early termination schemes achieve the best rate-distortion-complexity tradeoffs among all the compared works.

A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder

In this paper, a power- and area-efficient, multirate, Quasi-cyclic, low-density, parity-check decoder is proposed. The proposed decoder design is based on a simplified adaptive normalized min-sum algorithm. The proposed algorithm effectively utilizes two correction factors for check-node and variable-node update processes. This corrects the channel errors at relatively low signal-to-noise ratio. In order to reduce the finite word length effects, a six-bit nonuniform quantization with the overlapped message passing scheme is used. In addition, an improved early termination scheme is also used to reduce the total number of decoding iterations. This reduces the overall power consumption of the decoder. The simulations have been carried out using Xilinx ISE 14.1 and implemented on Virtex 5 FPGA. The proposed decoder is synthesized using CADENCE with UMC 130 nm technology. With a core area of 1.16 mm$$^{2}$$2, the proposed decoder achieves a maximum throughput of 3.4 Gb/s for 15 decoding iterations with a power dissipation of 114.3 mW.

A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications

This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz , achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.

Formulation of Joint Iterative Decoding for Raptor Codes

Raptor codes are a class of rateless codes originally designed for binary erasure channels. This paper presents a compact set of mathematical expressions for iterative soft decoding of raptor codes. In addition, an early termination scheme is employed, and it is embedded in a single algorithm with the formula. In the proposed algorithm, the performance is enhanced by adopting iterative decoding, both in each inner and outer code and in the concatenated code itself between the inner and outer codes. At the same time, the complexity is reduced by applying an efficient early termination scheme. Simulation results show that our proposed method can achieve better performance with reduced decoding complexity compared to the conventional schemes.

An area efficient and high throughput multi-rate quasi-cyclic LDPC decoder for IEEE 802.11n applications

In this paper, an area efficient and high throughput multi-rate quasi-cyclic low-density parity-check (QC-LDPC) decoder for IEEE 802.11n applications is proposed. An overlapped message passing scheme and the non-uniform quantization scheme are incorporated to reduce the overall area and power of the proposed QC-LDPC decoder. In order to enhance the decoding throughput and reduce the size of memories storing soft messages, an improved early termination (ET) scheme and base matrix reordering technique is employed. These techniques significantly reduce the total number of decoding iterations and memory accessing conflicts without mitigating the decoding performance. Equipped with these techniques an area efficient and high throughput multi-rate QC-LDPC decoder is designed, simulated and implemented with Xilinx Virtex6 (XC6VLX760-2FF1760) for an irregular LDPC code of length 1944 and code rates (1/2–5/6) specified in IEEE 802.11n standard. With a maximum clock frequency of 574.136–587.458MHz the proposed QC-LDPC decoder can achieve throughput in the range of 1.27–2.17Gb/s for 10 decoding iterations. Furthermore, by using Cadence RTL compiler with UMC 130nm VLSI technology, the core area of the proposed QC-LDPC decoder is found to be 1.42mm2 with a power dissipation in the range of 101.25–140.42mW at 1.2V supply voltage.

A Fast and Accurate Face Tracking Scheme by using Depth Information in Addition to Texture Information

This paper proposes a face tracking scheme that is a combination of a face detection algorithm and a face tracking algorithm. The proposed face detection algorithm basically uses the Adaboost algorithm, but the amount of search area is dramatically reduced, by using skin color and motion information in the depth map. Also, we propose a face tracking algorithm that uses a template matching method with depth information only. It also includes an early termination scheme, by a spiral search for template matching, which reduces the operation time with small loss in accuracy. It also incorporates an additional simple refinement process to make the loss in accuracy smaller. When the face tracking scheme fails to track the face, it automatically goes back to the face detection scheme, to find a new face to track. The two schemes are experimented with some home-made test sequences, and some in public. The experimental results are compared to show that they outperform the existing methods in accuracy and speed. Also we show some trade-offs between the tracking accuracy and the execution time for broader application.

Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems

Singular value decomposition (SVD) is an optimal method to obtain spatial multiplexing gain in multi-input multi-output (MIMO) channels. However, the high cost of implementation and high decomposing latency of the SVD restricts its usage in current wireless communication applications. In this paper, we present a complete adaptive SVD algorithm and a reconfigurable architecture for high-throughput MIMO-orthogonal frequency division multiplexing systems. There are several proposed architectural design techniques: reconfigurable scheme, division-free adaptive step size scheme, early termination scheme, and data interleaving scheme. The reconfigurable scheme can support all antenna configurations in a MIMO system. The division-free adaptive step size and early termination schemes are used to effectively reduce the decomposing latency and improve hardware utilization. The data interleaving scheme helps to deal with several channel matrices concurrently. Besides, we propose an orthogonal reconstruction scheme to obtain more accurate SVD outputs, and then the system performance will be greatly enhanced. We apply our SVD design to the IEEE 802.11 n applications. This design is implemented and fabricated in UMC 90 nm 1P9M CMOS technology. The maximum operating frequency is measured to be at 101.2 MHz, and the corresponding power dissipation is at 125 mW. The core size is 2.17 mm2 and the die size occupies 4.93 mm2. The chip result shows that the average latency is only 0.33% of the wireless local area network coherence time. Hence, the proposed reconfigurable adaptive SVD engine design is very suitable for high-throughput wireless communication applications.

Translation in Giant Viruses: A Unique Mixture of Bacterial and Eukaryotic Termination Schemes

Mimivirus and Megavirus are the best characterized representatives of an expanding new family of giant viruses infecting Acanthamoeba. Their most distinctive features, megabase-sized genomes carried in particles of size comparable to that of small bacteria, fill the gap between the viral and cellular worlds. These giant viruses are also uniquely equipped with genes coding for central components of the translation apparatus. The presence of those genes, thought to be hallmarks of cellular organisms, revived fundamental interrogations on the evolutionary origin of these viruses and the link they might have with the emergence of eukaryotes. In this work, we focused on the Mimivirus-encoded translation termination factor gene, the detailed primary structure of which was elucidated using computational and experimental approaches. We demonstrated that the translation of this protein proceeds through two internal stop codons via two distinct recoding events: a frameshift and a readthrough, the combined occurrence of which is unique to these viruses. Unexpectedly, the viral gene carries an autoregulatory mechanism exclusively encountered in bacterial termination factors, though the viral sequence is related to the eukaryotic/archaeal class-I release factors. This finding is a hint that the virally-encoded translation functions may not be strictly redundant with the one provided by the host. Lastly, the perplexing occurrence of a bacterial-like regulatory mechanism in a eukaryotic/archaeal homologous gene is yet another oddity brought about by the study of giant viruses.

Content-adaptive thresholding early termination scheme on directional gradient descent searches for fast block motion estimation

An efficient algorithm named modified directional gradient descent searches to enhance the directional gradient descent search (DGDS) algorithm is presented to reduce computations. A modified search pattern with an adaptive threshold for early termination is applied to DGDS to avoid meaningless calculation after the searching point is good enough. A statistical analysis of best motion vector distribution is analyzed to decide the modified search pattern. Then a statistical model based on the characteristics of the block distortion information of the previous coded frame helps the early termination parameters selection, and a trade-off between the video quality and the computational complexity can be obtained. The simulation results show the proposed algorithm provides significant improvement in reducing the motion estimation (ME) by 17.81% of the average search points and 20% of ME time saving compared to the fast DGDS algorithm implemented in H.264/AVC JM 18.2 reference software according to different types of sequences, while maintaining a similar bit rate without losing picture quality.

Low Noise Front End ASIC With Current Mode Active Cooled Termination for the Upgrade of the LHCb Calorimeter

The current mode line terminating input stage of an integrated circuit for the upgrade of the LHCb calorimeter front end electronics is presented. The circuit is based on a current mode input stage followed by two fully differential interleaved channels, namely a switched integrator and a track and hold. The input stage employs a novel electronically cooled input termination scheme to achieve stringent noise requirements. Compared to previous designs, its novelty relies in the use of two current feedback loops to decrease and control the input impedance of a common base stage. Two prototypes in Austriamicrosystems SiGe BiCMOS 0.35 μm technology have been designed and tested. Key measurements have been performed. Reflection coefficient is smaller than 0.5% for the full dynamic range, which is 12 bits. Relative linearity error is below 1%. Output noise is about 1 LSB after applying correlated double sampling.

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency synthesizer. To increase the throughout while hold down the area and power consumption, a method to reduce the number of the pre-skewing registers is proposed. The number is reduced to 29% of a conventional pipeline accumulator. The propagation delay versus bias current of the adder circuit with different size transistors is investigated. We analyze the delay by employing the open circuit time constant method. Compared to the simulation results, the maximum error is less than ±8%. A method to optimum the design of the adder based on the propagation delay is discussed. The clock traces for the 32-bit adder are heavily loaded, as there are 40 registers being connected to them. Moreover, the differential clock traces, which are much longer than the critical length, should be treated as transmission lines. Thus a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals. A multiple π-type termination scheme is proposed to match the transmission line impedance. The 32-bit accumulator was measured to work functionally at 5.3 GHz.

A termination scheme using intended asymmetric spatial filter response for averaging flash A/D converter

Averaging network is adopted to reduce the front-end amplifier's offset in the flash analog-to-digital converter (ADC) commonly at the cost of the boundary threshold error. Such error worsens the integral-nonlinearity and introduces distortion. An averaging termination scheme using intended asymmetric spatial filter response is proposed to overcome this problem. It matches the impulse response window width, W IR, to the active zero-crossing response window width, W ZX at the boundary of network. Analysis and simulation show that by tuning the ratio between termination resistor R T and averaging resistor R 1, the boundary error is reduced as close as to 1%. This method provides sufficient reliability since the resistance matching can be fabricated as high as 1% in modern CMOS technology. Its feasibility for the flash ADC has been validated by a 1GS/s 4-bit flash converter.

Implementation of a High Throughput 3GPP Turbo Decoder on GPU

Turbo code is a computationally intensive channel code that is widely used in current and upcoming wireless standards. General-purpose graphics processor unit (GPGPU) is a programmable commodity processor that achieves high performance computation power by using many simple cores. In this paper, we present a 3GPP LTE compliant Turbo decoder accelerator that takes advantage of the processing power of GPU to offer fast Turbo decoding throughput. Several techniques are used to improve the performance of the decoder. To fully utilize the computational resources on GPU, our decoder can decode multiple codewords simultaneously, divide the workload for a single codeword across multiple cores, and pack multiple codewords to fit the single instruction multiple data (SIMD) instruction width. In addition, we use shared memory judiciously to enable hundreds of concurrent multiple threads while keeping frequently used data local to keep memory access fast. To improve efficiency of the decoder in the high SNR regime, we also present a low complexity early termination scheme based on average extrinsic LLR statistics. Finally, we examine how different workload partitioning choices affect the error correction performance and the decoder throughput.

Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders

Many recent reconfigurable/multi-mode quasi-cyclic low density parity check (QC-LDPC) decoder designs have shown appealing implementation results in the literature. However, most of them are based on datapath multiplexing techniques with ad hoc matrix arrangement. There is still room for further interconnection reduction, throughput enhancement, and a more sophisticated early termination scheme. In this paper, we will focus on these issues and present a two-level design approach, which optimizes the design at (1) matrix merging level, and (2) module design level. First, direct multiplexing datapaths between multiple modes leads to great overhead on wiring complexity. In order to mitigate this problem, we merge multiple parity check matrices by proposing an efficient algorithm at matrix merging level, which helps to minimize multiplexer and wiring overhead. Second, for efficient decoding issues, we propose two design techniques at module design level. One is data wrapping scheme. It enhances the decoding throughput by using the data-wrapped memory with the proposed reconfigurable data-switching circuits (R-DSC) to conquer the data alignment problem and achieve multi-mode reconfigurability. The other is the adaptive early termination (AET) scheme. It can save the unnecessary decoding procedures under both high-SNR and low-SNR regions. Finally, to verify our design approach, we implement a triple-mode LDPC decoder chip which is compatible to IEEE 802.11n standard by using UMC 90 nm CMOS technology. This chip only occupies 3.32 mm2 and features high core utilization up to 70% with low power dissipation of 135.3 mW. The prototyping chip not only validates the proposed approach, but also outperforms the state-of-the-art QC-LDPC decoders for IEEE 802.11n systems.