TCAD process and device simulation has been used to understand and optimize advanced logic devices for many technology nodes. Stress engineering and modeling has also been an important part of device analysis for decades, long before it was intentionally engineered for transistor performance. Initial stress studies were process-only simulations of stress-dependent silicon oxide growth for isolation [1,2,3,4,5] and were extended to include strain from thermal mismatch, intrinsic, and dopant strain [6,7]. Process and device simulations have also been used to explain increased junction leakage [8] and layout dependent reduced electron mobility [9]. The first intentionally engineered strain sources include nitride capping layers and embedded SiGe S/Ds [10,11]. As technology development has progressed, both the unintentional and engineered strain sources have changed considerably. Device scaling modifies the geometry, which in turn changes the stress from generation to generation. In addition, new technology features and architectures can affect both intentional and unintentional strain sources. This paper reviews how strain sources have changed, how modeling has evolved to simulate the effects of strain in advanced logic devices, and the outlook for engineering strain in future device options. To model stressed devices, both front end process models and stress dependent mobility device models have been developed [12,13]. To evaluate stress effects on device performance requires a process simulator for structure creation, stress and dopant diffusion/activation modeling, and a device simulator that accurately captures the resulting electrostatics as well as carrier mobility and external resistance. In this work, process simulation is performed using an internally modified version of FLOOPS [12,14,15,16,21], while drift diffusion simulations are run with MDS [17] which includes models for stress, orientation and ballisticity on transport [13,18,19,20,22]. The first engineered stress in NMOS employed tensile nitride films over the polysilicon gate [10,11,12,13]. At the 45nm node, HiK and metal gates were introduced, removing the nitride induced stress, but allowing for other strain sources including tensile contact metals and compressive gate metals [23]. In addition, the strain due to edge dislocations in lattice improved NMOS device performance [16]. When trigate transistors were introduced at the 22nm node [24], the strains changed again. From the modeling perspective, trigate devices necessitated both routine 3D simulation [21] and capturing transport in [110] confined channels which changes the mobility response to stress [25]. Poor epitaxial regrowth in the trigate architecture removed edge dislocations as a strain source but allowed for stress from tensile gate metals and also a novel ILD0 [26]. Figure 1 shows stress simulations for different NMOS devices. The main engineered strain source for PMOS devices is embedded SiGe S/Ds. Over time, the Ge fraction was increased while the distance from the SiGe S/D to the channel was decreased [10,11,12,13,17]. In the 45 nm technology node [23], removal of the polysilicon gates increased channel compression [17]. The introduction of trigate devices [24] resulted in the need to capture stress effects on transport in [110]/(110) channels, which has a higher hole mobility but less stress response. Initially there was a concern that the strain from epi S/Ds growth would not be maintained in trigate devices,; however, its effectiveness was later confirmed with TEM measurements [27]. Modeling both edge dislocations [16] and Ge profiles in S/D are important for matching measured strain. Figure 2 shows stress profiles for different PMOS devices. Stress from SiGe S/Ds were also found to exhibit layout effects [28]. This requires simulating stress in an area larger than the device to accurately capture the resulting stress in the channel. Capturing unintentional strain sources, which can easily be overlooked, also makes simulating a larger area critical. For example, ILD0 and gate cut fill strain [29], which occur outside the diffusion box, impact device performance. Future logic device options will involve new materials and architectures which impact device responses to stress and present novel opportunities to engineer strain. New channel materials include sSi for NMOS, sSiGe for PMOS [30], and Ge for NMOS and PMOS [31,32]. Process flow concerns will also evolve, i.e. devices engineered with stress from the substrate will have challenges maintaining stress throughout an epi S/D process and the stress will depend on fin length. Future device architectures include nanowire/nanosheets [33], forksheets [34] and device stacking, which will allow mixing and matching both materials and architectures; examples include combining Ge PMOS nanosheets and Si NMOS finfets [35]. A stress simulation of tensile gate metal for the stacking approach in reference [35] is shown in Figure 3 and illustrates how the same strain source results in different stresses depending on architecture. Figure 1
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Nov 30, 2021
Egi Erlangga + 2
Open Access
