Temperature-dependent Leakage Power Research Articles

Comparative Study of Energy Performance between Chip and Inlet Temperature-Aware Workload Allocation in Air-Cooled Data Center

Improving the energy efficiency of data center has become a research focus in recent years. Previous works commonly adopted the inlet temperature constraint to optimize the thermal environment in the data center. However, the inlet temperature-aware method cannot prevent the servers from over-cooling. To cope with this issue, we propose a thermal-aware workload allocation strategy with respect to the chip temperature constraint. In this paper, we conducted a comparative evaluation of the performance between the chip and inlet temperature-aware workload allocation strategies. The workload allocation strategies adopt a POD-based heat recirculation model to characterize the thermal environment in data center. The contribution of the temperature-dependent leakage power to server power consumption is also considered. We adopted a sample data center under constant-flow and variable-flow cooling air supply to evaluate the performance of these two different workload allocation strategies. The comparison results show that the chip temperature-aware workload allocation strategy prevents the servers from over-cooling and significantly improves the energy efficiency of data center, especially for the case of variable-flow cooling air supply.

Chip Temperature-Based Workload Allocation for Holistic Power Minimization in Air-Cooled Data Center

Minimizing the energy consumption is a dominant problem in data center design and operation. To cope with this issue, the common approach is to optimize the data center layout and the workload distribution among servers. Previous works have mainly adopted the temperature at the server inlet as the optimization constraint. However, the inlet temperature does not properly characterize the server’s thermal state. In this paper, a chip temperature-based workload allocation strategy (CTWA-MTP) is proposed to reduce the holistic power consumption in data centers. Our method adopts an abstract heat-flow model to describe the thermal environment in data centers and uses a thermal resistance model to describe the convective heat transfer of the server. The core optimizes the workload allocation with respect to the chip temperature threshold. In addition, the temperature-dependent leakage power of the server has been considered in our model. The proposed method is described as a constrained nonlinear optimization problem to find the optimal solution by a genetic algorithm (GA). We applied the method to a sample data center constructed with computational fluid dynamics (CFD) software. By comparing the simulation results with other different workload allocation strategies, the proposed method prevents the servers from overcooling and achieves a substantial energy saving by optimizing the workload allocation in an air-cooled data center.

Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs

The reliability of multiprocessor system-on-chips (MPSoCs) is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. High chip temperatures might not only cause potential deadline violations, but also increase cooling costs and leakage power. Pro-active thermal-aware allocation and scheduling techniques that avoid thermal emergencies are promising techniques to reduce the peak temperature of an MPSoC. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming, in particular for unknown input patterns and data. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core real-time system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperature-dependent leakage power. Afterwards, we integrate the proposed thermal analysis method into a design-space exploration framework to optimize the task to processing component assignment. Finally, we apply the proposed method in various case studies to explore thermal hot spots and to optimize the task to processing component assignment.

Maximising energy efficiency in 3D multicore systems: a formalised approach

Three-dimensional integrated circuits (3D ICs) present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this article, we analyse for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power. We develop a novel convex optimisation framework to optimise the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation-based experiments with our proposed optimisation framework shows 5–17% improvement in the energy efficiency of a typical multicore system organised as 3D stacked dies.

Energy-Optimal Dynamic Thermal Management: Computation and Cooling Power Co-Optimization

Conventional dynamic thermal management (DTM) assumes that the thermal resistance of a heat-sink is a given constant determined at design time. However, the thermal resistance of a common forced-convection heat sink is inversely proportional to the flow rate of the air or coolant at the expense of the cooling power consumption. The die temperature of the silicon devices strongly affects its leakage power consumption and reliability, and it can be changed by adjusting the thermal resistance of the cooling devices. Different from conventional DTM which aims to avoid the thermal emergency, our proposed DTM regards the thermal resistance of a forced-convection heat sink as a control variable, and minimize the total power consumption both for computation and cooling. We control the cooling power consumption together with the microprocessor clock frequency and supply voltage, and track the energy-optimal die temperature. Consequently, we reduce a significant amount of the temperature-dependent leakage power consumption of the microprocessor while spending a bit higher cooling power than conventional DTM, and eventually consume less total power. Experimental results show the proposed DTM saves up to 8.2% of the total energy compared with a baseline DTM approach. Our proposed DTM also enhances the Failures in Time (FIT) up to 80% in terms of the electromigration lifetime reliability.

Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits

Thermal analysis has long been essential for designing reliable high-performance cost-effective integrated circuits (ICs). Increasing power densities are making this problem more important. Characterizing the thermal profile of an IC quickly enough to allow feedback on the thermal effects of tentative design changes is a daunting problem, and its complexity is increasing. The move to nanometer-scale fabrication processes is increasing the importance of thermal phenomena such as ballistic phonon transport. The accurate thermal analysis of nanometer-scale ICs containing hundreds of millions of devices requires characterization of heat transport across multiple length scales. These scales range from the nanometer scale (device-level impact) to the centimeter scale (cooling package impact). Existing chip-package thermal analysis methods based on classical Fourier heat transfer cannot capture nanometer-scale thermal effects. However, accurate device-level modeling techniques, such as molecular dynamics methods, are far too slow for use in full-chip IC thermal analysis. In this paper, we propose and develop ThermalScope, a multiscale thermal analysis method for nanometer-scale IC design. It unifies microscopic and macroscopic thermal modeling methods, i.e., the Boltzmann transport equation and Fourier modeling methods. Moreover, it supports adaptive multiresolution modeling. Together, these ideas enable the efficient and accurate characterization of nanometer-scale heat transport as well as the chip-package-level heat flow. ThermalScope is designed for full-chip thermal analysis of billion-transistor nanometer-scale IC designs, with accuracy at the scale of individual devices. ThermalScope enables the accurate characterization of various temperature-related effects, such as temperature-dependent leakage power and temperature-timing dependences. ThermalScope has been implemented in software and used for the full-chip thermal analysis and temperature-dependent leakage analysis of an IC design with more than 150 million transistors. ThermalScope will be publicly released for free academic and personal use.