Technology Design Rules Research Articles

POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP

Flip-flops are the fundamental building blocks of the data path structure. It is a key component of digital circuits and systems. This work offers an exclusive master-slave flip-flop topology by ensuing clocked complementary metal oxide semiconductor (C2MOS) logic, minimizing the total device count and the count of clocked devices. Reducing the number of clocked devices reduces undesirable transient activity and reduces dynamic power dissipation. C2MOS logic connects static logic design with clock signal synchronization, resulting in power savings and increased speed. The area reduction is also attained by reducing the total number of devices. The proposed topology has been realized using only sixteen transistors, including six clocked devices, resulting in area compression. Layout-level simulation at 0.12 mm C2MOS design rule technology is used to investigate the performance. According to an investigation, the proposed topology achieves power savings ranging from 19.77 to 63.75 %, area compaction ranging from 22.03 to 66.30 %, power delay product (PDP) enhancement ranging from 18.56 to 53.91 %, energy-delay product (EDP) enhancement ranging from 5.61 % to 41.39 %, power energy product (PEP) enrichment ranging from 35.63 to 82.82 %, and power area product (PAP) enrichment ranging from 35.19 to 66.30 %.

Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.

(Electronics and Photonics Division Award Address) Technological Issues and Design Rules of Electrodes for High-Efficiency GaN-Based Light-Emitting Diodes

Group III-nitride-based LEDs are of great technological importance because of their applications including display, solid-state lighting, automotive headlight, and water/air purification. For these applications, the attainment of high external quantum efficiency (EQE) of LEDs is essential. On the one hand, their applications necessitate the fabrication of different geometry LEDs, such as lateral-type, vertical-type, and flip-chip LEDs, which require different design rules of electrodes and current spreaders. To maximize the EQE, it is important to increase the light extraction efficiency (LEE). In addition, the improvement of current injection (by forming low contact resistivity) and current spreading is vital for the fabrication of high-efficiency LEDs. It is well known that lateral LEDs suffer from the light extraction limit due to the absorption of the metal contacts, such as n and p contacts, and bond pads. In addition, p-GaN has characteristic problems, which make it difficult to achieve device-quality ohmic contacts with the specific contact resistance lower than ~10–4 Ωcm2 because of the difficulty in growing a highly doped p-GaN and the absence of appropriate metals or conducting oxides having work function larger than that of p-GaN. Thus, for the formation of ohmic and reflective contacts to p-GaN, also serving as light extractor and/or current spreader, transparent conducting oxides (TCOs)-based and Ag-based schemes have been extensively investigated. In this talk, we present methods of enhancing current injection efficiency through the formation of transparent and reflective ohmic electrodes. Design rules are suggested to enhance current injection efficiency, such as the control of surface Fermi-level through surface treatment, barrier tunneling by forming interfaces with inhomogeneous Schottky barriers, the modification of Schottky barrier heights (SBHs), control of native defects in GaN surface regions. Furthermore, nanostructures, such as Ag nano-dots (NDs) and Ag nano-wires (NWs), are used to enhance the light output powers of GaN-based LEDs. Finally, on the basis of scanning transmission electron microscopy, X-ray photoemission spectroscopy, secondary ion mass spectroscopy and Auger electron spectroscopy results, possible ohmic formation and electrical degradation mechanisms are described and discussed.

Technological limitations in readout integrated circuits for infrared focal plane arrays based on quantum-well infrared photodetectors

This paper presents the physical and technical principles of readout integrated circuit (ROIC) for reading and preprocessing focal plane array signals in the infrared spectral range 8–14 μm. The noise equivalent temperature difference of long-wavelength infrared focal plane arrays based on ROIC with frame integration of signals of multilayer quantum well structures is evaluated. The influence of technological limitations in silicon readout circuits for photo signals on the performance of IR focal plane arrays is analyze for a wide range of parameters of QWIP -based focal plane arrays and CMOS technology design rules.

Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion

In this brief, we have developed a charge-based model for the symmetric double-gate junctionless (JL) field effect transistor (FET) that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of JL FETs beyond the domain of operation for which they have been designed. In addition, to its interest for providing technology design rules, the new model is able to explain the unexpected increase in the gate capacitance when biasing the device in deep depletion as well as the theoretical limit for the OFF-current in deep depletion.

Analog layout retargeting using geometric programming

To satisfy the requirements of complex and special analog layout constraints, a new analog layout retargeting method is presented in this article. Our approach uses geometric programming (GP) to achieve new technology design rules, implement device symmetry and matching constraints, and manage parasitics optimization. The GP, a class of nonlinear optimization problem, can be transferred or fitted into a convex optimization problem. Therefore, a global optimum solution can be achieved. Moreover, the GP can address problems with large-scale variables and constraints without setting an initialization variable range. To meet the prerequisites of the GP methodology for analog layout automation, we propose three kinds of mathematical transformations, including negative coefficient transformation, fraction transformation, and maximum of posynomial transformation. The efficiency and effectiveness of the proposed algorithm, as compared with the other existing methods, are demonstrated by a basic case-study example: a two-stage Miller-compensated operational amplifier and a single-ended folded cascode operational amplifier.

Design of an adaptive LNA for hand‐held devices in a 1‐V 90‐nm standard RF CMOS technology: From circuit analysis to layout

This paper deals the design of a reconfigurable Low‐Noise Amplifier (LNA) for the next generation of wireless hand‐held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand‐work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two‐stage topology including inductive‐source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b‐g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF<1.77dB, S21>16dB, S11<-5.5dB, S22<-5.5 dB and IIP3>-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1‐V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low- k materials ( k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.

IPRAIL—intellectual property reuse-based analog IC layout automation

This paper presents a computer-aided design tool, IPRAIL, which automatically retargets existing analog layouts for technology migration and new design specifications. The reuse-based methodology adopted in IPRAIL utilizes expert designer knowledge embedded in analog layouts. IPRAIL automatically extracts analog layout intellectual properties as templates, incorporates new technology design rules and device sizes, and generates fully functional layouts. This is illustrated by retargeting two practical operational amplifier layouts from the TSMC 0.25 μm CMOS process to the TSMC 0.18 μm CMOS process. While manual re-design is known to take days to weeks, IPRAIL only takes minutes and achieves comparable circuit performances.

Achievements and perspectives of the advice project

Present IC complexity and the evolution of the technological design rules have enhanced the request of new techniques to evaluate the real behaviour of VLSI circuits. E-beam based techniques have shown to be a winning approach to analyse the internal electrical and logical status of the circuit. The Scanning Electron beam Microscope can be really indispensable in IC debugging procedures if it is deeply integrated with the design environment. The ESPRIT Project 271 ADVICE 1 aimed to automate the electron beam tester, creating a link toward the design data. The foreground of the project is going to be a commercial product. Furthermore the basis for new developments have been established.

A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.

PSI: A symbolic layout system

A symbolic layout tool, PSI, is described for use with IBM circuit technology. Significant features of PSI are used with multiple circuit technologies, adaptation to rapid changes of technology design rules, creation of nested designs, and extensive designer control over the spacing process.

Reactive ion etching of polysilicon and tantalum silicide : W. Beinvogl and B. Hasler. Solid St. Technol., 125 (April 1983)

This chapter discusses the technological advantages of high-electron-mobility transistor (HEMT). It describes an HEMT technology for very-large-scale integration (VLSIs) including material, device fabrication, and characteristics for device modeling. Current work and recent advances in HEMT logic and memory integrated circuits (ICs) are reviewed. The future performance of HEMT VLSIs for ultrahigh- speed computer applications is projected. HEMTs are very promising devices for VLSIs, especially operating at liquid nitrogen temperatures, because of their ultra-high speed and low power dissipation. The projected HEMT performance target suitable for VLSIs is a fundamental switching delay below 10 ps with a power dissipation of about 100 μW per stage under 1 μm design rule technology. By evaluating the gate length dependence of threshold voltage and K factor of short-channel HEMTs, short-channel effects were found not to be a problem in microstructures of submicrometer dimensions. Master - slave flip-flop divide - by- two circuits achieved internal logic delays of 22 ps/gate at 77 K and 36 psfgate at 300 K, at an average fan-out of about 2. HEMT technology has been shown to have desirable features for high-performance VLSI devices. A HEMT 1 kbit static RAM has been developed and has achieved an address access time of 0.87 ns to demonstrate the feasibility of high-performance VLSIs. Using the same technology, a HEMT 4 Kb sRAM has also been successfully fabricated and normal read/write operation confirmed.

Electrical surface properties of semi-insulating and ion implanted GaAs revealed by thermo-optical acousto-electric voltage method : K. Varahramyan and P. Das. Solid-St. Electron.25 (6), 517 (1982)

This chapter discusses the technological advantages of high-electron-mobility transistor (HEMT). It describes an HEMT technology for very-large-scale integration (VLSIs) including material, device fabrication, and characteristics for device modeling. Current work and recent advances in HEMT logic and memory integrated circuits (ICs) are reviewed. The future performance of HEMT VLSIs for ultrahigh- speed computer applications is projected. HEMTs are very promising devices for VLSIs, especially operating at liquid nitrogen temperatures, because of their ultra-high speed and low power dissipation. The projected HEMT performance target suitable for VLSIs is a fundamental switching delay below 10 ps with a power dissipation of about 100 μW per stage under 1 μm design rule technology. By evaluating the gate length dependence of threshold voltage and K factor of short-channel HEMTs, short-channel effects were found not to be a problem in microstructures of submicrometer dimensions. Master - slave flip-flop divide - by- two circuits achieved internal logic delays of 22 ps/gate at 77 K and 36 psfgate at 300 K, at an average fan-out of about 2. HEMT technology has been shown to have desirable features for high-performance VLSI devices. A HEMT 1 kbit static RAM has been developed and has achieved an address access time of 0.87 ns to demonstrate the feasibility of high-performance VLSIs. Using the same technology, a HEMT 4 Kb sRAM has also been successfully fabricated and normal read/write operation confirmed.