System-level Co-simulation Research Articles

System-level co-simulation for embedded systems

The technological revolution affects the growth of systems in terms of functionality and complexity. Industries of embedded systems become increasingly an area of interest for researchers to develop Computer-Aided Design (CAD) environments to support at the same time the complexity in terms of different components and functionalities in terms of application programming interface and libraries. Mainly, CAD tools based on multi-level co-simulation are challenged by the time-to-market constraint. As known, the behavior description at a higher level provides a speedy simulation, but it suffers from bad accuracy. Therefore, describing a customized model for a system behavior with sufficient functional details at an earlier stage of modeling is a great challenge to researchers. As an attempt to overcome the last challenge, this paper presents a co-simulation model based on a synchronization methodology to ensure the verification between the conceptual level and the functional level. The proposed system-level co-simulation model is implemented to interfaces to provide the switch context in the case of the Arena and the Simulink/Matlab environments. The evaluation was performed by using two case studies with different domains to prove the effectiveness of the proposed system-level co-simulation interfaces.

Uncooled microbolometer system-level co-simulation using finite element analysis method and intellectual property core

The purpose of system-level simulation is to find out a coordinated simulation method between the design of microbolometer and read-out integrated circuit (ROIC). Thermal capacity, thermal conductivity and resistance values of the model are obtained by finite element analysis (FEA). A equipment circuit of microbolometer which containing the parameters mentioned above is established. Then this equipment circuit is described by verilog-analog and mixed-eignal (AMS) language which is the reduced-order macro-model of microbolometer. This macro-model is compiled and defined as intellectual property (IP) core in cadence. System-level collaborative simulation between the IP core of microbolometer and ROIC was conducted, which established a direct link between the design of microbolometer and ROIC in the same design platform. The result of simulation is in agreement with experimental data. It can offer a fast and efficient ways of infrared focal plane array (IRFPA) design and fabrication, and reduce cost and shorten the development cycle for IRFPA industry.

Research on Responsivity of Microbolometer in Food Temperature Prediction by System-level Collaborative Simulation Method

In this study, an 320×240 are fabricated according to the design to verify the system-level co-simulation results. Due to the complexity of microbolometer in food temperature prediction heat-transfer structure, thermoelectric characteristics could’t be simulated in the same design platform with the design of its Read-Out Integrated Circuit (ROIC) which is monolithically integrated with the heat-transfer structure. The purpose of coordinated simulation is to find out a coordinated analysis method between microbolometer in food temperature prediction and its Read-Out Integrated Circuit (ROIC). Input and output characteristics of microbolometer in food temperature prediction was obtained. Responsivity of the heat-transfer model is analyzed based on the results of system-level collaborative simulation. Test values of responsivity matched the known design results of simulation well.

Performance and Power Modeling of On-Chip Bus System for a Complex SoC

This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an on-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool.

Heterogeneous system level co-simulation for the design of telecommunication systems

The advanced complexity and heterogeneity of modern telecommunication systems mostly lead to the incorporation of heterogeneous implementation technologies and design styles. Consequently, the design representation of such systems often requires the mixed use of distinct model of computations at different abstraction layers. Therefore, heterogeneous co-simulation is needed in order to enable the effective communication and interaction among the involved models of computation. This paper resolves this issue by proposing the heterogeneous co-modelling of telecom systems based on the combination of SDL semantics with C language running on an instruction set simulator, coupling in that way the specification and the first refinement steps of the co-design flow. The missing test link between the corresponding tools that support the SDL-C co-model is addressed by proposing a heterogeneous co-simulation scheme through the development of a mediator. Finally, the proposed methodology and the efficiency of the built environment are evaluated through a case study associated with the design of the MAC layer of the DECT telecom system.1,2

System-level modeling and simulation of the 10G optoelectronic interconnect

Mixed-signal multidomain systems present a challenge for computer-aided design tools. Optical and electronic simulation tools are available as separate entities. However, to date, successful system-level cosimulation has not been implemented, leading to expensive refabrication. We present a unique system-level simulation tool for mixed electrooptical systems. We apply our tool Chatoyant to the simulation of an optical high-speed free-space interconnect system designed for 10-GHz speeds. The 10G free-space optical interconnect module has optical, optoelectronic, and microwave components and thus is an ideal vehicle to use as a test system. We demonstrate how Chatoyant, a mixed-signal multidomain simulator, has been used to evaluate end-to-end performance of this complex system, including the exploration of design tradeoffs and mechanical tolerancing.

Scalable techniques for system-level cosimulation and coestimation

A system-level design approach that enforces a separation between system behaviour and architecture is presented. The system designer focuses first on system behaviour, then looks for a suitable architecture to implement it, and finally verifies the performance. Techniques and tools are described to accurately evaluate the performance of a system at different levels of abstraction. The evaluation must be done dynamically, in a simulation framework, to capture runtime interaction among tasks and with the environment model. Moreover, it should be fast enough to enable the exploration of several algorithmic and architectural solutions in the search for the best implementation. Tunable models, where the designer can trade accuracy for speed, are essential for this purpose.