Symmetric Multiprocessor Systems Research Articles

Analysis and measurement of the effect of kernel locks in SMP systems

AbstractThis article reports the use of case studies to evaluate the performance degradation caused by the kernel‐level lock. We define the lock ratio as a ratio of the execution time for critical sections to the total execution time of a parallel program. The kernel‐level lock ratio determines how effective programs work on symmetric multiprocessor (SMP) systems. We have measured the lock ratios and the performance of three types of parallel programs on SMP systems with Linux 2.0: matrix multiplication, parallel make, and WWW server programs. Experimental results show that the higher the lock ratio of parallel programs, the worse their performance becomes. Copyright © 2001 John Wiley & Sons, Ltd.

Cacheminer: A runtime approach to exploit cache locality on SMP

Exploiting cache locality of parallel programs at runtime is a complementary approach to a compiler optimization. This is particularly important for those applications with dynamic memory access patterns. We propose a memory-layout oriented technique to exploit cache locality of parallel loops at runtime on Symmetric Multiprocessor (SMP) systems. Guided by application-dependent and targeted architecture-dependent hints, our system, called Cacheminer, reorganizes and partitions a parallel loop using the memory-access space of its execution. Through effective runtime transformations, our system maximizes the data reuse in each partitioned data region assigned in a cache, and minimizes the data sharing among the partitioned data regions assigned to all caches. The executions of tasks in the partitions are scheduled in an adaptive and locality-presented way to minimize the execution time of programs by trading off load balance and locality. We have implemented the Cacheminer runtime library on two commercial SMP servers and an SimCS simulated SMP. Our simulation and measurement results show that our runtime approach can achieve comparable performance with the compiler optimizations for programs with regular computation and memory-access patterns, whose load balance and cache locality can be well optimized by the tiling and other program transformations. However, our experimental results show that our approach is able to significantly improve the memory performance for the applications with irregular computation and dynamic memory access patterns. These types of programs are usually hard to optimize by static compiler optimizations.

MPI parallel implementation of CBF preconditioning for 3D elasticity problems

The numerical solution of 3D linear elasticity equations is considered. The problem is described by a coupled system of second-order elliptic partial differential equations. This system is discretized by trilinear brick finite elements. The PCG iterative method is used for solving the large-scale linear algebraic systems arising after the FEM discretization of the problem. Displacement decomposition technique is applied at the first step to construct a preconditioner using the decoupled block-diagonal part of the original matrix. Then circulant block-factorization is used for preconditioning of the obtained block-diagonal matrix. New construction of a parallel algorithm for the discussed preconditioning method is proposed. The theoretical part of this study includes analysis of the execution time on various parallel architectures and asymptotic estimates of the parallel speedup and the parallel efficiency. The parallel performance estimates indicate that the proposed algorithm will be especially efficient on coarse-grain parallel systems, which is also confirmed by the numerical experiments. A portable MPI parallel code is developed. Numerical tests on three symmetric multiprocessor systems: SUN Enterprise 3000, SUN SPARCstation 10 and Origin 2000 are presented. The reported speedup and parallel efficiency illustrate well the features of the proposed method and its implementation.

COMPaS: a PC-based SMP cluster

Symmetric multiprocessor systems have become widely available, both as computational servers and as platforms for high-performance parallel computing. The same trend is found in PCs-some have also become SMPs with many CPUs in one box. Clusters of PC based SMPs are expected to be compact, cost-effective parallel-computing platforms. At the Real World Computing Partnership, we have built a PC-based SMP cluster, COMPaS (Cluster of MultiProcessor Systems), as the next-generation cluster-computing platform. Our objective is to study the performance characteristics of a PC-based SMP cluster and the programming models and methods for an SMP cluster. There have been many other research efforts in cluster computing, including the Illinois High Performance Virtual Machines project, the Berkeley NOW project, and Jazznet. However, few researchers have studied a homogeneous, medium-scale PC-based SMP cluster like COMPaS.

A Comparison of Implicitly Parallel Multithreaded and Data-Parallel Implementations of an Ocean Model

Two parallel implementations of a state-of-the-art ocean model are described and analyzed: one is written in the implicitly parallel language Id for the Monsoon multithreaded dataflow architecture, and the other in data-parallel CM Fortran for the CM-5. The multithreaded programming model is inherently more expressive than the data-parallel model but is not especially adapted to regular data structures common to many scientific codes. One goal of this study is to understand what, if any, are the performance penalties of multithreaded execution when implementing a program that is well suited for data-parallel execution. To avoid technology and machine configuration issues, the two implementations are compared in terms of overhead cycles perrequiredfloating point operation. When flows in complex geometries typical of ocean basins are simulated, the data-parallel model only remains efficient if redundant computations are performed over land. The generality of the Id programming model, however, allows one to easily and transparently implement a parallel code that computes only in the ocean. When ocean basins with complex and irregular geometry are simulated the normalized performance on Monsoon is comparable with that of the CM-5. For more regular geometries that map well to the computational domain, the data-parallel approach proves to be a better match. We conclude by examining the extent to which clusters of mainstream symmetric multiprocessor (SMP) systems offer a scientific computing environment which can capitalize on and combine the strengths of the two paradigms.

Rationale and Strategy for a 21st Century Scientific Computing Architecture: The Case for using Commercial Symmetric Multiprocessors as Supercomputers

Rationale and Strategy for a 21st Century Scientific Computing Architecture: The Case for using Commercial Symmetric Multiprocessors as Supercomputers

Post-pass partitioning of signal processing programs

Symmetric multiprocessor systems are increasingly common, not only as high-throughput servers, but as a vehicle for executing a single application in parallel in order to reduce its execution latency. This article presents Pedigree, a compilation tool that employs a new partitioning heuristic based on the program dependence graph (PDG). Pedigree creates overlapping, potentially interdependent threads, each executing on a subset of the SMP processors that matches the thread’s available parallelism. A unified framework is used to build threads from procedures, loop nests, loop iterations, and smaller constructs. Pedigree does not require any parallel language support; it is post-compilation tool that reads in object code. The SDIO Signal and Data Processing Benchmark Suite has been selected as an example of real-time, latency-sensitive code. Its coarse-grained data flow parallelism is naturally exploited by Pedigree to achieve speedups of 1.63×/2.13× (mean/max) and 1.71×/2.41× on two and four processors, respectively. There is roughly a 20% improvement over existing techniques that exploit only data parallelism. By exploiting the unidirectional flow of data for coarse-grained pipelining, the synchronization overhead is typically limited to less than 6% for synchronization latency of 100 cycles, and less than 2% for 10 cycles.

Database buffer size investigation for OLTP workloads

It is generally accepted that On-Line Transaction Processing (OLTP) systems benefit from large database memory buffers. As enterprise database systems become larger and more complex, hardware vendors are building increasingly large systems capable of supporting huge memory configurations. Database vendors in turn are developing buffer schemes to exploit this physical memory. How much will these developments benefit OLTP workloads? Through empirical studies on databases sized comparably to those seen in the real-world, this paper presents the characteristics of an industry-standard OLTP benchmark as memory buffer size changes. We design the experiments to investigate how the database size, the buffer size and the number of CPUs impact performance, in particular the throughput and the buffer hit rate on Symmetric Multiprocessor Systems. The relationships of these major database attributes are plotted and key observations are summarized. We discuss how these relationships change as the number of CPUs changes. We further quantify the relationships: 1) between database buffer data hit rate, buffer size and database size, 2) between throughput, buffer data hit rate and database size and 3) between throughput and number of CPUs. Algorithms, rules-of-thumb and examples are presented for predicting performance, sizing memory and making trade-offs between adding more memory and increasing the number of CPUs.

Performance analysis using very large memory on the 64-bit AlphaServer system

Optimization techniques have been used to deploy very large memory (VLM) database technology on Digital’s AlphaServer 8400 multiprocessor system. VLM improves the use of hardware and software caches, main memory, the I/O subsystems, and the Alpha 21164 microprocessor itself, which in turn causes fewer processor stalls and provides faster locking. Digital’s 64-bit AlphaServer 8400 system running database software from a leading vendor has achieved the highest TPC-C results to date, an increased throughput due to increased database cache size, and an improved scaling with symmetric multiprocessing systems.

An overview of DB2 parallel edition

In this paper, we describe the architecture and features of DB2 Parallel Edition (PE). DB2 PE belongs to the IBM family of open DB2 client/server database products including DB2/6000, DB2/2, DB2 for HP-UX, and DB2 for the Solaris Operating Environment. DB2 PE employs a shared nothing architecture in which the database system consists of a set of independent logical database nodes. Each logical node represents a collection of system resources including, processes, main memory, disk storage, and communications, managed by an independent database manager. The logical nodes use message passing to exchange data with each other. Tables are partitioned across nodes using a hash partitioning strategy. The cost-based parallel query optimizer takes table partitioning information into account when generating parallel plans for execution by the runtime system. A DB2 PE system can be configured to contain one or more logical nodes per physical processor. For example, the system can be configured to implement one node per processor in a shared-nothing, MPP system or multiple nodes in a symmetric multiprocessor (SMP) system. This paper provides an overview of the storage model, query optimization, runtime system, utilities, and performance of DB2 Parallel Edition.

Workstation metrics

The use of measurement methods, called benchmarks, to predict how well different classes of computers will perform various tasks is discussed, and some popular benchmarks are considered. The problems entailed in benchmarking massively parallel processors and symmetric multiprocessing systems and, even more difficult, graphics workstations are examined. Requirements for advanced applications are addressed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Implementation of the subspace iteration method for eigenproblems on a symmetric multiprocessor system

The popular subspace iteration method for eigenproblems in science and engineering is reviewed briefly. Its suitability for execution on a parallel computer is then discussed. The algorithm was programmed for a shared memory symmetric multiprocessor system. The implementation of the algorithm on the parallel system is described. Timings, speed-ups and efficiencies for the parallel version of the program are given. It is concluded that this is a highly parallelizable algorithm, and high efficiency, in terms of processor utilization, was predicted and achieved.

Performance evaluation of a commercial cache-coherent shared memory multiprocessor

This paper describes an approximate Mean Value Analysis (MVA) model developed to project the performance of a small-scale shared-memory commercial symmetric multiprocessor system. The system, based on Hewlett Packard Precision Architecture processors, supports multiple active user processes and multiple execution threads within the operating system. Using detailed timing for hardware delays, a customized approximate closed queueing model is developed for the multiprocessor system. The model evaluates delays due to bus and memory contention, and cache interference. It predicts bus bandwidth requirements and utilizations for the bus and memory controllers. An extension to handle I/O traffic is outlined. Applications are profiled on the basis of execution traces on uniprocessor systems to provide inputs parameters for the model. Performance effects of various detailed architectural tradeoffs (memory interleaving, lower memory latencies) are examined. The sensitivity of overall system performance to various parameters is explored. Preliminary measurements of uniprocessor systems are compared against the model predictions. A prototype multiprocessor system is under development. We intend to validate the modeling results against measurements.

An experimental study of processor thrashing in multiprocessor systems

A special occurrence of a phenomenon calledprocessor thrashing caused by processor lockouts within the dispatcher of a symmetric multiprocessor system is studied. Results derived from simulation experiments involving up to 16 processors show that the potential danger of processor thrashing can be reduced noticably by locking only parts of the dispatcher's data during a specific dispatcher operation. The algorithms and data structure of a highly efficient implementation are outlined based on this principle and its performance is compared with a simple monitor realization of a dispatcher.