Symmetrical Inverter Research Articles

Improved power quality operation of symmetrical and asymmetrical multilevel inverter using invasive weed optimization technique

Low switching frequency pulse width modulation (PWM) technique for modulation and control of multilevel inverter in medium voltage high power applications is preferred in order to reduce the switching losses. In this context, a multilevel inverter operated with Selective harmonics minimization PWM technique offers better quality waveform at reduced switching losses. After the Fourier series analysis, the system of non-linear simultaneous transcendental equations is obtained. These equations are then solved to obtain switching angles to have certain low order harmonics at minimum value and regulation in the fundamental voltage magnitude. In this paper, a novel invasive weed optimization (IWO) technique is proposed to compute switching angles. The proposed technique can compute switching angles for both symmetrical and asymmetrical multilevel inverters. Thus it has superiority over well-known optimization techniques such as GA, PSO, DE, and ACO, etc. Moreover, in certain modulation index ranges, it provides faster convergence and accurate results which have been demonstrated in the paper. The computational results have been verified with the experimental result on the prototype developed in the laboratory. The field programming gate arrays (FPGA) based controller is used to implement the proposed technique. The hardware results have been found in close agreement with the computed results.

A novel 7-Level symmetric inverter module with less circuit components

Multilevel Power Converters (MPCs) have vast potential in power electronics research and development of DC-AC electrical energy conversion system. MLIs have become an inescapable power electronics device in various power conversion applications due to the incompatibility of traditional two-level inverters. MLIs are extremely popular for medium power and high AC voltage applications, and thus predicted to gather incessant attention in future. This article suggests a novel single-phase symmetric 7-level inverter suitable for a renewable energy application with an effort to lower the count of switching components and conducting devices in the path for the flow of current. The proposed symmetric type inverter circuit could produce 7-level output voltage by using three DC sources and seven power electronic switches. The suggested inverter structure can be used to generate any number of voltage levels, and it can produce all output voltage levels (i.e.,+ve,-ve and zero), which significantly reduces the inverter's total standing voltage. The performance of the suggested 7-level inverter topology was confirmed by simulation results obtained in MATLAB/Simulink.

7 level symmetrical inverter for photovoltaic system

This research presents the design, implementation, and evaluation of a seven-level symmetrical inverter for photovoltaic systems. The inverter is based on a cascaded H-bridges topology with distinct DC assets and is capable of efficiently converting DC power from a photovoltaic system to AC power with low Total Harmonic Distortion (THD). The system consists of a solar panel, charge controller, battery bank, and a multilevel inverter circuit. The inverter employs Pulse Width Modulation (PWM) techniques to control the output voltage and frequency, ensuring that it is suitable for the AC load. The performance of the inverter is analyzed using Fast Fourier Transform (FFT) to determine the THD, and the results are compared with those of other multilevel inverter topologies such as diode clamped (neutral clamped) and flying capacitors. The efficiency of the seven-level symmetrical inverter is evaluated under different load conditions and compared with other multilevel inverters to determine potential energy savings and performance improvements. The analysis provides insights into the advantages and limitations of the seven-level symmetrical inverter for photovoltaic systems, highlighting the importance of distinct DC assets in achieving high efficiency and low THD. The results of this research can be useful for designing and implementing high-performance and cost-effective photovoltaic systems.

Selective Harmonic Elimination Based THD Minimization of a Symmetric 9-Level Inverter Using Ant Colony Optimization

This paper proposed a new topology of a symmetric single-phase multilevel inverter with the smaller number of semiconductor switches and optimized low-frequency control methods to optimize the Total Harmonic Distortion. A nine-level single phase output is obtained by eight number of active semiconductor switches, four diodes and four capacitors from two asymmetrical dc sources. The selected harmonic order in the output voltage is eliminated by the PWM (SHE-PWM) based on selective harmonic elimination. To optimize the switching angles, an ant colony optimization is introduced. The proposed SHE-PWM and ant optimization are implemented and tested for THD on the SIMULINK platform. The proposed approach offers less THD and is best suited to high-power applications with medium voltage.

A Reduced Switch Count Seven Level Symmetrical Inverter with Low Distortion

Various types of new structures in multilevel inverters are evolving day by day. One among those is the reduced switch count type multilevel inverters. This inverter consists of low number of switches, gate driver components, and other switches like auxiliary switches. Depending on the value of the voltage sources we have symmetrical and asymmetrical multilevel inverters. In this paper, the seven level symmetrical inverter design is shown for seven levels in its output. The output voltage waveform is plotted and its FFT is performed and the THD values are shown. The inverter is simulated in SIMULINK software. Index Terms: Seven level MLI, inverter, and Modular Inverter.

A Novel Cascaded Symmetric and Asymmetric Multilevel Inverter Topology with Minimum Number of Power Electronics Components

A Novel Cascaded Symmetric and Asymmetric Multilevel Inverter Topology with Minimum Number of Power Electronics Components

Performance analysis of a Scalar Coupled and Decoupled PWM Technique for a Three Level symmetrical Dual Inverter Fed OEWIM Drive

Dual inverter fed IM drive is commonly employed in EV applications. In this application, SVPWM based PWM generator was utilised. However, they produce a high common-mode voltage(CMV). Because of this, bearing of motor will be affected and in turn, results in EMI problems. Hence, to overcome this problem, this work introduced a novel PWM generation techniques named scalar coupled and decoupled PWM topology to control a three-level symmetrical DI fed OEWIM. Hence, to find out the effectiveness of the proposed topologies, its operation is examined under both continuous and discontinuous modes of operation using MATLAB simulation. From the acquired results, it is concluded that this coupled PWM topology topology exhibits reduced CMV and harmonics when compared to decoupled topology

An Efficiency Analysis of 27 Level Single-Phase Asymmetric Inverter without Regeneration

For medium voltage applications, multilevel inverters are used. One of its classic topologies is the Cascaded H-Bridge, which requires isolated DC voltages to work. Depending on the DC voltage ratio used in the Cascaded H-bridge can be classified into symmetric and asymmetric. In comparison between symmetric and asymmetric inverters, the latter can generate an AC output voltage with more output voltage levels. DC voltage ratio most documented are binary and trinary. The last can generate an AC voltage of 3n = 27 levels is obtained, using n = 3 inverters in cascade and NLM modulation, which generates a flow power of the load to the inverters (regeneration). This work analyzes the semiconductor losses (switching and conduction) and the THD of the AC output voltage in function of index modulation, considering a non-regenerative modulation technique for a 27-level single-phase asymmetric inverter. To confirm the theoretical analyzes, simulation and experimental results are shown.

A hybrid T-type (HT-type) multilevel inverter with reduced components

This paper introduces a new HT-type module for both symmetrical and asymmetrical multilevel inverters (MLIs) with reduced power electric components. The proposed module comprises of two back to back T-type inverters connected with four cross-connected switches. This MLI addresses two major drawbacks associated with the conventional and other recently proposed MLIs which are the high voltage stress of switches and higher power component counts. The structure of the proposed device is designed combining the beneficial features of both T-type inverter and cross-switched inverter. The 1st feature allows the module to produce negative voltage levels deprived of any extra H-bridge circuit and thus decreasing the overall voltage stress significantly. The latter feature allows the device to utilize reduced number of switches to produce higher voltage levels. A comprehensive comparative analysis is additionally established between other MLI topologies to confirm the superiority of the HT-type MLI. From this analysis, it is found that the proposed MLI has successfully overcome the issues associated with other MLIs, it was able to produce the results following industrial standards and it outperformed other MLIs in different aspects such as power components count, cost, efficiency and dynamic performance. Selective harmonic elimination pulse width modulation (SHE-PWM) and nearest level control (NLC) algorithm is considered in this manuscript to generate the output results from the proposed HT-type module. All the details about the operating principle and modulation techniques utilized for the proposed MLI module are stated and validated by both simulation and experimental results.

Symmetrical and Asymmetrical Reduced Device Multilevel Inverter Topology

This article presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration and 13- and 17-level output voltage in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of dc sources, semiconductor switches, capacitors, and diodes compared with classical and recently proposed topologies. Reduction in component count decreases the size, complexity, and cost of the overall converter. A detailed comparison has been done of the presented topology with the recently proposed topologies in terms of dc sources, semiconductor switches, capacitor, and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented 9-, 13-, and 17-level MLI topologies has been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes, and nonlinear load.

An improved low switching frequency modulation scheme for a symmetric CCS-multilevel inverter

An improved low switching frequency modulation scheme for a symmetric CCS-multilevel inverter

A Novel Higher Level Symmetrical and Asymmetrical Multilevel Inverter for Solar Energy Environment

ABSTRACT In this paper, a higher level symmetrical and asymmetrical multilevel inverter (MLI) with reduced device count is proposed for renewable energy systems. Multilevel inverters are recently gaining importance in renewable energy systems and other DC to AC conversion applications due to reducing voltage stress, low total harmonic distortion (THD) and high-quality output as compared to classical inverters. This paper present a basic cell unit of reduced device count (RDC) MLI with six switching devices is proposed. The topology has advantages of reduced device count over existing topologies for the same number of output levels, thus improving operating efficiency and reliability. Upon cascading two such basic cells with 12 devices synthesizes a 49 level output with an estimated THD of 1.63%. The other advantages accrued due to reduced device count are a reduction in switch driver circuits, less number of required dc voltage sources, less installation space and reduction in cost. The major benefit of the proposed topology is that it can deliver power from an asymmetrical source to load even under sudden variation in environmental conditions. The proposed MLI topology is simulated in MATLAB/Simulink environment and a laboratory prototype is developed and tested in the lab. The control paradigm is developed as the Simulink model, which is interfaced with dSPACE DS-1104 for generating control pulses to drive switches of proposed MLI topology. The experimental results validate the concept and paradigm of the proposed MLI topology.

Compact symmetrical and asymmetrical multilevel inverter with reduced switches

The need for a multilevel inverter for medium voltage high power applications has attracted researchers and industrialists to focus on the design of hybrid multilevel inverter topology that uses a considerably lesser number of switches and sources. This paper proposes a symmetrical and asymmetrical multilevel inverter with reduced switches. The novelty of the proposed arrangement is lesser ON state switches and reduced total blocking voltages across switches. The optional series connection of the basic unit increases output voltage levels with high-quality output voltage. There are multiple algorithms proposed by varying the DC sources to generate different voltage levels using the same configuration. A suitable comparison is presented with conventional topologies and inverters of the same structure. The proposed topology is simulated and validated on hardware setup for both 7 levels, symmetrical and 15 levels, asymmetrical is performed using dSPACE 1104 controller. The impact of change in modulation index on the power and efficiency of the proposed 15-level inverter is validated under laboratory setup. The feasibility of this topology favors renewable energy integration applications.

A Novel Symmetrical Multilevel Inverter with Reduced Switch Count

Multilevel inverters produced lot of interest in academia and industry as they are becoming feasible technology for number of applications. These are considered as the progressing power converter topologies. To generate a quality output waveform with minimum number of switches, reduced switch multilevel inverter topologies has come in focus. This paper introduces a modified symmetrical MLI with reduced component count thereby ensuring the minimum switching losses, reduced total harmonic distortion, Size and installation cost. By proper combination of switches it produces a staircase output waveform with low harmonic distortion. In this paper novel symmetrical inverter topology with reduced component count based on level shift phase opposition and disposition PWM (PODPWM) is proposed. The results are validated using MATLAB/SIMULINK.

Synchronous Optimal Pulsewidth Modulation for Synchronous Machines With Highly Operating Point Dependent Magnetic Anisotropy

The performance of synchronous optimal pulsewidth modulation is investigated for the control of an automotive low voltage electrical drive system, which consists of a two-level voltage source inverter and an interior permanent magnet synchronous motor. The machine magnetic anisotropy varies due to magnetic saturation and cross-saturation effects and depends on the motor operating point. The main objective of this article is to investigate the influence of the varying magnetic anisotropy on the optimized half-wave symmetric inverter pulse patterns. For this purpose, the optimized inverter switching angles are derived by minimizing the current harmonic distortion of an isotropic and anisotropic permanent magnet synchronous motor. Their performance is evaluated and compared by experimental results.

FPA Optimized Selective Harmonic Elimination in Symmetric–Asymmetric Reduced Switch Cascaded Multilevel Inverter

Symmetrical and asymmetrical multilevel inverters (MLIs) have demonstrated its usefulness in a wide range of applications. This is accomplished due to the ongoing improvement by reducing the converter size and enhancement in the voltage quality. In this article, a generalized cascaded MLI structure is developed, which can operate in both symmetric and asymmetric modes. Comparative assessment in terms of the number of components and voltage stress warrants the design superiority. A new selective harmonic elimination (SHE) control using flower pollination algorithm (FPA) is investigated for the developed asymmetrical MLI. The salient features of the FPA such as less burdensome compilation and ability tos single-stage local and global search ascertain the elimination of the targeted harmonics through optimum angles computation. Moreover, the competence of the FPA is verified by comparing it with well-known SHE algorithms. Simulation analysis is carried out in MATLAB/Simulink environment, which validates the workability of the developed system. Experimental tests using fundamental and high switching frequency control techniques are further conducted under a dynamic environment to demonstrate the efficacy of the proposed methodology.

A New and Generalized Structure of MLI Topology with Half-bridge Cell with Minimum Number of Power Electronic Devices

Rapid developments in the field of high-power, high-voltage applications have led to a tremendous increase in the popularity and utility of multilevel inverters. The requirement of reduced harmonics coupled with an ever-increasing demand for clean and renewable energy sources has led to a great interest in the multilevel inverter. This paper presents a novel architecture of a single-phase multilevel inverter that utilizes fewer power electronic switches and driver circuits than various popular multilevel inverter circuits. The design presented is generalized in nature, thereby allowing for the generation of any number of levels in the output voltage. The working and modes of operation of the 9-level symmetrical configuration of the proposed topology is extensively elaborated. Simulation results from MATLAB Simulink as well as real-time hardware results have been included to verify the existence and proper working of the proposed 9-level symmetrical and 15-level asymmetrical inverter. Comparison results with other discussed configurations are also included to further establish the advantages possessed by the proposed circuit.

Implementation of 5-Level H-Bridge Inverter with Multicarrier based Modulation Techniques

Paper Setup must be in A4 size with Margin: Top In the present paper multi carrier sinusoidal modulation technique which is an efficient method of producing control signals is used for a symmetrical inverter with several levels in cascade H Bridge is discussed. The Cascaded H-Bridge performance output levels depend on the DC voltage sources used at the input side. With the help of two DC voltage sources, five level output can be obtained whereas three sources gives levels of seven in output voltage. In this paper, multi-carrier SPWM switching is obtained for switching of multilevel inverter based switches. Two signals are used in this switching method, among which one of the signals is reference which is a low frequency sinusoidal signal and the one is a carrier signal. In case of sinusoidal PWM method of modulation technique, the reference signal is a sinusoidal one and triangular signal can be used as a carrier signal. These types of inverters have the ability to generate inverted output voltage with an efficient harmonic spectrum and reliable output results. This document provides switching signal for H-bridge inverter structure which can improve harmonic performance. The 5-level multilevel inverter is simulated for traditional carrier-based pulse-width modulation (PWM) phase change carrier techniques. The total harmonic performance of the output voltages is analyzed for the two PWM control methods. The performance of the symmetrical PWM CHB is simulated using MATLAB-SIMULINK model. Model results show that THD can be minimized to a limit with level shifted modulation method of the sinusoidal pulse width. The results from the simulations show that the quality of the waveform of the output voltage improves with less loss and with a lower THD.

Modified symmetrical inverter topology and switching pulse generation using logic gates

Multilevel inverters are more reliable and better quality dc-dc power converters and received much greater attention in the field of low voltage and medium power applications. The objective of this paper is to propose a new 11 level symmetrical multilevel inverter to generate staircase output voltage. The proposed inverter structure consists of four dc voltage sources and ten power electronic switches to synthesize 11-levels across the load. Different comparison results are provided based on number of switches, total number of conducting switches and total blocking voltage. Switching pulses are obtained by using multicarrier based digital logic technique. Finally, various simulation results are presented to validate the proposed inverter for different RL load.

Harmonic Analysis of Symmetrical and Asymmetrical Cascaded H-Bridge Multilevel Inverter

This paper proposes harmonic comparison between Symmetrical and Asymmetrical CHB MLI using multiple carrier based phase disposition PWM technique (PDPWM). Topologies of different multilevel inverter are reported in the literature, but mainly this work focuses on the harmonic comparison of Symmetrical and Asymmetrical cascaded MLI with same count of sources and switches. In this paper, PWM switching technique for harmonic comparison of both symmetrical and asymmetrical cascaded MLI is PD. Total harmonic distortion is analyzed in FFT window. Results are observed in SIMULINK/MATLAB software. In these comparative results we can see that an asymmetrical configuration is producing higher voltage levels in voltage output with equal quantity of component compared with the 5-level symmetric inverter and this could lead towards the reduction in harmonic content of output voltage. The benefits of this method of control are applicability and simplicity for n-levels MLI, with no any considerable change in the control circuitry. The experimental measurement results validate proper operation of the discussed MLI