Switching Activity Research Articles

Multi-Level Sum of Product (SOP) Network Power Optimization Based on Switching Graph

The article presents the methodology of optimization of technology mapping of a multi-output function implemented in the form of sum of product (SOP) networks. The optimization is based on the concept of reducing the switching activity of combinational circuits. The aim of reducing network switching is to limit the consumption of dynamic power. Since dynamic power is one of the components of the total power consumed by digital systems, this leads to an optimization focused on the energy efficiency of digital systems. The basis of the proposed method is the technology mapping using a modified output graph describing the result of minimizing the multi-output function. The modified output graph, in terms of parameters associated with dynamic power, is defined as a switching graph. It was assumed that the key parameter associated with dynamic power is the switching activity of individual nodes of the logic network. The article presents elements of switching graph optimization which lead to the improvement of parameters associated with the dynamic power of the circuit. The essence of the proposed optimization methods is the appropriate movement of products and connections occurring in the logic network. Reducing the number of logic network vertices is also extremely important. The effectiveness of the proposed method was confirmed by the results of experiments performed on selected benchmarks. A significant reduction in the total value of switching activity was obtained for the optimized structures.

Design and implementation of low power multiplierless FIR filters on FPGA and ASIC

ABSTRACT This paper presents a low-power design and implementation approach for multiplierless FIR filters by reducing switching activity between filter coefficients using different optimisation algorithms. The objective function simultaneously minimises hamming distance between the consecutive filter coefficients, passband, and stopband ripples. Low-pass, high-pass, band-pass, and band-stop FIR filters of different order and word lengths are designed using improved grey-wolf optimisation. Comparison with grey-wolf optimisation, hybrid particle swarm optimisation, and grey-wolf optimisation, and whale optimisation algorithms is performed for different statistical parameters. The proposed filter is also compared with existing filter designs and shows considerable improvement in design metrics. For low-power implementation of designed FIR filters, carry-save-adder trees are utilised. FPGA and ASIC platforms are used for implementation. Basys-3 (Artix-7) FPGA board is targeted using the Vivado tool for FPGA implementation. Hardware design metrics such as slice LUTs, slice registers, slices, and dynamic power consumption are obtained. ASIC implementation is also performed using the Cadence Genus tool for a 45 nm Nan gate open cell library and total area, power, and delay are reported. The obtained results for FPGA slice utilisation and power consumption provide an average reduction of 61.39% and 74.13%, respectively. ASIC implementation provides an average 58.60% reduction in area-power product.

Low-power coding method in data transmission systems

The object of the study is the Network-on-Chip (NoC) technology, which has become a popular choice for the on-chip communication architecture of modern System-on-Chip (SoC) devices. The subject matter of the article is methods of reducing dissipated power in NoC and SoC. The goal of the work is: development of a low-power coding method that allows for the efficient transmission or storage of information. The following tasks are solved in the article: analysis of classification methods for combinatorial structures, construction a system of typical representatives and analysis of their characteristics. The research methods are based on the use of set theory, system theory and combinatorics. The following results are obtained: analyzed factors that affect the dissipated power, considered principles of constructing energy-efficient codes. It is shown that switching activity significantly affects the total power and one of the effective methods for reducing switching activity during communication between devices or on-chip communication is the use of low-power coding methods. A method of hierarchical classification of unit distance codes and algorithms for solving step-by-step problems have been developed. The method is based on the invariant approach and construction of a system of different representatives. Estimates of their number have been obtained, characteristics have been determined, and catalogs of typical representatives have been formed. Conclusions. The article analyzes factors that affect dissipated power, and considers the principles of constructing energy-efficient codes. A method of hierarchical classification of single distance codes and algorithms for solving step-by-step problems have been developed, and catalogs of typical representatives have been formed. The application of the developed method will allow developers to analyze and select codes with the best properties and, as a result, obtain better results in terms of network delays, energy costs, and other design limitations for computer systems.

Programmable Analog Circuits with Neuromorphic Nanostructured Platinum Films

AbstractSelf‐assembled nanoparticle or nanowire networks have recently come under the spotlight as systems able to emulate brain‐like data processing performances by exploiting the memristive character and the wiring of the junctions connecting the nanostructured network building blocks. Recently it is demonstrated that nanostructured Au films, fabricated by the assembling of gold clusters produced in the gas phase, have non‐linear and non‐local electric conduction properties caused by the extremely high density of grain boundaries and the resulting complex arrangement of nanojunctions. These observations suggest that nanostructured metallic films can be explored and exploited as a novel class of neuromorphic systems for unconventional electronic devices. Here it is reported that nanostructured cluster‐assembled Pt films show resistive switching activity, negative differential resistance, and reversible memory effects. These properties allow the use of nanostructured Pt films in programmable analog circuits, such as gain amplifiers and relaxation oscillators with fast response.

Metaheuristic algorithm inspired by enterprise development for global optimization and structural engineering problems with frequency constraints

In this study, a novel metaheuristic optimization algorithm inspired by the enterprise development (ED) process was developed. This process encompasses tasks, structure, technology, and human interactions. A mechanism for switching activities was utilized to determine each step by updating the searched solutions. The ED optimizer underwent evaluation against 50 mathematical functions and 54 IEEE Congress on Evolutionary Computation (CEC) functions, and it was compared with six up-to-date algorithms, three winners of CEC 2020 in real-world single-objective constrained optimization, and ten well-known algorithms. The evaluation results revealed that the ED optimizer outperformed the algorithms in mathematical tests. Using finite element simulation, this novel method was applied to minimize steel structure component weights under various frequency constraints. The engineering designs included a 37-bar planar truss, a 52-bar dome, a 72-bar space truss, a 600-bar dome, and a 1,410-bar dome. Optimization results for these structures showed that the developed ED optimizer yielded the optimal solution and required fewer function evaluations. In conclusion, the ED optimizer is a superior metaheuristic algorithm that can effectively solve complex structural design problems.

Dynamic Power Saving for CMOS Circuits

With more functionalities being integrated into a microchip today, higher processing power is drawn. As a result of this, clock and logic power consumption has turned out to be a critical issue to be coped with by chip designers. In this paper, we present various power-saving approaches employed in complementary metal oxide semiconductor (CMOS) circuit designs. The approaches involve restructuring the logic circuits, performing clock gating, and selecting the appropriate circuits for counters and frequency divisions. In order to show their efficacies in power optimization, the approaches were applied to a phase-locked loop (PLL), clock divider (CD), full adder (FA), counter, arithmetic logic unit (ALU), and microprocessor without interlocked pipelined stages (MIPS) circuits and validated using Intel Quartus Prime Lite and Mentor Graphics Modelsim. The following conclusions can be drawn from the results: Firstly, the efficacy of minimizing power dissipation using logic restructuring is found to be in direct proportion with the rate of the switching activity (SA); secondly, a maximum of 3.5% of thermal power dissipation can be saved using clock gating; thirdly, gray counters give the lowest power consumption; and, finally, the thermal power estimation for the phase-locked loop (PLL) is relatively higher than that for the clock divider (CD) when both of them are implemented for dividing frequencies.

Molecular Origins of Long-Term Changes in a Competitive Continuous Biosensor with Single-Molecule Resolution.

Biosensing by particle motion is a biosensing technology that relies on single-molecule interactions and enables the continuous monitoring of analytes from picomolar to micromolar concentration levels. However, during sensor operation, the signals are observed to change gradually. Here, we present a comprehensive methodology to elucidate the molecular origins of long-term changes in a particle motion sensor, focusing on a competitive sensor design under conditions without flow. Experiments were performed wherein only the particles or only the surfaces were aged in order to clarify how each individual component changes over time. Furthermore, distributions of particle motion patterns and switching activity were studied to reveal how particle populations change over timespans of several days. For a cortisol sensor with anticortisol antibodies on the particles and cortisol analogues on the sensing surface, the leading hypotheses for the long-term changes are (i) that the particles lose antibodies and develop nonspecific interactions and (ii) that analogue molecules dissociate from the sensing surface. The developed methodologies and the acquired insights pave a way for realizing sensors that can operate over long timespans.

Active playful learning as a robust, adaptable, culturally relevant pedagogy to foster children’s 21st century skills

ABSTRACT Drawing upon Vygotskian and Piagetian learning theories, recent research reveals children’s learning can be maximized through a specific Active Playful Learning (APL) approach called guided play. The deepest and most engaging learning happens during guided play. In guided play, adults might prepare an environment and set a learning goal, but children get to direct their own play and exploration towards that goal. Research suggests that guided play fosters math skills, shape knowledge, task switching, spatial vocabulary, literacy, language, social interaction, and physical activity. The intersection of play and the intentionality of having a learning goal holds great potential as a pedagogical approach that can be applied to technology, community spaces, and to classrooms. We describe current directions in: (1) the conceptualization of guided play, (2) areas for implementing this approach in formal and informal education (including television and digital applications, as in the case of Sesame Street), and (3) future opportunities and challenges.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

RCVM‐ASS‐CICSKA‐PAPT‐VDF: VLSI design of high‐speed reconfigurable compressed Vedic PAPT‐VDF filter for ECG medical application

AbstractDuring signal acquisition, the signals are impacted by multiple noise sources that must be filtered before any analysis. However, many different filter implementations in VLSI are dispersed among many studies. This study aims to give readers a systematic approach to designing a Pipelined All‐Pass Transformation based Variable digital filter (PAPT‐VDF) to eliminate the high‐frequency noise from ECG data. The modified design emphasizes first‐ and second‐order responses to obtain high‐speed filter realization with high operating frequencies. The addition of adder and multiplier designs to the hardware architecture of a filter design improves performance. The fundamental blocks of the filter design are the adder and multiplier. The adder and multiplier are employed with an Adaptable stage size‐based concatenation, incremented carry‐skip adder (ASS‐CICSKA), and Improved reconfigurable compressed Vedic multiplier (IRCVM). Utilizing the adder design diminishes the delay with enhanced performance because receiving the carry from an incrementation block is not mandatory. In the multiplier design, the compressor and the reconfigurable approach are adapted with a data detector block to detect the redundant input and lower the logic gates' switching activity with less area overhead. The proposed filter design is implemented in vertex 7 FPGA family device, and the performance measures are analyzed regarding area utilization, delay, power, and frequency. Also, by using the denoised signal, the mean square error (MSE), and signal‐to‐noise ratio (SNR) are evaluated in the MATLAB platform.

Implementation of Full adder in Multiple valued Logic for Performance Optimization

Multiple valued logic is now becoming more significant in real-world applications. Mathematical design blocks are essential in digital and mixed-signal systems. A system's arithmetic blocks often use the most power because of the high switching activity. Implementations of quaternary arithmetic may be a way to cut down on energy use while improving system performance. In this paper, quaternary adders are developed using three different approaches, and their binary equivalents are evaluated in terms of size, predicted logic depth, and performance estimation.

Basic Approaches for Reducing Power Consumption in Finite State Machine Circuits—A Review

Methods for reducing power consumption in circuits of finite state machines (FSMs) are discussed in this review. The review outlines the main approaches to solving this problem that have been developed over the last 40 years. The main sources of power dissipation in CMOS circuits are shown; the static and dynamic components of this phenomenon are analyzed. The power consumption saving can be achieved by using coarse-grained methods common to all digital systems. These methods are based on voltage or/and clock frequency scaling. The review shows the main structural diagrams generated by the use of these methods when optimizing the power characteristics of FSM circuits. Also, there are various known fine-grained methods taking into account the specifics of both FSMs and logic elements used. Three groups of the fine-grained methods targeting FPGA-based FSM circuits are analyzed. These groups include clock gating, state assignment, and replacing look-up table (LUT) elements by embedded memory blocks (EMBs). The clock gating involves a separate or joint use of such approaches as the (1) decomposition of FSM inputs and (2) disabling FSM inputs. The aim of the power-saving state assignment is to reduce the switching activity of a resulting FSM circuit. The replacement of LUTs by EMBs allows a reduction in the power consumption due to a decrease in the number of FSM circuit elements and their interconnections. We hope that the review will help experts to use known methods and develop new ones for reducing power consumption. We think that a good knowledge and understanding of existing methods of reducing power consumption is a prerequisite for the development of new, more effective methods to solve this very important problem. Although the methods considered are mainly aimed at FPGA-based FSMs, they can be modified, if necessary, and used for the power consumption optimization of FSM circuits implemented with other logic elements.

Dynamic DNA Assembly by Programmable Hybridization Chain Reaction Mimicking Tubulin.

Dynamic biological structures involve the continual turnover of molecules within supramolecular assemblies such as tubulin. Inspired by dynamic biology self-organizing systems, we build an artificial dynamic structure based on DNA nanotechnology through a nonequilibrium chemical system. Herein, a metastable domain (MD), essentially a stem-loop structure, was introduced into DNA hairpins within hybridization chain reaction (HCR), thereby imparting dynamic activity to the DNA polymers. Hairpins with MD thermodynamically assemble to a high-energy polymer in the presence of trigger strands. The polymer can relax back to the stable unassembled state once the invader is added and finally relax to the activated hairpin by an anti-invader. Reversible assembly/disassembly of the HCR is achieved through invader/anti-invader cycles. We accomplished kinetic modulation, reversible conformational switching, cascading regulation, and enzyme activity control through the MD-HCR. We believe that the design of the MD-HCR could inspire the development of autonomous biological functions within artificial systems.

Reliable single-ended ultra-low power GNRFETs-based 9T SRAM cell with improved read and write operations

This paper presents a reliable single-ended nine-transistor (9T) static random access memory (SRAM) cell which is based on 16 nm graphene nanoribbon FETs (GNRFETs) technology. Single-ended operation significantly reduces switching activity and layout area. Therefore, the power consumption and area of the proposed cell is enhanced by 48.9 % and 3.8 %, respectively, as compared to the 2-bitline (2-BL) 9T SRAM cell. A separate read and write port provides significant improvement in the read and write performance simultaneously. The performance of the proposed cell and other existing cells are evaluated using HSPICE-simulations. The multi-threshold technology is used to improve the performance of cells in terms of delay and power consumption. The proposed cell shows significant improvement in read stability and write-ability due to proper device sizing ratio. In nanometer regime, the cell is capable to operate at ultra low supply voltage of 300 mV due to outstanding electrical property of the GNRFETs devices.

Performance Analysis of Hybrid Comparator using 45nm Technology

In the present real-time world, due to the improvements and innovations of System on Chip (SoC) applications, there is a requirement to integrate multiple technology design topologies. The electronic system design is classified as analog, digital, and mixed-signal design. The comparator is the major building block used in the datapath of System on Chip (SoC) application device. The usage of these devices depends on not only functionality but also on the non-functionality parameters considering different performance estimation metrics. The nonfunctional performance metrics for a transistor level design depends on the number of transistors, switching activities of logic level voltages and delay between input and outputs. These performance metrics are improved by considering the multiple logic families for multiple output generations instead of using a single logic family topology. The comparator is the major component in the arithmetic circuits for SoC applications and can be realized by using various design topologies. The vividly used topologies are Conventional CMOS logic, Pass Transistor Logic (PTL), Gate Diffusion Input (GDI) Logic, Stacking technique, Quantum-dot cellular automata, etc. The selection of the design topology for the comparator is made based on the non-functional parameters. The performance of non-functional parameters is improved by combining the topology architectures of different design techniques. In this paper, the comparator is designed using conventional CMOS logic, PTL, GDI, and a hybridized topology for best performance and the same is implemented using 45nm technology. These circuits are designed by using Cadence Virtuoso Electronic Design Automation (EDA) design tools. Non-functional performance parameters are analyzed for different topologies. Index Terms: VLSI Design, Comparator, Datapath, EDA tools, CMOS Logic, GDI Logic, PTL Logic.

Functionally Possible Path Delay Faults With High Functional Switching Activity

Functionally Possible Path Delay Faults With High Functional Switching Activity

A New Embedded Clock Gating Technique in 8- bit Synchronous Counter with Reduced Switching Activity for Clock Divider Circuit

Counters play an inevitable role in many VLSI circuits such as timers, frequency dividers, memories, and ADC/DAC. Integrating the timing discriminator, Pulse Swallow, and Correlated double sampling are various approaches used in counters for low power consumption. The main objective was to minimize the power consumption and device count. In this work, a new embedded clock gating technique is used in an 8-bit counter to reduce the switching activity. A clock gating circuit and clock buffer network pattern are used in the proposed algorithm to reduce the power consumption of synchronous counters. The proposed counter reduced the unwanted clock activity of all T FFs and noise is reduced to a greater extent thereby reducing the power and the device count. CMOS 45nm technology is used for designing the proposed counter 1.5 supply voltage. Simulated results show the improvement of the proposed approach over other conventional counters in terms of power consumption and device count.

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

Engineering the structural and electrical interplay of nanostructured Au resistive switching networks by controlling the forming process

Networks of random-assembled gold clusters produced in the gas phase show resistive switching (RS) activity at room temperature and they are suitable for the fabrication of devices for neuromorphic data processing and classification. Fully connected cluster-assembled nanostructured Au films are characterized by a granular structure rich of interfaces, grain boundaries and crystalline defects. Here we report a systematic characterization of the electroforming process of the cluster-assembled films demonstrating how this process affects the interplay between the nano- and mesoscale film structure and the neuromorphic characteristics of the resistive switching activity. The understanding and the control of the influence of the resistive switching forming process on the organization of specific structures at different scales of the cluster-assembled films, provide the possibility to engineer random-assembled neuromorphic architectures for data processing task.

Data branch sharing dual‐edge explicit‐pulsed level converting flip‐flops

AbstractVariable supply clustered voltage scaling (VS‐CVS) is an effective way to decrease power consumption without compromising performance. One of the major challenges in VS‐CVS design is that level converting flip‐flops (LCFFs) not only need to have low power consumption but also high performance. In this paper, we propose two new structures of LCFF: the data branch sharing LCFF based on conditional charging (DBS‐LCFFCC) and the data branch sharing LCFF based on precharging (DBS‐LCFFP). The new structures adopt a data branch sharing scheme to improve the speed of the circuit as well as to reduce the number of transistors. Based on simulation results using HSPICE with PTM 32‐nm CMOS technology, the proposed LCFFs show an improvement of 19.2–67.2% and 41.6–76.3% in power‐delay‐product (PDP) at 50% data switching activity, respectively, compared to other advanced LCFFs.