Switched-capacitor Power Amplifier Research Articles

A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM

This article presents a digital polar Doherty switched-capacitor power amplifier (SCPA) using on-chip self-calibration technique with storage capacitor array (SCA) to compensate the amplitude modulation (AM)–phase modulation (PM) distortion automatically for high data-rate signals. Such a self-calibration technique detects the AM–PM distortion at output and generates the related phase compensation in PM signals. The SCA is proposed to store control voltages of phase shifter for different amplitude code and decrease the settle time for high data-rate, which achieves fast locking of the calibration loop. Based on the proposed self-calibration with SCA, a polar Doherty SCPA is designed and fabricated in conventional 40-nm CMOS technology. This chip achieves 28.9-dBm peak output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{P}_\textup{sat}$</tex-math> </inline-formula> ) and 43.9% peak drain efficiency (DE) at 1.8 GHz. It supports 100-MHz 64-QAM/10-MHz 1024-QAM signal with 22.6-/21.3-dBm average output power and 33.9%/32.1% average DE without digital pre-distortion (DPD).

An Edge-Combining Frequency-Multiplying Class-D Power Amplifier

The class-D power amplifier (PA) is commonly implemented in CMOS, but its operating frequency is often limited due to the power loss of parasitic capacitances and the lower transition frequency of the PMOS transistor. In this brief we demonstrate edge-combining frequency-multiplication embedded directly in the output-stage, allowing higher-frequency operation of the class-D PA, while maintaining similar performance to a lower-frequency PA. A 65nm CMOS prototype achieves output power and system efficiency of 22.3dBm and 30.2%, respectively. The prototype is tested with a D-BPSK signal and achieves an EVM of 2%-rms. Although the prototype was not embedded with amplitude modulation capability, it can be readily adapted for such operation using switched-capacitor PA techniques.

Multiphase Interpolating Digital Power Amplifiers for TX Beamforming

This paper presents a four-channel beamforming TX implemented in 65 nm CMOS. Each beamforming TX is comprised of a C-2C split-array multiphase switched-capacitor power amplifier (SAMP-SCPA). This is the first use of multiphase interpolation (MPI) for beam steering. This technique is ideal for low-frequency beamforming and MIMO, as it does not require passive or LO-based phase shifters. The SCPA is ideal for use as the core element since it can perform frequency translation and data conversion, and drive an output at high power and efficiency in a compact die area. A prototype four-element beamforming TX, occupying 2mm×2.5mm, can achieve a peak output power of 24.4 dBm with a peak system efficiency (SE) of 24%, while achieving &lt;1∘ phase resolution and &lt;1 dB gain error. When transmitting a 15 MHz, 64-QAM long-term evolution (LTE) signal it outputs 18.4 dBm at 14% SE with a measured adjacent channel leakage ratio (ACLR) of &lt;−30 dBc and an error vector magnitude (EVM) of 3.27% RMS at 1.75 GHz. A synthesized beam pattern based on measured results from a single die achieves &lt;0.32∘ RMS beam angle error and &lt;0.1 dB RMS beam amplitude error.

A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS

Human body communications require energy-efficient transceivers to connect diverse devices on the human body for wellness and medical applications. This article presents a fully digital pulse-based transmitter (TX) for capacitive body-coupled communications (c-BCCs) in 28-nm Fully Depleted Silicon on Insulator (FD-SOI) CMOS. The TX is operating at 450 MHz where surface-wave (SW) propagation is the dominant mechanism of c-BCC, offering a larger bandwidth with a more stable channel. The heavily duty-cycled TX uses a 90-MHz free-running oscillator and edge combiners to generate OOK Gaussian-shaped pulses through a switched-capacitor power amplifier (PA). Wide range forward body biasing (FBB), specific to FD-SOI technology, allows frequency tuning and adaptive efficiency optimization as a function of data rate. The proposed TX consumes 17–76 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> for flexible data rates from 0.1 to 27 Mb/s (170 down to 2.8 pJ/b) with up to 14% system efficiency under 0.5-V supply voltage.

Impact of Forward Body-Biasing on Ultra-Low Voltage Switched-Capacitor RF Power Amplifier in 28 nm FD-SOI

The Switched-Capacitor Power Amplifier (SCPA) has become a key enabler for modern wireless communication because of its high efficiency, high linearity, and high integrability. This brief discusses the impact of the extended Forward Body-Biasing (FBB) feature in 28 nm FD-SOI technology on Ultra-Low Voltage (ULV) SCPA. A new model of the Drain Efficiency (DE) and System Efficiency (SE) including body-biasing and drivers power consumption is introduced and validated with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$SpectreRF$ </tex-math></inline-formula> simulations. FBB on the SCPA improves by up to 14 % and 67 % the SE and transistors area, respectively, compared to a nominally body-biased SCPA under 0.5 V supply voltage at 2.4 GHz, while improving linearity and enhancing PVT variations.

A 65 nm CMOS Quadrature Balanced Switched-Capacitor Power Amplifier for Full- and Half-Duplex Wireless Operation

This article proposes a multi-mode wireless transmitter for full-duplex (FD) and half-duplex (HD) operation based on a quadrature balanced switched-capacitor power amplifier (QB-SCPA) architecture in 65 nm CMOS. The QB-SCPA provides inherent passive transmit–receive (TX–RX) isolation along with an embedded digital self-interference cancellation (SIC) signal injection mechanism and exhibits excellent TX and RX linearity characteristics. To minimize noise figure degradation to the RX path, local oscillator (LO) signal sharing between the two SCPAs comprising the transmitter and a retiming circuit that generates the 25% clock signals is employed to obtain phase noise suppression at the LNA port. In the FD mode, 50 dB of SIC is demonstrated across the instantaneous bandwidth of a 20 MHz orthogonal frequency-division multiplexing (OFDM) signal with 11 dB peak-to-average power ratio (PAPR), along with −35 dB TX error vector magnitude (EVM) with SIC ON and without digital predistortion. The transmitter achieves a maximum output power of 23 dBm with 26.5% power-added efficiency (PAE) and 21 dBm with 17.4% PAE in HDTX and FD modes, respectively, and has a wide operating bandwidth between 1.5 and 3 GHz.

Design optimization guidelines for a class of RF switched-capacitor power amplifiers

An optimization methodology for a popular class of differential RF switched-capacitor power amplifiers exhibiting high efficiency, output power and linearity is presented. Analytical maximization of the output power with respect to component values provides explicit formulas and design guidelines for the amplifier’s core and the tuning of the matching network, that can be used as a starting point for the design and trimming of the power amplifier circuit in an IC design environment.

A Predistortion-Less Digital Transmitter With −50-dB ACLR Exploiting Output Conductance Linearization

Switched capacitor power amplifiers (SCPAs) are a class of digital transmitters which have shown promising results for high linearity with good drain efficiency (DE). Their linearity is limited by AM-PM distortion, caused by a difference in output conductance in switching and nonswitching driver cells. Often, digital predistortion (DPD) is required to transmit higher-order modulation schemes. In this letter, a driver cell implementation as an inverter with drain resistors is proposed which has equal output conductance in both cases, aiming to eliminate AM-PM distortion. An SCPA with these driver cells is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS process which demonstrates excellent DPD-less linearity with an adjacent channel leakage ratio (ACLR) of −50 dB and an error vector magnitude (EVM) of −45.5 dB for 5-MHz 1024 QAM signals at a DE of 8.8%. A matching network exploiting bondwires as high-Q inductors removes on-chip inductors and significantly reduces chip area.

A Multimode Multi-Efficiency-Peak Digital Power Amplifier

A 30.0-dBm polar digital power amplifier (PA) is implemented based on a switched-capacitor PA (SCPA) and multiple efficiency-enhancement techniques, such as Class-G, Doherty, and time interleaving (TI). The PA demonstrates six efficiency peaks and seamless efficiency curves between the peaks in the power back-off (PBO) region with the three efficiencyenhancement techniques. For the implementation of the efficient and linear Class-G technique, a linear single-supply current-reuse Class-G switch is proposed. It realizes a Class-G operation without any additional dedicated supply voltages, resulting in enhanced efficiency and reduced cost for an external power management unit (PMU). A local oscillator (LO) signal restoration technique is proposed to reduce the area and power consumption for the LO signal distribution. The prototype SCPA, fabricated in a 65-nm CMOS, generates 30-dBm peak output power (POUT) at 2.4 GHz and achieves drain efficiency (DE) (normalized DE) of 40.2% (100%), 37.9% (94.3%), 38.8% (96.3%), 36.3% (90.2%), 29.4% (73.0%), and 19.7% (48.9%) at 0-, 2.5-, 6-, 8.5-, 12-, and 18-dB PBOs, respectively. It achieves less than ±1° amplitude modulation (AM)-phase modulation (PM) distortion with a continuous-wave (CW) signal. It also demonstrates error vector magnitude (EVM) of -41.7 dB (-44.5 dB) and DE of 30.3% (36.2%) at an average output power of 19.1 dBm (23.2 dBm) for a 10-MHz 64-quadrature AM (QAM) orthogonal frequency-division multiplexing (OFDM) signal with a 10.9-dB peak-to-average power ratio (PAPR) (10-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR).

RF Switched-Capacitor Power Amplifier Modeling

Detailed state-space modeling and analysis of a class of RF switched-capacitor power amplifiers achieving high efficiency, output power, and linearity are presented. Time-domain voltage and current waveforms are analytically obtained via the steady-state solution of the amplifier's model equations. The output power of the fundamental and that of the harmonics, as well as the drain efficiency of the switched-capacitor power amplifier (SCPA) are derived. The state-space model is implemented in MATLAB and all theoretical results are compared to Cadence Spectre simulation of the SCPA and are found to be in good agreement.

Leveraging Programmable Capacitor Arrays for Frequency-Tunable Digital Power Amplifiers

This article presents a digitally frequency-tunable switched-capacitor power amplifier (SCPA) in 65-nm CMOS. The operable frequency range spans from 1.4 to 2.5 GHz. The center frequency is tuned by a programmable capacitor array, widely available from both monolithic microwave integrated circuit (MMIC) and MEMS manufacturers. A prototype is able to achieve a peak output power of 21.7 dBm with a peak system efficiency (SE) of 38.8%, while achieving 58.8% fractional bandwidth. When transmitting a 20-MHz, 64-quadrature amplitude modulation (QAM) long-term evolution (LTE) signal, it outputs 14.1 dBm at 15.7% SE with a measured adjacent channel leakage ratio (ACLR) <−30 dBc and error vector magnitude (EVM) of < 3.9% rms, without the use of digital predistortion (DPD).

Analysis of Switched Capacitor Losses in Polar and Quadrature Switched Capacitor PAs

This brief derives the efficiency limitations of switched capacitor power amplifiers (SCPAs) due to switched capacitor (SC) losses during charging and discharging of their capacitor arrays. Polar modulation is covered, as well as quadrature modulation both with clock duty cycles of 50% (Q50) and 25% (Q25). Closed form expressions are derived for both the maximum output power and SC power loss for signals with arbitrary phase and amplitude. These expressions are verified by simulations using ideal switches and capacitors, and 22 nm CMOS transistor models. These results are used to analyze the SCPA efficiency for 64QAM signals using a statistical model. It is shown that for a given array capacitance and supply voltage, the polar architecture is the most power efficient. Compared to polar modulation, the SC loss for 64QAM is fundamentally 18% higher for Q50 and 46% higher for Q25 SCPAs, whereas the generated output powers are fundamentally 6 and 3dB lower, respectively.

A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier

This article presents a multi-subharmonic switching (SHS) digital power amplifier (PA) architecture for enhancing power back-off (PBO) efficiency while achieving watt-level output power. The proposed phase-interleaved architecture provides the inherent cancellation of the subharmonic components in the PBO region, alleviating the burden of the matching network. The proposed multi-SHS scheme can be further combined with a class-G operation to create a greater number of efficiency peaks in the PBO region. A transformer-based, three-way power combiner and a triple-stacking class-D driver are utilized to obtain watt-level output power. The proof-of-concept PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS and achieved 30-dBm peak power at 1.9 GHz, with 45.9%/41.3%/35.3%/32.2%/24.2% drain efficiency located at 0-, -3.5-, -7.0-, -9.5-, and -12-dB PBO, respectively. The average efficiency was 31.4% in real-time operation with a 7.2-dB peak-to-average power ratio (PAPR) modulated signal.

A CMOS Polar Class-G Switched-Capacitor PA With a Single High-Current Supply, for LTE NB-IoT and eMTC

Class-G efficiency enhancement of switched-capacitor (SC) power amplifiers (PAs) requires the power management unit (PMU) to have two high-current power supplies. This paper presents a Class-G efficiency enhancement that only requires one single high-current power supply with a lower bandwidth requirement, significantly simplifying the PMU. The system analysis shows that a transmitter with a resolution of 13 bits and a sample rate of $F_{RF}/2$ meets the requirements of the Cat-M1 and Cat-NB1 standard. The presented PA consists of a number of parallel SC cells. Each cell can be configured in two output-power modes, using only a single supply. At 807 MHz, the peak output power is 27.1 dBm, with an efficiency (PAE) of 33.3%. The efficiency at −6 and −12 dBFS is 22.5% and 14.4%, respectively, which is an improvement of $1.3\times $ and $1.7\times $ compared to Class-B. The 13-bit resolution enables a power-control range for Cat-M1 and Cat-NB1 signals of >63 dB. In that range, the error vector magnitude (EVM) is <4.2%.

A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques

A 30.1-dBm quadrature transmitter is implemented based on Class-G IQ-cell-shared switched-capacitor power amplifier (SCPA) and voltage mismatch compensation techniques for dual-supply voltage in a Class-G SCPA. For the Class-G operation in the IQ-cell-shared quadrature SCPA, a merged cell switching (MCS) technique comprising vector amplitude switching (VAS) and vector phase switching (VPS) is proposed. The VAS boosts system efficiency (SE) by enabling the Class-G operation with multiple supply voltages and the VPS conserves vector information in the merged cells that process the quadrature vectors. The linearization technique for Class-G SCPA minimizes the distortion that arises from the supply-voltage mismatches in a multiple supply-voltage system. Two SCPAs are coupled with a power combining transformer to achieve a watt-level output power. A time-domain interpolation minimizes the spectral image. The prototype SCPA, fabricated in a 65-nm CMOS, achieves peak output power and SE of 30.1 dBm and 37.0%, respectively. It achieves error vector magnitude (EVM) of −40.7 dB (−40.3 dB) and SE of 14.7% (18.3%) at an average output power of 19.5 dBm (22.5 dBm) with 802.11g 64-QAM OFDM signal with 10.6 dB peak-to-average power ratio (PAPR) (20-MHz single-carrier 256-QAM signal with 7.6-dB PAPR).

An Efficient Class-G Stage for Switching RF Power Amplifier Applications

An efficient class-G stage based on a class-D power amplifier (PA) for switching RF PA applications is described. Class-G operation is achieved by introducing one additional transistor in a cascoded class-D PA, that can reduce area as well as enhance efficiency when compared to prior class-G designs. In addition, a multi-level switching operation is proposed which provides stacked class-G PA operation without using any additional switches. The stacked PA can avoid the requirement for an extra supply voltage for class-G operation. The efficiency and losses in the proposed design, as well as conventional designs, at various output power levels are analyzed by utilizing these in a 5-bit switched-capacitor PA (SCPA). A stacked class-G design with single supply voltage is also compared to an unstacked dual-supply class-G design. While the proposed approach has been explored in an SCPA, the approach can be applied to any switching RF PA architecture that employs a class-D PA.

A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, -3.5, -9.5, and, -13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at -13-dB PBO.

A Wideband Efficiency-Enhanced Class-G Digital Power Amplifier for IoT Applications

This letter presents a wideband digital power amplifier (DPA) with Class-G technique to enhance back-off efficiency for Internet-of-Things (IoT) applications. The switched-capacitor power amplifier topology is adopted for high linearity performance. A wideband matching network is proposed to achieve 0.54–0.95-GHz frequency coverage for 802.11ah and narrowband IoT standards. The measurement results demonstrate a flat frequency response with only 0.5-dB power deviation over 0.54–0.95 GHz. The DPA achieves the peak output power of 23.5 dBm with 42.7% peak PAE and 32.8% PAE at 6-dB back off. When amplifying an 8-MHz 64 quadratic-amplitude modulation 802.11ah signal at 800 MHz, it obtains −28.4-dB error vector magnitude and 30.1% average PAE at 16.5-dBm average output power.

Split-Array, C-2C Switched-Capacitor Power Amplifiers

This paper presents a 13-b C-2C split-array (SA) multiphase switched-capacitor power amplifier (SAMP-SCPA) implemented in 65-nm CMOS. The SAMP-SCPA was designed for 16-b resolution to offer extra states for linearization/calibration using digital pre-distortion (DPD). Resolution limits for SA SCPAs are presented. The SAMP-SCPA allows for the improvement of the SCPA resolution while minimizing the impact on the input power required driving it. A prototype SAMP-SCPA, occupying 0.85 mm $\times $ 2 mm, delivers a peak output power of 24 dBm with a peak system efficiency (SE) of 40% at 1.8 GHz. When amplifying a long-term evolution (LTE) signal, the average output power and SE are 18.8 dBm and 21.6%, respectively, with an adjacent channel leakage ration (ACLR) < −30 dBc and error vector magnitude (EVM) of 2.65% rms. The increased resolution allows output power to be traded off for improved linearity and a low power mode demonstrates an EVM as low as 1% rms.

Wideband Mixed-Domain Multi-Tap Finite-Impulse Response Filtering of Out-of-Band Noise Floor in Watt-Class Digital Transmitters

A major drawback of digital transmitters (DTX) is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to radio frequency and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in frequency-division duplexing systems due to receiver desensitization or impose stringent coexistence challenges. In this paper, we describe a DTX that embeds mixed-domain multi-tap finite-impulse response (FIR) filtering with programmable analog sub-sample delays within a highly linear and mismatch-resilient switched-capacitor DTX architecture. It is shown that switched-capacitor power amplifiers (SCPA) in conjunction with transformer-based power combining are ideal candidates for embedding mixed-domain FIR filtering since the near-constant source impedance of the SCPA greatly aids in linear FIR summation thereby preserving the desired noise-shaping profile. Moreover, their excellent mismatch characteristics help in ensuring precise tap weights in the FIR which enhances noise suppression. The availability of multiple taps in this architecture also allows the synthesis of FIR configurations with wide notch bandwidths (BW). Theoretical analyses of this architecture and design trade-offs related to linearity, mismatch, output power, and efficiency are discussed. The implemented 65 nm CMOS prototype exhibits a peak output power of 30.3 dBm and a peak system efficiency of 34%, and achieves a noise floor of -149 dBc/Hz over a BW of 20 MHz at an offset of 135 MHz from a 2.23 GHz carrier while transmitting a 1.4 MHz 64-QAM signal with an average output power of 22 dBm.