Surrounding Gate MOSFET Research Articles

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.

A unified short-channel compact model for cylindrical surrounding-gate MOSFET

For the first time, a continuous and explicit model valid in all operating regions, for undoped short-channel cylindrical gate-all-around (GAA) MOSFETs, is presented in this study. From a two-dimensional analysis, the threshold voltage roll-off, the drain-induced barrier lowering (DIBL) and the subthreshold swing are explicitly modeled. Short-channel effects are then implemented into a continuous drain-current model based on an effective surface potential approach using the gradual channel approximation. Improving the model behavior in the saturation operating region by accounting the channel pinch-off displacement, channel length modulation is studied and implemented as well. Analytical results are compared to TCAD-Atlas numerical simulations and validate the short-channel model in all operating modes making it suitable for circuit design simulations.

Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges

On the basis of 2-D potential analysis performed while taking into account the effective conducting path effect, a new analytical model for threshold voltage in cylindrical surrounding-gate MOSFETs (SGMOSFETs) that contain localized charges is presented. From the 2-D Poisson's equation based on a parabolic potential approximation, a simple and accurate analytical expression for the threshold voltage is derived. The proposed model is validated using a 3-D device simulator, and good agreement is obtained for various device dimensions and charge distributions. This model can be used to investigate hot-carrier-induced degradation of SGMOSFETs.

Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations

This paper presents a compact model for the electrostatic potentials and the current characteristics of doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. An analytical expression of the potentials is derived as a function of doping concentration. Then, the mobile charge density is calculated using the analytical expressions of the surface potential at the surface and the difference of potentials between the surface and the center of the silicon doped layer. Using the expression obtained for the mobile charge, a drain current expression is derived. Comparisons of the modeled expressions with the simulated characteristics obtained from the 3D ATLAS device simulator for the transfer characteristics, as well for the output characteristics, show good agreement within the practical range of gate and drain voltages and for doping concentrations ranging from 10 16 cm −3 to 5 × 10 18 cm −3.

A Compact Analytical Threshold-Voltage Model for Surrounding-Gate MOSFETs With Interface Trapped Charges

With the effects of equivalent oxide charges on flatband voltage, a compact analytical threshold-voltage model for surrounding-gate MOSFETs with interface trapped charges is developed based on the parabolic potential approach. The model shows how interface charge density, damaged zone, oxide thickness, and diameter of silicon body affect the threshold voltage. The model is verified by a 3-D device simulator and can be used to explore the hot-carrier-induced threshold-voltage behavior of surrounding-gate MOSFETs for its memory device application.

Continuous surface potential versus voltage equation of intrinsic surrounding-gate MOSFETs and analytic solution from accumulation to strong inversion region

A continuous surface potential versus voltage equation is proposed and then its solution is further discussed for a long channel intrinsic surrounding-gate (SRG) MOSFET from the accumulation to strong inversion region. The original equation is derived from the exact solution of a simplified Poisson equation and then the empirical correction is performed from the mathematical condition required by the continuity of the solution, which results in a continuous surface potential versus voltage equation, allowing the surface potential and the related derivatives to be described by an analytic solution from the accumulation to strong inversion region and from linear to the saturation region accurately and continuously. From these results, the dependences of surface potential and centric potential characteristics on device geometry are analyzed and the results are also verified with the 3-D numerical simulation from the aspect of accuracy and continuity tests.

Explicit Continuous Current–Voltage (<I>I</I>–<I>V</I>) Models for Fully-Depleted Surrounding-Gate MOSFETs (SGMOSFETs) with a Finite Doping Body

An analytical and continuous dc model for cylindrical doped surrounding-gate MOSFETs (SGMOSFETs) in the fully-depleted regime is presented. Starting from Poisson's equation, an implicit charge equation is derived approximately by a superposition principle with the exact channel potential and the charge equations in the depletion approximation. Also, a new explicit charge equation is derived from the implicit charge equation. The current equations without any charge-sheet approximation are based on the implicit and explicit charge control models, and both of them are valid for all the operation regions (linear, saturation, and subthreshold) and traces the transition between them without any fitting parameters. In the case of the SGMOSFETs with the fully-depleted condition, both of results simulated from the SGMOSFET models reproduce various 3D simulation results within 5% errors.

Compact capacitance modeling of a 3-terminal FET at zero drain–source voltage

The accuracy and continuity of the C– V characteristics of a transistor at V ds = 0 is one of the main benchmark tests a good compact model must pass. Singularities (in the form of 0/0 divisions) at V ds = 0 in compact capacitance models developed for several types of undoped 3-terminal devices, such as Double-Gate and Surrounding-Gate MOSFETs, have been corrected by means of techniques based on dealing individually with each of the targeted devices. Due to the lengthy calculations required for each of those particular cases, it will be useful to develop relationships between capacitances, with expressions easy to calculate, that can be applied to any type of undoped 3-terminal FET. We present compact modeling schemes valid for long-channel 3-terminal devices at V ds = 0 and we demonstrate suitable relationships between the different capacitances, deriving general analytic expressions for them in terms of the derivative of the drain charge sheet density with respect to the drain voltage; we also show how they can be calculated using the device charge control model.

Impact of laterally asymmetric channel and gate stack architecture on device performance of surrounding gate MOSFETs

AbstractA new device design laterally asymmetric channel gate stack (LACGAS) SGT is proposed, and its impact on device performance is examined. By using analytical modeling and numerical simulations, the novel features of this structure are studied, and it is demonstrated that LACGAS offers superior performance when compared with conventional devices. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 746–750, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25022

A carrier-based analytic drain current model incorporating velocity saturation for undoped surrounding-gate MOSFETs

A carrier-based analytic drain current model including the velocity saturation effect for the undoped surrounding-gate (SRG) MOSFETs is developed in this paper. Based on the previously ideal carrier-based drain current model, the Caughey–Thomas mobility model with an exponent factor n = 2 is applied and integrated into the analytic drain current model development. The validity of the presented model is confirmed by comparisons with three-dimensional (3D) TCAD device simulations for good agreements between the model prediction and numerical simulation on transfer/output characteristics and trans/output-conductance of the SRG MOSFETs are obtained in the whole operation regions from subthreshold to strong inversion and from linear to saturation regions. The symmetry property of the developed drain current model is guaranteed by the exponent factor n = 2 in the Caughey–Thomas model and also further tested, promoting the analog circuit design function of the proposed model.

A Review on Compact Modeling of Multiple-Gate MOSFETs

This paper reviews recent development on compact modeling of multiple-gate (MG) MOSFETs. Long-channel core models based on the analytical potential solutions of Poisson and current continuity equations for symmetric double-gate (DG) and surrounding-gate (SG) MOSFETs have been developed first. Highly accurate explicit solutions are subsequently developed to deal with the implicit algebraic equations of the models. By adding quantum mechanical effects and short-channel effects, as well as capacitance formulations, the core model for DG MOSFETs has been expanded into a full-blown compact model which has been calibrated to and validated by experimental FinFET hardware. With regard to the various other types of MG MOSFETs developed, the core models for DG and SG MOSFETs have been generalized to the less symmetric structures, including quadruple-gate (QG), triple-gate (TG), ?-gate, and ?-gate MOSFETs. Other research activities on multiple-gate MOSFETs are briefly summarized at the end.

2D Transconductance to Drain Current Ratio Modeling of Dual Material Surrounding Gate Nanoscale SOl MOSFETs

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

Sub-threshold behavior of long channel undoped cylindrical surrounding-gate MOSFETs

This paper reported the sub-threshold behavior of long channel undoped surrounding-gate (SRG) MOSFETs with respect to body radius. Based on a rigorous channel potential model presented in this work, the ideal room temperature subthreshold slope of 60 mV/dec can only be achieved when the silicon body radius is smaller than a critical value. With larger silicon body radius, SRG MOSFETs display a dual subthreshold slope of 60 mV/dec and 120 mV/dec. Based on the complex subthreshold characteristics, a new definition of threshold voltage together with an extraction method is adopted to investigate threshold voltage characteristics of undoped SRG MOSFETs in this paper.

A complete analytic surface potential-based core model for intrinsic nanowire surrounding-gate MOSFETs

An analytic surface potential-based non-charge-sheet core model for intrinsic nanowire surrounding-gate (SRG) MOSFETs is presented in this paper. Starting from the Poisson–Boltzmann equation in the cylindrical SRG MOSFETs, a surface potential equation is derived. Based on the exact surface potential solutions evaluated at the source and drain ends, a single set of the analytic drain current expression is obtained from the Pao–Sah's dual integral without the charge-sheet approximation. The analytical trans-capacitance model is also obtained from Ward–Dutton's charge partition method within the surface potential-based model framework. It is shown that the proposed drain current model and trans-capacitance model are valid for all operation regions, allowing the nanowire SRG MOSFET characteristics to be adequately described from the linear to saturation and from the sub-threshold to strong inversion region without any fitting-parameters. Moreover, the model prediction is verified by the three-dimensional numerical simulation.

Symmetric linearization method for double-gate and surrounding-gate MOSFET models

Symmetric linearization method is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFET. This leads to a core compact model of certain multiple-gate transistors that has the form almost identical to that used in a standard PSP MOSFET model. The accuracy of the proposed technique is verified by comparison with the exact results. The new core is compatible with the previous version of the double gate MOSFET model that has been found in agreement with the experimental data including short-channel effects and frequency response.

A surface potential-based non-charge-sheet core model for undoped surrounding-gate MOSFETs

A surface potential based non-charge-sheet core model for cylindrical undoped surrounding-gate (SRG) MOSFETs is presented. It is based on the exact surface potential solution of Poisson's equation and Pao–Sah's dual integral without the charge-sheet approximation, allowing the SRG-MOSFET characteristics to be adequately described by a single set of the analytic drain current equation in terms of the surface potential evaluated at the source and drain ends. It is valid for all operation regions and traces the transition from the linear to saturation and from the sub-threshold to strong inversion region without fitting-parameters, and verified by the 3-D numerical simulation.

Analytical and Numerical Study of the Impact of Halos on Surrounding-Gate MOSFETs

Halo doping profile is used in nanoscale surrounding-gate MOSFETs to suppress short channel effect and improve current driving capability. Analytical surface potential and threshold voltage models are derived based on the analytical solution of Poisson's equation for the fully depleted symmetric and asymmetric halo-doped MOSFETs. The validity of the analytical models is verified using 3D numerical simulation. The performance of the halo-doped MOSFETs are studied and compared with the uniformly doped surrounding-gate MOSFETs. It is shown that the halo-doped channel can suppress threshold voltage roll-off and drain-induced barrier lowering, and improve carrier transport efficiency. The asymmetric halo structure is better in suppressing hot carrier effect than the symmetric halo structure.

Charge-based model enhancement for undoped surrounding-gate MOSFETs

Charge-based and surface-potential-based models for undoped surrounding gate MOSFETs are compared from the aspect of their different accuracy. It has been identified that surface-potential-based models have superior accuracy near the threshold voltage. By including an additional charge density correction, the charge-based equations can be enhanced to achieve similar accuracy as the surface-potential-based models.

An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass

Threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective mass is calculated from the solution of 2D Schrödinger equation in elliptic coordinates. The solutions are of the Mathieu function type. It is shown that for some intermediate range of radius in silicon, several subbands need be taken into account to obtain accurate threshold voltage shifts. However, for small radius, only the lowest subband need be considered, and even anisotropic effective mass can be replaced by reduced isotropic effective mass, for which Bessel function is sufficient.

A charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped cylindrical surrounding-gate MOSFETs

This paper presents a charge-based compact model for predicting the current–voltage and capacitance–voltage characteristics of heavily doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. Starting from Poisson’s equation with fixed charge and inversion charge terms, a closed-form equation of inversion charge is obtained with the full-depletion approximation. Substituting this inversion charge expression into Pao-Sah’s dual integral, a drain current expression with concise form is derived. Based on the Ward-Dutton linear-charge-partition method and the current continuity principle, all trans-capacitances are obtained analytically. The developed model is valid in all operation regions from the sub-threshold to strong inversion and from the linear to the saturation region without any smooth function. The model predictions have been extensively compared with 3D numerical simulations and a good agreement is observed in most of the operation regions with a wide range of geometrical parameters.