Surface Passivation Technology Research Articles

N-Heterocyclic Carbene Based Nanolayer for Copper Film Oxidation Mitigation

The wide use of copper is limited by its rapid oxidation. Main oxidation mitigation approaches involve alloying or surface passivation technologies. However, surface alloying often modifies the physical properties of copper, while surface passivation is characterized by limited thermal and chemical stability. Herein, we demonstrate an electrochemical approach for surface-anchoring of an N-heterocyclic carbene (NHC) nanolayer on a copper electrode by electro-deposition of alkyne-functionalized imidazolium cations. Water reduction reaction generated a high concentration of hydroxide ions that induced deprotonation of imidazolium cations and self-assembly of NHCs on the copper electrode. In addition, alkyne group deprotonation enabled on-surface polymerization by coupling surface-anchored and solvated NHCs, which resulted in a 2 nm thick NHC-nanolayer. Copper film coated with a NHC-nanolayer demonstrated high oxidation resistance at elevated temperatures and under alkaline conditions.The ease of preparation and well-controlled growth process of electrochemically-induced NHC nanolayer make it an easily-applicable method for large-scale coating to provide thin and effective passivation layer for copper surfaces. Moreover, the electro-induced mechanism of NHC-nanolayer formation makes it possible to selectively deposit the protective layer on conducting copper wires without changing the optical properties of the entire device. These advantages make the presented technology highly suitable for applications that require high transparency, such as solar cells and electroluminescence devices.

Surface Cleaning and Passivation Technologies for the Fabrication of High-Efficiency Silicon Heterojunction Solar Cells.

Silicon heterojunction (SHJ) solar cells are increasingly attracting attention due to their low-temperature processing, lean steps, significant temperature coefficient, and their high bifacial capability. The high efficiency and thin wafer nature of SHJ solar cells make them ideal for use as high-efficiency solar cells. However, the complicated nature of the passivation layer and prior cleaning render a well-passivated surface difficult to achieve. In this study, developments and the classification of surface defect removal and passivation technologies are explored. Further, surface cleaning and passivation technologies of high-efficiency SHJ solar cells within the last five years are reviewed and summarized.

Low Thermal Budget Reconfigurable Fully Depleted Silicon on Insulator Field-Effect-Transistors With Embedded Boolean Logic

We report the low thermal budget reconfigurable fully depleted silicon on insulator (FDSOI) field-effect-transistors, focusing on the management of the fabrication thermal budget, toward three-dimensional integration and the further improvement of the circuit functionality. This is realized using atomic layer deposition tool-enabled O2/NH3 plasma surface passivation technology and long duration thermal procedure. Moreover, such front-gated FDSOI reconfigurable field effect transistors (RFETs) gain the embedded Boolean logic of “AND” and “NOR” in N and P-type modes, respectively. This strategy has the potential to be a key enabler for functional improvement in the nanoscale hyper-scaling era.

Addressing separation and edge passivation challenges for high efficiency shingle heterojunction solar cells

We are reporting the fabrication of high efficiency Silicon heterojunction shingle solar cells with very limited performance losses related to the cell separation. A clean and innovative separation process was elaborated and optimized, based on 45° rotated silicon brick and wafers fabrication, allowing the alignment of the preferential cleavage plan (110) with the solar cells bus bars. Hence, a simple but efficient mechanical crack propagation was sufficient to insure a proper shingles cell cut. The smooth resulting solar cell edges were found to be sensitive to surface passivation technologies. Aluminum oxide layers fabricated by atomic layer deposition were specifically developed so that their activation process is fully compatible with heterojunction low temperature constraints (typically less than 220°C). Interestingly, we showed that the annealing temperature alone was not sufficient to activate such layers; alternative forming gas annealing and/or light soaking treatments were thus successfully applied instead with very high passivation values measured on bare samples. Such layers were then deposited and activated on 45° wafer based cleaved heterojunction solar cells edges. Applied for example on heterojunction shingle cell configuration, we managed to recover up to 80% of the initial efficiency loss due to the separation, limiting the overall efficiency losses to less than 0.2% absolute. • (110) edge oriented Si wafers for mechanical separation of shingle cells. • Low temperature ALD AlOx layers with high passivation properties. • Light soaking and hydrogen rich atmosphere for low temperature activation. • New separation and passivation protocol strongly reduces efficiency cut losses.

The study of the passivation technology for bare HPGe detector working in LN2

The direct operation of bare high purity germanium (HPGe) in liquid nitrogen (LN2) is a desirable method for rare event detection. However, how to improve the long-term stability of the HPGe detectors in this working condition is still worth exploring. In this study, a method combining chemical treatment (methanol passivation) with thin film deposition (SiOx films passivation) has been applied to the HPGe detector intercontact surface. As a result, the leakage current of the bare detector stabilized at the level of 1 pA (applied voltage up to 3600 V, depletion voltage of 1800 V) while it had been immersed in LN2 for more than six months. It shows that the surface passivation technology raised by this work can reliably protect the HPGe detector from environmental impact, which is very helpful to obtaining a stable HPGe detector with ultra-low leakage current.

Ultrastable Anti-Acid "Shield" in Layered Silver Coordination Polymers.

Surface passivation technology provides noble-metal materials with limited chemical stability, especially under highly acidic condition. To design effective strategy to enhance stability of noble-metal particles, an understanding of their surface anticorrosion mechanism at the atomic level is desirable by using two-dimensional (2D) noble-metal coordination polymer (CP) as an ideal model for their interfacial region. With the protection of 2-thiobenzimidazole (TBI), we isolated two Ag-based 2D CPs, {Ag14 (TBI)12 X2 }n (S-X, where S denotes sheet and X=Cl or Br). These compounds exhibited excellent chemical stability upon immersion in various common solvents, boiling water, boiling ethanol, 10 % hydrogen peroxide, concentrated acid (12 M HCl), and concentrated alkali (19 M NaOH). Systematic characterization and DFT analyses demonstrate that the superior stability of S-X was attributed to the hydrophobic organic shell and dynamic proton buffer layer acting as a double protective "shield".

N-Heterocyclic Carbene Based Nanolayer for Copper Film Oxidation Mitigation.

The wide use of copper is limited by its rapid oxidation. Main oxidation mitigation approaches involve alloying or surface passivation technologies. However, surface alloying often modifies the physical properties of copper, while surface passivation is characterized by limited thermal and chemical stability. Herein, we demonstrate an electrochemical approach for surface‐anchoring of an N‐heterocyclic carbene (NHC) nanolayer on a copper electrode by electro‐deposition of alkyne‐functionalized imidazolium cations. Water reduction reaction generated a high concentration of hydroxide ions that induced deprotonation of imidazolium cations and self‐assembly of NHCs on the copper electrode. In addition, alkyne group deprotonation enabled on‐surface polymerization by coupling surface‐anchored and solvated NHCs, which resulted in a 2 nm thick NHC‐nanolayer. Copper film coated with a NHC‐nanolayer demonstrated high oxidation resistance at elevated temperatures and under alkaline conditions.

N‐Heterocyclic Carbene Based Nanolayer for Copper Film Oxidation Mitigation

AbstractThe wide use of copper is limited by its rapid oxidation. Main oxidation mitigation approaches involve alloying or surface passivation technologies. However, surface alloying often modifies the physical properties of copper, while surface passivation is characterized by limited thermal and chemical stability. Herein, we demonstrate an electrochemical approach for surface‐anchoring of an N‐heterocyclic carbene (NHC) nanolayer on a copper electrode by electro‐deposition of alkyne‐functionalized imidazolium cations. Water reduction reaction generated a high concentration of hydroxide ions that induced deprotonation of imidazolium cations and self‐assembly of NHCs on the copper electrode. In addition, alkyne group deprotonation enabled on‐surface polymerization by coupling surface‐anchored and solvated NHCs, which resulted in a 2 nm thick NHC‐nanolayer. Copper film coated with a NHC‐nanolayer demonstrated high oxidation resistance at elevated temperatures and under alkaline conditions.

Photovoltaic Device Application of a Hydroquinone-Modified Conductive Polymer and Dual-Functional Molecular Si Surface Passivation Technology.

In the last decades, the conductive polymer PEDOT:PSS has been introduced in Si-based hybrid solar cells, gaining noticeable research interest and being considered a promising candidate for next generation solar cells which can achieve both of low manufacturing cost and high power conversion efficiency. This study succeeded in improving the electrical conductivity of PEDOT:PSS to 937 S/cm through a simple process of adding hydroquinone (HQ) to the pristine PEDOT:PSS solution. The results also showed that the addition of HQ to PEDOT:PSS(HQ-PEDOT:PSS) could not only dramatically improve the conductivity but also well-sustain the work function characteristics of PEDOT:PSS by promoting the formation of more continuous conductive-PEDOT channels without removing the insulating PSS. In this report, we reveal that the application of the HQ-PEDOT:PSS to the Si/PEDOT:PSS HSC could significantly improve the short-circuit current and open-circuit voltage characteristics to increase the power conversion efficiency of the HSCs compared to the conventional approaches. Moreover, we also treated the Si surface with the organic monomer, benzoquinone (BQ) to (1) passivate the excess Si surface defect states and (2) to improve the properties of the Si/PEDOT:PSS interface. We show that BQ treatment is able to dramatically increase the minority carrier lifetime induced by effective chemical and field-effect passivation in addition to enhancing the wettability of the Si surface with the PEDOT:PSS solution. As a result, the power conversion efficiency was increased by 10.6% by introducing HQ and BQ into the fabrication process of the Si/PEDOT:PSS HSC.

Extraordinarily High Minority Charge Carrier Lifetime Observed in Crystalline Silicon

Recent progress in surface passivation technology and wafer pretreatment already resulted in significant improvements in the achievable minority charge carrier lifetime of crystalline silicon. Herein, this is further exemplified by studying the lifetime on lowly doped crystalline silicon wafers passivated by poly‐Si. To ensure credible lifetime measurements multiple measurement techniques are compared and good agreement between the investigated approaches is found. The resulting lifetime curves are analyzed in detail and the main limitation is very likely caused by silicon bulk recombination—most likely due to impurities. This analysis indicates that even very low impurity concentrations can be a limiting factor at the extraordinary high level of charge carrier lifetime observed in this study. Despite these limitations, lifetimes of 0.18 s on p‐type and 0.5 s on n‐type crystalline silicon wafers are measured, which to our knowledge exceed previously reported lifetimes. In both cases, these measured lifetimes correspond to an effective minority charge carrier diffusion length of ≈2.5 cm.

The impact of deposition and annealing temperature on the growth properties and surface passivation of silicon dioxide films obtained by atomic layer deposition

This paper studies the impact of deposition and annealing temperature on the growth properties and surface passivation of silicon dioxide (SiO2) films obtained by atomic layer deposition (ALD) using tris(dimethylamino)-silane (TDMAS) precursor. Increasing in deposition temperature from 200 to 350 °C alters the growth rate and refractive index significantly. The ALD-SiO2 films deposited at over 250 °C obtain excellent surface passivation after annealing at 650 °C, which could be explained by the synergistic effects of chemical and field-effect passivation caused by low interface defect states density (Dit) and high positive fixed charges density (Qf), respectively. Meanwhile, the effect of deposition temperature on surface passivation depends on the extent of TDMAS chemical adsorption and dissociation during ALD. X-ray photoelectron spectroscopy (XPS) shows low temperature as-deposited SiO2 films contain higher carbon impurities because of the remained dimethylamine groups. Regarding the impact of annealing temperature on surface passivation, secondary ion mass spectroscopy profiles and XPS results reveal that high-temperature annealing probably forms more hydrogen and oxygen vacancies at SiO2/Si interface, causing a decrease in Dit and an increase in positive Qf, respectively. This work provides a reference for applying ALD-SiO2 films to surface passivation technology of crystalline silicon solar cells.

Conformal Passivation of Multi-Channel GaN Power Transistors for Reduced Current Collapse

Multi-channel power devices, in which several AlGaN/GaN layers are stacked to achieve multiple two-dimensional electron gases (2DEGs), have recently led to a significant increase in the device conductivity while maintaining high breakdown voltage, resulting in excellent DC performances. However, their dynamic performance is yet to be demonstrated, especially due to the absence of an effective passivation technique for their 3D structure. Here, we present a surface passivation technology for multi-channel devices based on a conformal deposition of a thin SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interlayer followed by a low-pressure chemical vapor deposition (LPCVD) Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> layer around the multi-channel fins, which enables to effectively reduce the electron traps both at the AlGaN top surface and at the fin sidewalls. Such an approach led to a significant reduction of the dynamic on-resistance (RON) in multi-channel devices under large off-state voltages of 350 V and comparable dynamic performance with passivated single-channel reference devices. This work proves that, in addition to the excellent DC performance, the multi-channel technology can offer reduced current collapse, unveiling the potential of this platform for future power electronic applications.

Surface coordination layer passivates oxidation of copper.

Owing to its high thermal and electrical conductivities, its ductility and its overall non-toxicity1-3, copper is widely used in daily applications and in industry, particularly in anti-oxidation technologies. However, many widespread anti-oxidation techniques, such as alloying and electroplating1,2, often degrade some physical properties (for example, thermal and electrical conductivities and colour) and introduce harmful elements such as chromium and nickel. Although efforts have been made to develop surface passivation technologies using organic molecules, inorganic materials or carbon-based materials as oxidation inhibitors4-12, their large-scale application has had limited success. We have previously reported the solvothermal synthesis of highly air-stable copper nanosheets using formate as a reducing agent13. Here we report that a solvothermal treatment of copper in the presence of sodium formate leads to crystallographic reconstruction of the copper surface and formation of an ultrathin surface coordination layer. We reveal that the surface modification does not affect the electrical or thermal conductivities of the bulk copper, but introduces high oxidation resistance in air, salt spray and alkaline conditions. We also develop a rapid room-temperature electrochemical synthesis protocol, with the resulting materials demonstrating similarly strong passivation performance. We further improve the oxidation resistance of the copper surfaces by introducing alkanethiol ligands to coordinate with steps or defect sites that are not protected by the passivation layer. We demonstrate that the mild treatment conditions make this technology applicable to the preparation of air-stable copper materials in different forms, including foils, nanowires, nanoparticles and bulk pastes. We expect that the technology developed in this work will help to expand the industrial applications of copper.

Vacuum-Free, Room-Temperature Organic Passivation of Silicon: Toward Very Low Recombination of Micro-/Nanotextured Surface Structures.

Crystalline silicon (c-Si) solar cells remain dominant in the photovoltaic (PV) market because of their cost-effective advantages. However, the requirement for expensive vacuum equipment and the power-hungry thermal budget for surface passivation technology, which is one of the key enablers of the high performance of c-Si solar cells, impede further reductions of costs. Thus, the omission of the vacuum and high-temperature process without compromising the passivation effect is highly desirable due to cost concerns. Here, we demonstrate a vacuum-free, room-temperature organic Nafion thin-film passivation scheme with an effective minority carrier lifetime (τeff) exceeding 9 ms on an n-type c-Si wafer with a resistivity of 1-5 Ω·cm, corresponding to an implied open circuit voltage (i Voc) of 724 mV and upper-limit surface recombination velocity (SRV) of 1.46 cm/s, which is a level that is in line with the hydrogenated amorphous Si film-passivation scheme used in the current PV industry. We find that the Nafion film passivation of Si can be enhanced in an O2 atmosphere and that the Nafion/c-Si interface oxidation should be responsible for the passivation mechanism. This highly effective passivation is also achieved on various micro-/nanotextured Si surface structures from actual production, including a pyramidal surface and nanopore-pyramid hybrid structure with nanopores on the inclined plane of the pyramid. We develop an organic Nafion-passivated n-type back-junction Si solar cell to examine application in a real device. The open circuit voltage ( Voc) of the solar cell with the Nafion passivation layer achieves a clear improvement (30.8 mV) over those without the passivation layer, resulting in an increase (1.5%) in the power conversion efficiency. These results suggest the potential use of these organic electronics with current Si microelectronics and a new strategy for the development of vacuum-free, low-temperature Si-based PVs at low cost.

Ternary Self-Catalyzed GaAsP Nanowire Grown by Molecular Beam Epitaxy

III-V nanowires demonstrate controlled dimensions, high aspect ratio, high carrier mobility and light trapping ability, making them promising blocks for next generation electronic and photonic devices. GaAsP nanowire has been widely investigated for light-emitting diodes, solar cells due to its tunable bandgap. However, it is a very immature field and significant growth development need to be made for optimising their properties and further for a range of applications. In this paper, self-catalyzed GaAsP nanowires were grown on Si substrate without introducing contamination from metallic nanoparticles. Surface passivation technology was applied on nanowires to boosts their optical performance.

Effect of atomic layer deposition temperature on current conduction in Al2O3 films formed using H2O oxidant

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al2O3 films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al2O3 metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO2 capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al2O3 capacitors are found to outperform the SiO2 capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al2O3 interface. The Al2O3 electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al2O3 capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al2O3. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al2O3 capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al2O3/underlying SiO2 interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al2O3 films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al2O3 films.

AC-Capacitance Techniques for Interface Trap Analysis in GaN-Based Buried-Channel MIS-HEMTs

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth.

Photonic light trapping and electrical transport in thin-film silicon solar cells

Efficient solar cells require both strong absorption and effective collection of photogenerated carriers. With these requirements in mind, the absorber layer should be optically thick but electrically thin, to benefit from reduced bulk transport losses. It is therefore important to clarify whether thin-film silicon solar cells can compete with conventional wafer-based devices. In this paper we present a theoretical study of optical and electro-optical performance of thin-film crystalline silicon (c-Si) solar cells implementing light-trapping schemes. First, we use Rigorous Coupled-Wave Analysis (RCWA) to assess the light-trapping capabilities of a number of photonic structures characterized by different levels of disorder. Then, we present two approaches for electro-optical modeling of textured solar cells: a simplified analytic model and a numerical approach that combines RCWA and the Finite-Element Method. We consider both bulk and surface recombination in solar cells with the absorber thickness ranging from 1 to 100μm. Our results predict that with state-of-the-art material quality of thin c-Si layers, the optimal absorber thickness is of the order of tens of microns. Furthermore, we show that thin-film solar cells with realistic material parameters can outperform bulk ones, provided surface recombination is below a critical value, which is compatible with present-day surface passivation technologies. This gives prospects for high-efficiency solar cells with much smaller c-Si thickness than in present wafer-based ones.

Silicon Surface Passivation Technology for Germanium-Tin P-Channel MOSFETs: Suppression of Germanium and Tin Segregation for Mobility Enhancement

We report a two-step silicon (Si) surface passivation technology for germanium-tin (Ge1-xSnx) p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs), featuring an initial low temperature atomic-layer-epitaxy or passivation step to suppress the segregation of subsurface germanium (Ge) and tin (Sn) atoms into the first monolayer of the ultrathin Si passivation layer. Evidence of reduced Ge and Sn segregation into the ultrathin Si passivation layer is provided by angle-resolved X-ray photoelectron spectroscopy (ARXPS) measurement. As compared to a Si passivation process performed at a higher temperature (370°C), the two-step Si passivation process gives ∼13% higher drive current in Ge0.94Sn0.06 pMOSFETs. It also achieved a high effective hole mobility μeff of 472 cm2/V·s at inversion carrier density Ninv of 1 × 1013 cm−2. The two-step Si surface passivation technology enables the formation of high-quality gate stack on Ge1-xSnx surface channel for high performance logic applications.

Industrial high performance crystalline silicon solar cells and modules based on rear surface passivation technology

Abstract Stimulated by the extreme market conditions, the increase in performance and the reduction of manufacturing costs of standard crystalline silicon solar cells and modules have been quite significant in the last years. This progress was achieved mainly by process and material improvements avoiding additional process complexity. As todays cells are predominantly limited by optical and recombination losses at the rear surface, dielectric rear surface passivation represents an obvious approach to overcome the limitations. In recent years several concepts have been developed to implement dielectric rear side passivation into industrial-scale mass production. In this paper a short review is given about the evolution of dielectric rear side passivation technologies as well as on state-of-the-art cell and module results. Simple and cost effective cell and module designs utilizing standard as well as innovative manufacturing technologies are presented. Furthermore, it is shown that for all major steps multiple process options are available to further reduce the manufacturing costs. Using an optimized emitter and screen-printed metallization on commercially available 156 mm×156 mm p-type Czochralski-grown crystalline silicon wafers best cell efficiencies of 19.9% without dielectric rear surface passivation and 21.0% with dielectric rear surface passivation are demonstrated. Replacing the screen-printed front contacts by electroplated nickel–copper contacts record efficiencies of up to 21.3% are reached. By optimizing the module design and materials to reduce the resistive and optical losses, a peak module power of up to 306 W and 19.5% aperture area efficiency are achieved.