Reduced Supply Voltage Research Articles

(Invited) Recent Progress in Vertical Si/III-V Tunnel FETs: From Fundamentals to Current-Boosting Technology

Inherent issue for low-power LSI is lowering supply voltage of transistor while beating physical limit of subthreshold slope (SS = 2.3 k BT/q = 60 mV/dec) [1]. Otherwise, this limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented [2-4]. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. The tunneling transistors are most promising switching devices because of possibility for lower SS than 60 mV/dec. and better compatibility with conventional integration process. However, there are some difficulties in decreasing SS while increasing tunneling current as high as that of conventional FETs. Recently, we reported on new tunnel junction based on III-V/Si interface [4,5] which is formed by selective-area growth of III-V nanowires (NWs) on Si [6-8], and demonstrated vertical TFETs with steeper SS [9,10]. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials. Here we report on recent progress in the vertical TFETs using III-V NW/Si heterojunction and discuss some current-boosting technology such as strain and other technique. As for integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping [4,5]. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [8]. Sn was used for n-type dopant, and Zn-pulse doping technique [10] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-ling in this case). The vertical TFET with a single vertically aligned n+-InGaAs/Zn-pulse doped InGaAs axial NW on a p-Si substrate was firstly demonstrated. The device process was reported elsewhere [4,5]. The channel length was 200 nm. In the TFET using the bare InGaAs NW, the tunneling current under revise bias was modulated by gate bias with SS of 80 – 90 mV/dec, and the ION was 2.7 nA/µm at VDS = 0.50 V. With decreasing VDS, the SS become steeper than 60 mV/dec. at low drain current region. The minimum SS was around 50 mV/dec. at VDS= 0.10 V. As for current boosting technology, channel length scaling was characterized [5]. The ION was 100 times enhanced with decreasing the channel length to 50 nm, and the SS decreased to 30 mV/dec. at VDS = 0.10 V. This indicated that the drain end should be close to the tunnel junction width. Next, strain effect was characterized by using InGaAs/InP core-shell nanowire structure. Switching behavior with a SS of 42 mV/dec was obtained under reverse bias direction. This switching characterization appeared at as low as VDS of 10 mV. The SS of the TFET exhibits steeper SS behavior under various VDS. The ION for InGaAs/InP core-shell NW/Si TFET was 10 times higher than that of the bare InGaAs NW/Si TFET. The benefit of InP shell layer is improvement of SS and enhancement of ION. The InP shell layer act as passivation effect on the semiconductor/oxide interface. TEM analysis revealed the large compressive strain was induced at the near InGaAs NW/Si, which ascribes that the uniaxial compressive strain decrease effective band gap of InGaAs/Si while enhancing tunneling probability. Reduction in effective band gap of tunnel junction can partly enhance the tunneling current, but the tunneling leakage at source/channel region was increased degrading SS. Thus, further additional technology to enhance the tunneling current will be discussed.

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM

As the technology node scales down, the spin-transfer-torque random access memory (STT-RAM) has been considered as a promising memory solution owing to its scalability. However, the increased process variation and the reduced supply voltage lead to degradation in the sensing yield (SY) as well as an increase in the read disturbance probability. Temperature variation further aggravates this phenomenon. Thus, achieving a target SY with a lower sensing current in all process, voltage, and temperature (PVT) corners has become an important issue in a deep-submicrometer technology node. In this paper, we propose a corner-aware dynamic gate voltage scheme to achieve constant-current sensing, regardless of the PVT variations. By adopting this scheme, the state-of-the-art sensing circuits (SCs) can significantly reduce the sensing current, while achieving the target read yield. The Monte Carlo HSPICE simulation results using industry-compatible 45-nm model parameters show that the offset-canceling dual-stage SC that uses the proposed scheme satisfies a target SY of six-sigma (96.34% for 32 Mb) with two times lower sensing current and two times lower read energy compared with that using a fixed gate voltage.

(Invited) UTBB FDSOI PMOSFETs Including Strained SiGe Channels at the 14nm Technology Node and Beyond

The 28 nm Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology is in production [4]. This technology addresses both high performance and low power / low voltage applications. Indeed, a 28 nm FDSOI Processor (CPU) has been demonstrated to run at 3 GHz for a 1.3 V supply voltage (Vdd), 1 GHz for 0.6 V, still 300 MHz at 0.5 V [1]. This latter result evidences the high potential of FDSOI for Low Voltage operation, required for the next handheld, mobile or Internet-of-Things markets. The 14nm FDSOI technology extends this offer to even more performance (+50% frequency at a given dissipated power), with a 100mV supply voltage reduction [5]. For the 14nm FDSOI, we have integrated SiGe channel, which enables to achieve high biaxial compressive stress due to the lattice mismatch between Silicon and Germanium. The compressive stress enhance the hole mobility, and in turn pMOSFETs performance. In such an approach, one of the main challenges is to conserve the strain during the CMOS integration. Especially, it is well known that the patterning of SiGe leads to partial relaxation close to the active edges. This relaxation affects especially the level of stress in the channel when the dimensions of the active are small. The stress configuration becomes thus strongly layout-dependent. We have physically and electrically characterized the strain-induced layout effects in SiGe pMOSFETs built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). This layout effect is reproduced by an accurate physics-based electrical model, which enable us to predict the device and design performance for various technological configurations: germanium concentration in the channel, isolation and channel process integration. In order to mitigate the impacts of the SiGe channel relaxation, we have studied two kinds of solutions. First, technological solutions are possible, leading to +21% effective current increase in short transistor at Lg=20nm gate length and in turn -15% delay reduction for ring-oscillator of 1-gate finger inverters. Secondly, we demonstrate the benefits induced by smart design layouts, enabled by process integration goodies and some layout constructs. Especially, a continuous-RX design, which consists in a long active line configuration, optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage [10]. This demonstrates the interest of process/design co-optimization of strain-induced layout effects. For next UTBB-FDSOI nodes below 14nm, both the electrostatics and the carrier mobility must be improved. For the hole mobility, one may think about changing the crystalline orientation of the channel and using (110)-oriented substrates. However, in terms of electronic transport, the long channel carrier mobility is no longer the most relevant electrical parameter. One should pay a great attention to i) the strain compatibility and ii) the evolution of the apparent mobility with the gate length and width. Taking them into account, for pMOSFETs, SiGe channel + SiGeB source/drain + compressive contact etch stop layers in the (100) <110> direction is the best combination. For nMOSFETs, different technological solutions have been assessed, especially based on strain memorization techniques [6-7]. Strain-SOI substrates (sSOI) is another option, which brings enough performance boost to ensure a one-node scaling (+20-30% performance increase for nMOSFETs due to tensile strain, even for narrow active regions) [8]. Finally, the gate-last integration on planar FDSOI could be another strain booster because it leverages not only a low thermal budget for EOT and a threshold voltage optimization, but also a strain improvement during the final gate formation [9].

Negative capacitance transistors with monolayer black phosphorus

AbstractQuantum transport properties of negative capacitance transistors (NC-FETs) with monolayer black phosphorus (ML-BP) are theoretically studied. Our calculations show that atomistic thin ML-BP can enhance the amplification effect of the ferroelectric layer, and subthreshold swing is effectively reduced to 27 mV per decade in ML-BP NC-FETs. Device performance can be further improved by increasing the thickness of ferroelectric layer and using thinner or high-k insulate layer. Due to the temperature dependence of ferroelectric layer ML-BP NC-FETs have higher on-state current at low temperature, which is different from that of MOSFETs. By considering the metal–ferroelectric interface layer, our calculations show that the device performance is degraded by the interface. Compared with the International Technology Roadmap (ITRS) 2013 requirements, ML-BP NC-FETs can fulfil the ITRS requirements for high-performance logic with a reduced supply voltage. The new device can achieve very low power delay product per device width at VD=0.3 V, which is just 44% of that in ML-BP FETs.

Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling

Dynamic Voltage and Frequency Scaling is the most commonly used power managment techinique in modern processors. However, the ability of an individual chip to operate under reduced supply voltage can no longer be predetermined at the design stage and may even change over time. This paper presents Cyclic Power-Gating (CPG), a novel power management strategy where the power consumption of a core can be finely controlled without scaling the supply voltage. CPG builds on state-retentive power-gating which allows the power supply to a core to be switched off and on again at high speed (tens of clock cycles) with minimal disruption to running programs. The power-gating is cyclic, by altering the ratio of time spent powered-on and off in each power-gating period the effective operating frequency and power consumption of a core can be controlled. The overheads in delay and power consumption of CPG for an out-of-order core in a 14 nm technology are accurately modelled and compared to the performance and power consumption of Voltage/Frequency pairs in the same technology. The proposed power gating method reduces average power consumption by 4 percent over voltage and frequency scaling with only a 2 percent degradation in performance.

A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm

We propose a new transmitter architecture for ultra-low power radios in which the most energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS transistors. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its startup margin. It also reduces 1/f noise and supply pushing, thus allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during a direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency at low voltage. The transmitter is realized in 28 nm digital CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy mode.

Design of Cascaded Common Source Low Noise Amplifier for S-Band using Transconductance Feedback

Background/Objectives: Now-a-days advancements in CMOS technology increase the demand on transceiver design in the aspect of gain, linearity, power, re-configurability and cost-effectiveness. The performance of RF frontend of transceiver system using MOS device are excellent and found to be the par of 3-5 semiconductor technology. Methods/Statistical Analysis: The first component present in transceiver design is Low Noise Amplifier (LNA) which requires high gain, low noise, better input-output matching, low power, good linearity and stability. Trade off between these performances is more complex when transistors operate at reduced supply voltage and reduced power consumption. So many researchers focus to modify the existing topology by adding active/passive feedback elements and/or using current re-use inductors 2,3. But the latter, suffer from large power consumption. Moreover LNA using cascode configuration offers good gain with low power but the circuit has the limitation of output voltage swing 4. So the proposed work focuses on the design of LNA using transconductance feedback in Common Source (CS) configuration circuits. Findings: At RF frequencies, distributed parasitic of the device dominates thus altering the input-output matching characteristics which degrades gain, noise figure and stability of Low Noise Amplifier. So design of multistage LNA with feedback techniques is necessary to increase the gain. The transconductance feedback used in the design of LNA suits well for increase of gain provided if it is properly designed to ensure stability. The proposed work involves the design of MOS based low noise amplifier using single stage and cascaded Common Source (CS) configuration in S-band. By using the transconductance feedback in CS amplifier, the voltage gain is boosted. Using the extracted small signal equivalents, single stage and cascaded CS amplifier with the transconductance feedback are designed and analyzed. Importance of device parasitic like gate to source capacitance, gate to drain capacitance and the output resistance influence the loop gain. This is brought in the design and emphasizes on the proper utilization of these parasitic in LNA design with transconductance feedback. Using a standard 90 nm CMOS process, LNAs have been demonstrated for 2-GHz frequency (S-band) applications. Operated at a supply voltage of 0.6 V, the gain and noise figure of single stage CS LNA with transconductance feedback are observed to be 17.9 dB and 2.1 dB respectively. It is noted that nearly 17% gain improvement has been achieved with excellent input reflection coefficient of -54.8 dB and low power consumption of 2.92 mW. Similarly, for a cascaded CS amplifier when operated at 0.6V, it is observed that the gain and noise figure are found to be 13.6 dB and 2.38 dB respectively. It is noted that nearly 6.25% increase in gain is achieved with appealing reverse gain of -52. 8 dB when compared to cascaded CS circuit without transconductance feedback. Higher reverse gain ensures the stability of the designed amplifier. Applications: The proposed work is needed in the design of transceivers working at S-band (2 GHz - 8 GHz). Few noticeable applications are: Communication satellites (NASA), weather radar systems, microwave ovens and optical communication which require low power modules. Improvements: This work can be further extended to reconfigure the input matching network so that UWB bandwidth is covered.

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM

Due to the increased process variation and reduced supply voltage in deep submicrometer technology nodes, an offset-tolerant sensing scheme has become essential. However, most offset-tolerant sensing schemes suffer from inherent performance degradation owing to multiple-stage sensing. In this paper, a dual $V_{\mathrm {ref}}$ sensing scheme (DVSS) that selectively uses an optimal $V_{\rm {ref}}$ between $V_{\rm {ref+}}$ and $V_{\rm {ref-}}$ is proposed. This scheme is tolerant to process variations, and can be used as a spin-transfer-torque random access memory. Because of no additional sensing stage, the offset-tolerant sensing is achieved without sacrificing the performance. The optimal $V_{\rm {ref}}$ is selected after fabrication, and the calibrated switch control bit, which contains $V_{{\rm {ref}}}$ selection information, is stored permanently in an on-chip nonvolatile latch. Monte Carlo HSPICE simulation results, using an industry-compatible 45-nm model parameters, show that the proposed DVSS achieves a read yield of 98.24% for 32 Mb (6.1 sigma) with $2\times $ faster sensing speed and $1.5\times $ lower read energy per bit compared with the state-of-the-art offset-tolerant sensing scheme.

Analysis of 7/8-nm Bulk-Si FinFET Technologies for 6T-SRAM Scaling

The benefits of a super-steep retrograde (SSR) fin doping profile, which can be achieved using the oxygen insertion technology, are quantified via 3-D technology computer-aided design simulations for the 7/8-nm bulk-Si FinFET technology targeting low-power applications. A calibrated compact model is then used to estimate the six-transistor static RAM cell performance and yield. The SSR FinFET technology is projected to provide for up to 100 mV reduction in minimum cell supply voltage, to facilitate voltage scaling to below 0.50 V.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

Effect of supply voltage and body-biasing on single-event transient pulse quenching in bulk fin field-effect-transistor process**Project supported by the National Natural Science Foundation of China (Grant Nos. 61376109, 61434007, and 61176030).

Charge sharing is becoming an important topic as the feature size scales down in fin field-effect-transistor (FinFET) technology. However, the studies of charge sharing induced single-event transient (SET) pulse quenching with bulk FinFET are reported seldomly. Using three-dimensional technology computer aided design (3DTCAD) mixed-mode simulations, the effects of supply voltage and body-biasing on SET pulse quenching are investigated for the first time in bulk FinFET process. Research results indicate that due to an enhanced charge sharing effect, the propagating SET pulse width decreases with reducing supply voltage. Moreover, compared with reverse body-biasing (RBB), the circuit with forward body-biasing (FBB) is vulnerable to charge sharing and can effectively mitigate the propagating SET pulse width up to 53% at least. This can provide guidance for radiation-hardened bulk FinFET technology especially in low power and high performance applications.

Enabling New Computation Paradigms with HyperFET - An Emerging Device

High power consumption has significantly increased the cooling cost in high-performance computation stations and limited the operation time in portable systems powered by batteries. Traditional power reduction mechanisms have limited traction in the post-Dennard Scaling landscape. Emerging research on new computation devices and associated architectures has shown three trends with the potential to greatly mitigate current power limitations. The first is to employ steep-slope transistors to enable fundamentally more efficient operation at reduced supply voltage in conventional Boolean logic, reducing dynamic power. The second is to employ brain-inspired computation paradigms, directly embodying computation mechanisms inspired by the brains, which have shown potential in extremely efficient, if approximate, processing with silicon-neuron networks. The third is “let physics do the computation”, which focuses on using the intrinsic operation mechanism of devices (such as coupled oscillators) to do the approximate computation, instead of building complex circuits to carry out the same function. This paper first describes these three trends, and then proposes the use of the hybrid-phase-transition-FET (Hyper-FET), a device that could be configured as a steep-slope transistor, a spiking neuron cell, or an oscillator, as the device of choice for carrying these three trends forward. We discuss how a single class of device can be configured for these multiple use cases, and provide in-depth examination and analysis for a case study of building coupled-oscillator systems using Hyper-FETs for image processing. Performance benchmarking highlights the potential of significantly higher energy efficiency than dedicated CMOS accelerators at the same technology node.

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30 × on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage.

Design of Low Power Current Mode Square-Root Circuit

Analog circuits have been viewed as a voltage dominated type of signal processing. With the advent of CMOS technology, shrinking feature size, and reduction of supply voltage a new class of circuits developed: currentmode circuits. Among current-mode circuits “Translinear circuits” is one of the important and emerging research interests for low power analog designers. It is the practical means of implementing nonlinear signal processing functions. The performance of analog circuits strongly depends upon techniques used to exploit the characteristics of the transistors. In this paper, using exponential current-voltage relationship of MOS transistor when biased in subthreshold-mode, a square-root circuit is proposed. The circuit simulations were carried on TSMC 0.18 micrometer technology using ELDO Simulator.

A low-power 12-bit SAR ADC for remote pressure measurement

A 12-bit low power successive approximation ADC has been designed and fabricated in 0.35 µm, poly---poly capacitor AMS technology. The SAR ADC is targeted for bridge type pressure sensor in wireless sensor node applications. An improved cascaded inverter based comparator is used for its lower power consumption at reduced supply voltage of 1.3 V. A modified SAR digital circuit has been incorporated to accommodate a higher input range of 1.8 V for the ADC . For a given noise floor, the higher input range of ADC ensures enhanced SNR performance relaxing the constraint on sensor interface circuit preceding to the ADC. Also a novel switching scheme is used in the feedback of comparator to reduce the charge injection induced offset without sacrificing the useful bandwidth of ADC. The inverter based comparator consumes 2 µW of power while operating at a speed of 1.6 MHz. The comparator does not make use of any offset cancellation techniques. By suitably choosing the capacitor array of inherent DAC, the calibration techniques have been avoided for the ADC. The ADC achieves an effective number of bits of 10.01 while consuming 6.69 µW at a conversion speed of 100 KHz. The FOM of the whole ADC is found to be 64.8 fJ/conversion-step. The active area occupied by the ADC is 0.170625 mm2 (375 µm × 455 µm).

Minimum energy consumption for rate monotonic scheduled tasks

Limited battery power is a typical constraint in stand-alone embedded systems. One way to extend the battery lifetime is by reducing CPU power consumption. Because of the quadratic relationship between power consumption in CMOS circuits and CPU voltage, power reduction can be obtained by scaling down supply voltage, or dynamic voltage scaling. However, reducing supply voltage slows down CPU speed since supply voltage has a proportional relationship with CPU frequency. On the other hand, in any real-time embedded environment (especially hard real-time), timing constraints are critical. In this paper, we focus on dynamic energy reduction of tasks scheduled by rate monotonic (RM) algorithm in a hard real-time embedded environment. The RM algorithm preemptively schedules any set of periodic tasks by assigning higher priorities to frequent tasks. For any periodic task set that satisfies the CPU utilization bound, we determine the provably optimal scaling of the worst-case execution time of each task that consumes minimum dynamic energy while satisfying the utilization bound. As RM algorithm is widely used, we expect this work can lead to better energy reduction management and expectations.

Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

This paper discusses the ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed. As a prototype, a 0.5 V, 420-MS/s, and 7-bit, flash ADC is developed using a 90-nm CMOS technology to demonstrate the validity of ULV operation. To overcome the challenges associated with a reduced supply voltage, a double-tail latched comparator with a variable capacitance calibration technique using metal–oxide–metal capacitors is implemented. An all-digital time-domain delay interpolation technique further enhances the resolution with very little additional power consumption. Using two-way time-interleaving, the prototype ADC achieves an effective number of bits (ENOB) of 5.5 bits while operating at 420 MS/s consuming a total power of 4.1 mW. The lowest measured FoM is the 195 fJ/conv.-step during single-channel operation at 210 MS/s, which results in an extremely low FD product of 0.93 pJ $\times $ ns/conv.-step.

Fully printed flexible audio system on the basis of low‐voltage polymeric organic field effect transistors with three layer dielectric

ABSTRACTFully mass printed, flexible and truly polymeric organic field effect transistors consisting of a three layer dielectric made of CYTOP (low‐k), PVA (intermediate) and P(VDF‐TrFE‐CTFE)(high‐k) are introduced. Gravure‐, flexo‐and screen printing were selected as highly productive manufacturing technologies. These OFETs work at strongly reduced voltages and show high field effect mobility (µ = 0.2 cm2/Vs) and remarkable good bias stress stability at very high current density (50 µA/mm). Fully printed OFETs are used for the realization of ring oscillators working in the kHz regime at reduced supply voltage (10 V). In combination with printed fully polymeric piezoelectric loudspeakers, this work shows for the first time fully printed flexible audio systems. © 2015 Wiley Periodicals, Inc. J. Polym. Sci., Part B: Polym. Phys. 2015, 53, 1409–1415

(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions

A main goal of future electronic circuits is lower huge power consumption of LSIs while enhancing the chip performance. The Si-CMOS technologies are expected to change their gate-architecture, channel material, and transport mechanism to overcome the apparently-paradoxical demands which is owing to the inherent issues in miniaturization of Si MOSFETs. Enhanced short-channel effect and leakage current is emerged problem in further scaling of the transistor size. To avoid these issues, the gate structure have already changed into fin architecture [1] and will shifted to gate-all-around (GAA) [2] or surrounding-gate structure [3]. As for channel materials, III-V and Ge are promising alternative channels [4,5] because of higher carrier mobility and low electron/hole effective mass achieving higher ON-state current under lower bias. Since these materials tend to exhibit slightly high leakage current due to tunneling leakage, multi-gate architecture for these channel would necessary for decreasing leakage current. Furthermore, the inherent mobility mismatch between the III-V and Ge will be bottleneck in device-integration scheme to match current density. In near future, the III-V channel has no other choice except for vertical channel architecture to avoid the issue. In this regard, a co-integration technique of vertical III-V channel with p-channel Ge will be required for Si-CMOS. Final target is beating physical limit of conventional MOSFET especially subthreshold slope (SS) due to carrier thermal diffusion (SS = 2.3 k BT/q = 60 mV/dec). This limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channel are applied. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs [6] have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. These distinct features should be mutually addressed as extended CMOS technologies. In this regard, the selective-area epitaxy of III-Vs on Si will play an important role as integration technique of vertical III-V channels on Si and Ge, and the excellent III-V/Si heterojunction can assist to connect these challenges smoothly. In this paper, we review recent advances in direct integration of vertical III-V nanowire (NW)-channel on Si and FET application such as vertical III-V NW surrounding-gate transistors (SGTs) and tunneling FET (TFETs) using III-V NW/Si heterojunctions. In addition to the high-performance vertical FET application using the III-V nanowire-channel on Si, the III-V/Si heterojunction, which is formed underneath the small footprint of the III-V nanowire, is a promising junction for the use of steep-SS switches because this heterojunction shows preudo-staggered Type-II band discontinuity in the case of the n-III-V nanowire/p+ -Si heterojunctions. Under the reverse bias condition, a large Zener current depending on the carrier concentration of p-Si occurs, indicating that this current is modulated by the gate bias. Once the Fermi level is laid in the valence band in p-Si with a high carrier concentration, band-to-band tunneling appears under the forward bias. In case of a vertical steep-SS switch using the III-V nanowire/Si heterojunction, controlling the series resistance is important to achieve a steeper SS (< 60 mV/dec) because the SS is the function of VG and VDS [7]. This means a large electrical field should be induced at the heterojunction or channel region under a lower VG and VDS. In this regard, reducing the diameter of the heterojunction to avoid the trap-assisted tunneling process via defect level and forming an intrinsic layer are important for obtaining steep SS property. The device using an InAs nanowire (30 nm in diameter)/Si heterojunction demonstrated a steep SS (minimum SS = 12 mV/dec) at room temperature [7, 8]. [1]. I. Ferain et al., Nature 479 (2011) 310. [2]. J. J. Gu et al., IEEE IEDM Tech. Dig. 769 (2011). [3]. H. Takato et al., IEEE TED 38 (1991) 573. [4]. J. A. del Alamo, Nature 479 (2011) 317. [5]. H. Riel et al., MRS Bulletin 39 (2014) 668. [6]. A. M. Ionescu et al., Nature 479 (2011) 329. [7]. K. Tomioka et al., VLSI Symp. Tech. Dig. (2012) 47 [8]. K. Tomioka et al., Nano Lett. 13 (2013) 5822.

Foreword Special Issue on Transistors With Steep Subthreshold Swing for Low-Power Electronics

The increasing power consumption of integrated circuits is today the main impediment to the density scaling of integrated circuit technology. The reduction of supply voltage is the most effective way to reduce power; however, using modern transistors voltage reduction is traded against reduced speed or limited by a rising off-state leakage, neither of which is desirable. A better tradeoff can be achieved if the fundamental current control mechanism provides a steep turn-on characteristic. Steep means better than 60 mV/decade at room temperature, the limit obtained by barrier lowering in a bipolar transistor or metal oxide semiconductor field effect transistor (MOSFET) when the current is dominated by the thermionic emission of carriers above the energy barrier in the base or channel region.