Reduced Supply Voltage Research Articles

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

TMD material investigation for a low hysteresis vdW NCFET logic transistor

Boltzmann limit is inevitable in conventional MOSFETs, which prevent them to be used for low-power applications. Research in device physics can address this problem by selection of proper materials satisfying our requirements. Recently, 2D transition metal di-chalcogenide (TMD) materials are gaining interest because they help alleviate short-channel effects and DIBL problems. The TMD materials are composed by covalently bonded weak van der Waals (vdW) interaction and can be realized as hetero structures with 2D ferro-electric material CuInP2S6 at the gate stack. This paper demonstrates a vdW negative capacitance field effect transistor (NCFET) structure in TCAD and the design was validated for voltage-current Characteristics. Parametric analysis shows MoS2 with phenomenal on/off ratio, narrow hysteresis than the counterparts. Simulation shows that MoS2 vdW NCFET has a high transconductance of 2.36 µS µm−1. A steep slope of 28.54 mV dec−1 is seen in MoS2 vdW NCFET which promises the performance of logic applications at a reduced supply voltage.

Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC

In order to compensate for the non-linearity of an electronic device, an exponentiation conversion circuit that can change the power exponent to any value has been proposed. The exponentiation conversion circuit multiplies the logarithmically converted input signal by a power exponent value to perform exponential conversion. As a result, we can obtain the power function characteristic of a power exponent value. This circuit is a small-scale circuit that utilizes the exponential characteristics of the MOSFET subthreshold region. In a conventional circuit, expansion of the signal dynamic range and reduction of the power supply voltage have been an issue. In this paper, it was confirmed by simulation that the signal dynamic range has expanded by optimizing the current density of MOSFETs. In addition, the linearity of the multiplying circuit was improved by feedback produced by the operational amplifier circuits. We proposed reducing its power supply voltage from 6.0 to 3.3 V by a new multiplying circuit that can eliminate the restriction of maximum voltage gain. Our circuit expands its signal dynamic range from 17.5 to 42.7 dB in condition of the power exponent value from 0.50 to 2.0.

On the design of an ultra-low-power ultra-low-voltage inverter-based OTA

In this paper, an inverter-based Operational Transconductance Amplifier (OTA) is introduced. This design is tailored for applications demanding ultra-low power consumption and exceptionally reduced supply voltage. In addition to the utilization of composite transistors and forward-body-biasing, a feedforward path is also employed to enhance the voltage gain. The OTA is simulated in a 65 nm CMOS technology with a supply voltage of 0.3 V. Simulation results show a voltage gain of 42.57 dB and a power consumption of 1.06 nW.

Power Consumption Minimization of a Low-Cost IoT Data Logger for Photovoltaic System

This paper introduces an innovative IoT-based data logger for photovoltaic (PV) system monitoring, emphasizing low power consumption and affordability. The system comprises a PV panel, a charging controller, and a backup battery, focusing on monitoring their voltages and currents through a network of voltage and current sensors. Data is stored on an SD card and displayed in real-time on a web server. The FireBeetle 2 ESP32-E microcontroller, chosen for its efficient deep-sleep mode power management, is central to the data logger's design. This study employs several low-power strategies, notably reducing supply voltage and CPU frequency to decrease power consumption significantly. A data buffering mechanism stores sensor readings in the microcontroller's flash memory, transferring them to the SD card hourly to balance power efficiency and data security. Wi-Fi connection intervals are optimized to 45 seconds, balancing power use and system monitoring frequency. The data logger averages a power consumption of 122.78 mW and demonstrates its efficacy against the commercial DI-145 model. Priced at C$ 55.05, the system is both cost-effective and scalable, capable of monitoring multiple PV panels and batteries, reducing per-unit costs. The study underscores the successful integration of affordability, low-power operation, and efficient monitoring in a PV system data logger, showcasing its potential in future renewable energy research.

Analytical modelling of ultra‐small group delay variation of ultra‐broadband RF power amplifier using NSGA‐II algorithm

AbstractThis paper proposes a ± 9.4 ps ultra‐small group delay (GD) variation of fully integrated 65 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) over 6.5–17 GHz broadband for wireless application. The proposed CMOS PA is realised by using broadband stage, RLC inter‐stage and power stage topologies. The non‐dominated sorting genetic algorithm (NSGA‐II) is employed for PA parameter optimisation to ensure a small GD variation of ±9.4 ps over broadband with an excellent small signal gain flatness of 23.65 ± 1.85 for 6.5–17 GHz. The small GD variation of ±9.4 ps and ± 11.05 ps are attained under two cases of DC supply voltages of 2.4/1.2 V and 1.2/1.2 V, respectively. To the best of author's knowledge, the achieved GD variations are lowest among all CMOS PAs as reported so far. In addition, an analytical modelling of GD is derived to validating the minimum GD variation using zero‐pole compensation. With supply voltages of 2.4/1.2 V at 6.5 GHz, the large signal power gain, Psat and OP1dB are 26 dB, 19.3 dBm and 17.94 dBm, respectively, while peak power added efficiency (PAE) is 38.196%. At reduced supply voltages of 1.2/1.2 V, the PA achieves maximum power gain of 17.7 dB and peak PAE of 35% at 6.5 GHz. The CMOS PA occupies an area of 0.206 mm2.

Artificial Neural Network Modeling of a CMOS Differential Low-Noise Amplifier Using the Bayesian Regularization Algorithm.

The purpose of this communication is to present the modeling of an Artificial Neural Network (ANN) for a differential Complementary Metal Oxide Semiconductor (CMOS) Low-Noise Amplifier (LNA) designed for wireless applications. For satellite transponder applications employing differential LNAs, various techniques, such as gain boosting, linearity improvement, and body bias, have been individually documented in the literature. The proposed LNA combines all three of these techniques differentially, aiming to achieve a high gain, a low noise figure, excellent linearity, and reduced power consumption. Under simulation conditions at 5 GHz using Cadence, the proposed LNA demonstrates a high gain (S21) of 29.5 dB and a low noise figure (NF) of 1.2 dB, with a reduced supply voltage of only 0.9 V. Additionally, it exhibits a reflection coefficient (S11) of less than -10 dB, a power dissipation (Pdc) of 19.3 mW, and a third-order input intercept point (IIP3) of 0.2 dBm. The performance results of the proposed LNA, combining all three techniques, outperform those of LNAs employing only two of the above techniques. The proposed LNA is modeled using PatternNet BR, and the simulation results closely align with the results of the developed ANN. In comparison to the Cadence simulation method, the proposed approach also offers accurate circuit solutions.

Stability Parameters of Register File Bit Cell with Low Power Consumption Priority

This research is dedicated to a transistor sizing method of an 8-transistor register file static random access memory bit cell aiming to create two-port register files and two-port static random access memory with reduced supply voltage to reduce power consumption. This method can also be applied to 6-transistor single-port static random access memory bit cells. The method is based on the analysis of butterfly curves and the search for such values of the sizes of transistors and margin of their threshold voltages, in which, for a given critical minimal supply voltage, the condition for the existence of one intersection and one touch of its curves is achieved for the butterfly curves. The obtained samples of the register files bit cell in silicon and its critical voltage were compared to the results of circuit simulation in the write and read mode depending on the supply voltage. Experimental register files chip samples were successfully tested in silicon at a voltage of 0.75 V.

Design and Implementation of High-Performance Power-Efficient Multiple-Output Class-AB Current Mirror For Capacitance Multiplier and Precision Rectifiers

The development of high-efficiency capacitance multipliers and precision rectifiers for VLSI (Very Large-Scale Integration) systems is examined in this work, with a focus on low voltage operation. The major goal is to reduce supply voltage in order to consume energy as little as possible. It has been successfully created for the capacitance multiplier to work properly even with extremely low voltage supply, as low as 0.25 V. Class-AB current mirrors, which are renowned for their outstanding current efficiency, are used in the design. Experimental measurements were made on a 180-nm CMOS-based capacitance multiplier that obtained a multiplication factor of 11 in order to assess performance. The same class-AB current mirrors were also used in the same CMOS technology to construct low-voltage precision rectifiers. Over a hundred times more output current than quiescent current is produced by these rectifiers. Notably, both circuits function with 0.25 V supply and dissipate static power at a rate of only 100 nW. The work shows that low-voltage designs and class-AB current mirrors can be used to produce great performance and efficient power usage in VLSI systems.

Design of High Performance Operational Transconductance Amplifier

Designing high-performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in an analog circuit is the operational amplifier. At large supply voltages, there is a trade off among speed, power, and gain, amongs to ther performance parameters. Often these parameters present contradictory choices for the op-amp architecture. At reduced supply voltages, output swing becomes yet another performance metric to be considered when designing the opamp. Of the several architecture folded cascode OTA is used in which all the transistors are in saturation regime. Furthermore, in an effort to reduce costs and integrate analog and digital circuits onto a single chip, the analog designer must often face the challenges using CMOS processes. This paper covers the design and implementation of a novel CMOS folded cascode OTA designed in 1m technology. Covered topic include current source and sinks, differential amplifier, compensation techniques, two stage compensated OTA and cascode OTA. Our design emphasis is on practical design where power consumption and speed are critical. The OTA has very low settling time and can be used for high speed applications, such Analog-to–Digital converters, high speed Sigma-delta ADC.

Efficacy of Spatial and Temporal RHBD Techniques at Advanced Bulk FinFET Technology Nodes

Single-event (SE) performance of a variety of radiation-hardened by design (RHBD) flip flop (FF) circuits are evaluated at the 7-nm and 5-nm bulk FinFET nodes. For a given RHBD technique, the 5-nm node design has a single-event upset (SEU) cross-section an order of magnitude higher than that at the 7-nm node. Such an increase in SEU cross-section was not seen with scaling of previous nodes. Simulations indicate that the increase in SEU cross-section is due to disproportionate changes in single-event transient pulse-widths and sensitive areas after an ion strike. A figure-of-merit is proposed to quantify the efficacy of a given RHBD technique. RHBD FF designs are evaluated using this metric to show the efficacy of spatial and temporal RHBD techniques at the 7-nm and 5-nm technology nodes at both nominal and reduced supply voltage operations.

Design and Characterization of a Picosecond Timing ASIC in 55-nm CMOS

For more than two decades, amplifier-discriminator ASICs have been demonstrated to be the optimal choice for time measurement in high-energy physics experiments. With the requirement of time resolution further evolving towards the picosecond and sub-picosecond ranges, circuit innovation has become increasingly essential. We present a PIcoSecond Timing (PIST1) ASIC, utilizing the conventional amplifier-discriminator architecture and optimized for the readout of silicon photomultipliers (SiPMs) in the electromagnetic calorimeter (ECAL) for future Higgs factories such as the Circular Electron Positron Collider (CEPC). Further circuit developments are made to enable the ASIC to operate under minimal power with reduced supply voltage. A comprehensive analysis of the noise in the signal link is also conducted and the findings presented. A single-channel prototype is designed in 55 nm CMOS with a single 1.2 V supply voltage. The standalone ASIC testing highlights a time resolution of 4.20±0.04 ps for a minimum ionizing particle (MIP) which is equivalent to 32 pC charge. Additionally, a linear time-over-threshold (ToT) response from 1 to 12 MIP is attained and typical 15 mW power consumption realized.

Design and Analysis of a Wideband K/Ka-Band CMOS LNA Using Coupled-TL Feedback

We demonstrate a low power (PD) 22-33 GHz CMOS low-noise amplifier (LNA) with low noise-figure (NF) and small group-delay (GD) variation for 28 GHz 5G system. Body-selfforward-bias (BSFB) technique, i.e., connection of transistor’s body to drain via body resistance, is used for threshold and supply voltage reduction, and substrate leakage suppression. Gain and NF enhancement at the same PD is achieved because lower VDD and higher transconductance (due to larger bias current) are used. Current-reused topology is used for low PD. Coupled transmission -line (TL) feedback neutralization technique is proposed for further gain and NF enhancement. The feedback from output (drain) to input (gate) via gate-drain capacitance (Cgd) can be cancelled by the feedback from drain (through source) to gate via the coupled TL and gate-source capacitance (Cgs). The LNA consumes 12.2 mW and achieves S21 of 16 dB, 3 dB bandwidth (f3dB) of 11 GHz (22-33 GHz), minimum NF (NFmin) of 2.5 dB, average NF (NFavg) of 3.1 dB, and GD variation of ±6 ps for 22-33 GHz, and figure-of-merit (FOM) of 91.7 GHz. Moreover, the LNA achieves input third-order intercept point (IIP3) of -3 dBm. The NF and FOM are one of the best results ever reported for LNAs with f3dB greater than 7 GHz and PD lower than 15 mW.

Thermal-Electric Modeling: A New Approach for Evaluating the Impact of Conservation Voltage Reduction on Cooling Equipment

It has been suggested in the literature that by reducing the incoming voltage at a distribution feeder head or at the supply side of buildings, significant electricity savings can be achieved. This technique is called Conservation Voltage Reduction (CVR). Data-based analysis with and without CVR is primarily used to support such assertions, which does not explain the physics behind reduction in energy consumption with CVR. This paper presents a new approach for evaluating the impact of CVR on cooling equipment. In this approach, a thermal-electric model of the cooling process is developed in MATLAB’s SIMSCAPE toolbox that can be used to explain the physics behind energy reduction with CVR. This model includes an accurate model of a compressor coupled to an induction motor whose supply voltage can be varied to simulate CVR. Simulations performed using this model show that the Coefficient of Performance (COP) of cooling equipment improves with a reduction in supply voltage. However, the energy lost in the motor windings may nullify the impact of the improvement in the COP and render the CVR programs ineffective if the range of speed change is small over the allowable voltage change. The simulation results show an increase in energy consumption of 4% at 90% rated voltage compared to the energy consumed at the rated voltage. However, if variable frequency drives-based cooling equipment is appropriately controlled, it is possible to reduce their net energy consumption using CVR. Simulations performed keeping the ratio of the supply voltage and the frequency constant showed a reduction in energy consumption of 2.5% at 90% rated voltage compared to the energy consumed at the rated voltage. Thermal-electric modeling of building cooling equipment is, therefore, vital to accurately evaluating the benefits of CVR as smart, power electronics-based end-use equipment is globally adopted.

Integrated Low‐Dimensional Semiconductors for Scalable Low‐power CMOS Logic

AbstractScalable nanoelectronics with energy‐efficient logic technology is crucial for next‐generation edge devices. Low‐dimensional semiconductors, such as transition metal dichalcogenides and single‐walled carbon nanotubes (SWCNTs), have tunable properties with reduced short‐channel effects. The unique properties of each material can be utilized owing to the heterogeneous integration of multiple semiconducting channels to form complementary metal‐oxide‐semiconductor (CMOS) logic. However, the integration remains challenging. This study reveals the realization of low static power hetero‐CMOS inverters by the integration of n‐type monolayer MoS2 and p‐type SWCNT networks. The balanced inverter exhibits a large peak gain of ≈67 at a supply voltage of 2 V with the customized design of the wafer‐scale synthetic process and channel integration. An ultralow standby power consumption of ≈5 pW and a practical peak gain of ≈7 at a reduced supply voltage of 0.25 V are achieved. A high noise margin (>70%) validates the circuit's tolerance to external noises and the dynamic analysis of the inverting amplifier in push–pull configuration exhibits a large AC gain. This work paves the way toward the wafer‐scale integration of low‐dimensional materials for low‐power nanoelectronics.

Study of Multicell Upsets in SRAM at a 5-nm Bulk FinFET Node

Single-port and two-port SRAM designs in a 5-nm bulk FinFET node were tested for multi-cell upset (MCU) vulnerability against alpha particles, 14-MeV neutrons, thermal neutrons, and heavy ions with nominal and reduced supply voltages. Multi-cell upset contributions to single-event upset rates and observed bit-line upset ranges are presented for each particle as a function of supply voltage. Results show that MCUs account for a majority of events from high LET particles and neutrons at lower supply voltages. MCU shapes are shown for various sizes of upset clusters.

Reliability Analysis of FinFET Based High Performance Circuits

In the VLSI industry, the ability to anticipate variability tolerance is essential to understanding the circuits’ potential future performance. The cadence virtuoso tool is used in this study to assess how PVT fluctuations affect various fin-shaped field effect transistor (FinFET) circuits. In this research, high-performance FinFET-based circuits at 7 nm are discussed with a variation in temperature and voltage. The idea behind the technology is the improvement of power dissipation and delay reduction at the rise of temperature and reduced supply voltage. With the use of a multi-gate predictive model, simulation is carried out employing diverse domino logic at the 7 nm technology node of FinFET files. The proposed set-reset logic circuit and high-speed cascade circuit method shows less power dissipation and delay compared to the existing current mirror footed domino, high-speed clocked delay, and modified high-speed clocked delay with a variation of temperature and supply voltage. For the proposed set-reset logic circuit and high speed cascade circuit, a Monte Carlo simulation is done to find the mean and standard deviation. FinFET simulations are run on the suggested circuit for the reduction of delay for the rise of temperature and reduction of supply voltage from 0.7 V to 0.3 V. In comparison, the proposed method results in a maximum power decrease compared to existing ones. Compared to the existing one, proposed techniques achieve a maximum delay and area reduction.

A Selective Bit Dropping and Encoding Co-Strategy in Image Processing for Low-Power Design in DRAM and SRAM

A novel and efficient way of image processing is proposed in this paper, which fully exploits the features of DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) as well as the human visual system. The proposed strategy first approximates and encodes the image to effectively reduce the number of bit-‘1’ in the original pixel data, then the processed data is pushed into the off-chip DRAM, and later written into the on-chip SRAM for further computation. Since the storage power consumption of DRAM is proportional to the number of bit-‘1’, while the write power consumption of SRAM is linear relative to the switch probability and the square of the supply voltage, fewer bits-‘1’ in the processed pixel data will decrease the power consumption of DRAM and SRAM, yet accompanied by negligible influence on output quality as our proposed method has the advantages of both approximate computation and error compensation. Thus, a tradeoff is finally achieved between storage power consumption and output quality. In the experimental simulations, 39.8% power reduction for DRAM and 25.9% write power reduction for SRAM have been achieved. Regarding output quality, Discrete Cosine Transform (DCT), quantization, inverse quantization and inverse DCT (IDCT) are employed to process the approximated data. The simulations shows average 3.36 dB losses in Peak-Signal-Noise-Ratio (PSNR). Based on this strategy, an approach of priority-based reduction in supply voltage for insignificant pixel data is introduced to achieve further reduction in power consumption for SRAM. Undoubtedly, a lower supply voltage will increase the probability of read error from SRAM. However, with our proposed approximate coding strategy, the output quality is barely impacted by the lower supply voltage.

A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories

Power supply voltage reduction is a primary enabler for sustaining the increasing demand for ultra-low power processors. On-die memories, which are traditionally implemented by SRAM, stop functioning properly when the supply voltage is scaled down aggressively; hence, embedded DRAM (eDRAM) bit-cells are used instead. These bit-cells leak their data strongly in one direction, whereas the leakage in the opposite direction is considerably lower. Due to their intrinsic limited Data Retention Time (DRT), these memories require power-hungry refreshing, which degrades performance. In an attempt to extend the DRT of a bit-cell, theoretically to infinity, compounds of various types of storage nodes in a single bit-cell, storing the datum and its complement, were examined here. A rigorous proof shows that under realistic leakage models, there is an inherent incompleteness preventing the proper readout and decision of the stored value after a certain time. Adopting the idea of dual-polarity complementary storage nodes, a new eDRAM self-refreshable bit-cell is proposed that yields a considerably extended DRT. The dual-polarity property enables the refreshing of an entire memory array in a single clock cycle, thus almost nullifying the unavoidable performance loss occurred by row-by-row ordinary power-hungry refreshing.

Investigation of the Effect of the Voltage Drop and Cable Length on the Success of Starting the Line-Start Permanent Magnet Motor in the Drive of a Centrifugal Pump Unit

The use of Line-Start Permanent Magnet Synchronous Motors (LSPMSM) improves the efficiency of conventional direct-on-line electric motor-driven fluid machinery such as pumps and fans. Such motors have increased efficiency compared to induction motors and do not have an excitation winding compared to classical synchronous motors with an excitation winding. However, LSPMSMs have difficulty in starting mechanisms with a high moment of inertia. This problem can be exacerbated by a reduced supply network voltage and a voltage drop on the cable. This article investigates the transients during the startup of an industrial centrifugal pump with a line-start permanent magnet synchronous motor. The simulation results showed that when the voltage on the motor terminals is reduced by 10%, the synchronization is delayed. The use of the cable also leads to a reduction in the voltage at the motor terminals in a steady state, but the time synchronization delay is more significant than that with a corresponding reduction in the supply voltage. The considered simulation example shows that the line-start permanent magnet synchronous motor has no problems with starting the pumping unit, even with a reduced supply voltage. The conclusions of this paper support a wider use of energy-efficient electric motors and can be used when selecting an electric motor to drive a centrifugal pump.