Sum-product Decoding Algorithm Research Articles

Improving LDPC and turbo LDPC codes using Collection of Punctured Codes Decoding (CPCD)

In our previous paper [1], a novel CPCD technique has been introduced to significantly improve decoding of LDPC codes over the known sum product algorithm (SPA) decoding. However, results presented in [1] were limited to shorter low density parity check (LDPC) codes and transmission over an addition white Gaussian noise (AWGN) channels using QPSK modulation. In this study, we demonstrate that CPCD can achieve significant gains regardless of the length of the code or the modulation technique used for transmission or the type of the channel including fading channels. In addition, a novel turbo-CPCD technique that follows the principle of turbo LDPC is introduced. It is shown here that CPCD and turbo-CPCD can perform about 0.2−1.5 dB better than SPA decoding and turbo LDPC codes.

High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes

Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

Design of Channel Coded Heterogeneous Modulation Physical Layer Network Coding

In a two-way relay channel network (TWRC), the integration of channel coding into symmetric physical layer network coding (PNC) has been well studied, where both sources use exactly the same channel coding and modulation schemes and the relay decodes and reencodes the codewords obtained from the superimposed signals. How to integrate the channel coding into heterogeneous modulation PNC (HePNC), where the sources apply different modulations, is an open issue. In this paper, we propose a channel coded HePNC (CoHePNC) scheme under asymmetric TWRC. For repeat-accumulate (RA) codes applied at the sources, a full-state sum-product decoding algorithm is proposed which enables the relay to decode the superimposed signals from the sources to the raw decoding results firstly, and then re-encode and obtain the network-coded codewords by mapping the raw decoding results according to the proposed bit-level mapping functions. We further optimized the bit-level mapping functions according to the two source-relay channel conditions. Extensive simulation results demonstrated that the proposed CoHePNC outperforms the existing channel coded PNC schemes in terms of the relay decoding error rate and the end-to-end bit error rate under asymmetric TWRC scenarios.

An improved low-complexity sum-product decoding algorithm for low-density parity-check codes

In this paper, an improved low-complexity sum-product decoding algorithm is presented for low-density parity-check (LDPC) codes. In the proposed algorithm, reduction in computational complexity is achieved by utilizing fast Fourier transform (FFT) with time shift in the check node process. The improvement in the decoding performance is achieved by utilizing an optimized integer constant in the variable node process. Simulation results show that the proposed algorithm achieves an overall coding gain improvement ranging from 0.04 to 0.46 dB. Moreover, when compared with the sum-product algorithm (SPA), the proposed decoding algorithm can achieve a reduction of 42%–67% of the total number of arithmetic operations required for the decoding process.

Structured quasi‐cyclic low‐density parity‐check codes based on cyclotomic cosets

This study considers the construction of four-cycle free quasi-cyclic low-density parity-check (QC-LDPC) codes. These codes are based on the cyclotomic cosets of q modulo n where q is a prime power, n is a prime and (n, q) = 1. If s is the order of q modulo n, then n − 1 = sl for some integer l. Then there are l distinct cyclotomic cosets Cai , 1 ≤ i ≤ l. Concatenation of the l circulant matrices formed using these sets gives an s × sl matrix M co(n, q). In addition, the Kronecker product of the transpose of ∪ i Cai with itself modulo n gives an sl × sl matrix M kr(n, q). Replacing the entries of these matrices with their associated dispersed binary n × n matrices provides binary QC-LDPC codes with girth at least six. Furthermore, for any prime power q′ such that q′ = n + 1 or q′ ≥ 2n, these two matrices can be used to construct q′-ary QC-LDPC codes with girth at least six. These constructions produce large classes of four-cycle free binary and non-binary QC-LDPC codes. Among the structured LDPC codes, the introduced technique, from code-construction-complexity perspective, which is an engineering factor, is at least among the best ones if not the best. Performance results are presented which show that the codes obtained perform well over additive white Gaussian noise channel with the iterative sum-product decoding algorithm.

Maximum average mutual information quantisation of low density parity check codes for eight-phase-shift keying modulation

Low density parity check (LDPC) codes enjoy the good properties of approaching the Shannon limit, and its practical application is of great significance. In this paper, the decoding algorithm of LDPC codes for eight-phase-shift keying modulation is particularly studied, and the specific methods of the maximum average mutual information quantisation are analysed and deduced. With this method to quantify the initial message, the variable messages and check messages are converted into integers when each iteration has been finished, and then the min-sum decoding algorithm based on integer arithmetic is implemented. Simulation results demonstrate that the performance of the min-sum decoding algorithm with maximum average mutual information quantisation is close to that of the high-precision floating-point sum-product decoding algorithm. Meanwhile, It is convenient for hardware implementation since all the variables in the algorithm are fixed-length integers. Although the bit error rate is slightly worse than that of the sum-product decoding algorithm, the decoding time consumption is greatly reduced.

Maximum Average Mutual Information Quantisation of Low Density Parity Check Codes for Eight-Phase-Shift Keying Modulation

Low density parity check (LDPC) codes enjoy the good properties of approaching the Shannon limit, and its practical application is of great significance. In this paper, the decoding algorithm of LDPC codes for eight-phase-shift keying modulation is particularly studied, and the specific methods of the maximum average mutual information quantisation are analysed and deduced. With this method to quantify the initial message, the variable messages and check messages are converted into integers when each iteration has been finished, and then the min-sum decoding algorithm based on integer arithmetic is implemented. Simulation results demonstrate that the performance of the min-sum decoding algorithm with maximum average mutual information quantisation is close to that of the high-precision floating-point sum-product decoding algorithm. Meanwhile, It is convenient for hardware implementation since all the variables in the algorithm are fixed-length integers. Although the bit error rate is slightly worse than that of the sum-product decoding algorithm, the decoding time consumption is greatly reduced.

Error Floor Approximation for LDPC Codes in the AWGN Channel

This paper addresses the prediction of error floors of low-density parity-check codes transmitted over the additive white Gaussian noise channel. Using a linear state-space model to estimate the behavior of the sum-product algorithm (SPA) decoder in the vicinity of trapping sets (TSs), we study the performance of the SPA decoder in the log-likelihood ratio (LLR) domain as a function of the LLR saturation level. When applied to several widely studied codes, the model accurately predicts a significant decrease in the error floor as the saturation level is allowed to increase. For nonsaturating decoders, however, we find that the state-space model breaks down after a small number of iterations due to the strong correlation of LLR messages. We then revisit Richardson's importance-sampling methodology for estimating error floors due to TSs when those floors are too low for Monte Carlo simulation. We propose modifications that account for the behavior of a nonsaturating decoder and present the resulting error floor estimates for the Margulis code. These estimates are much lower, significantly steeper, and more sensitive to iteration count than those previously reported.

Recursive method for generating column weight 3 low‐density parity‐check codes based on three‐partite graphs

In this study, a method is presented to construct column weight 3 (CW3) low-density parity-check (LDPC) codes using three-partite graphs. Let Gb be a bipartite graph and Ng be the set of all minimum length cycles in Gb. Using Gb and Ng, a three-partite graph denoted G(Gb, Ng), or simply Gt, is formed. Let T be the set of length 3 cycles in Gt and Ta be the set of three element subsets of vertices in Gt such that each of these subsets form a subgraph with no edges in Gt and has precisely one element in each section of Gt. Furthermore, let H be the binary matrix in which the set of rows represent the set of vertices of Gt, the columns represent the elements of V:= T ∪ Ta, and hij = 1 if and only if the ith vertex of Gt belongs to the jth three element set in V. Then H is a CW3 binary matrix. Using the Tanner graph representing H, a recursive construction for CW3 LDPC codes is provided. Applying a simple restriction on T and Ta, codes free of length 4 cycles are generated. Euclidean and finite geometry codes are used as the base codes for generating new CW3 LDPC codes. Results are presented which show that these new codes perform well in an additive white Gaussian noise (AWGN) channel with the iterative sum-product decoding algorithm.

Random Edge-Local Complementation with Applications to Iterative Decoding of High-Density Parity-Check Codes

We describe the application of edge-local complementation (ELC) to a Tanner graph associated with a binary linear code, C. Various properties of ELC are described, mainly the special case of isomorphic ELC operations and the relationship to the automorphism group of the code, Aut(C), and the generalization of ELC to weight-bounding ELC (WB-ELC) operations under which the number of edges remains upper-bounded. ELC generates all systematic parity-check matrices (the orbit) of the code, so WB-ELC facilitates a restriction to low-weight matrices of this orbit. We propose using ELC and WB-ELC as a source of diversity, to improve iterative soft-input soft-output decoding of high-density parity-check (HDPC) codes, with the sum-product algorithm (SPA). A motivation of ELC-enhanced SPA decoding is locality; that diversity is achieved by local graph action, and is well-suited to the local actions that constitute the SPA and allows for parallel software implementation. Simulation data on the error-rate performance of the proposed SPA-ELC and SPA-WBELC iterative decoding algorithms is shown for several HDPC codes. A gain is reported over SPA decoding, and over a recently proposed algorithm to decode HDPC codes using permutations from Aut(C). ELC-enhanced decoding extends the scope of iterative decoding to codes with trivial Aut(C).

Improved Decoding Algorithm of Bit-Interleaved Coded Modulation for LDPC Code

Bit-interleaved coded modulation (BICM), which has been proven to be powerful when applied in low-density parity-check (LDPC) sum-product algorithm (SPA) decoder, is a bandwidth efficient coding scheme. However, the BICM-SPA decoder does not take the statistical dependencies between bits from the same <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> -ary modulated symbol into account so that it cannot converge to the maximum a-posteriori (MAP) decoding algorithm. In this paper, an improved SPA decoding algorithm for the LDPC code, which combines decoding and demodulation, is proposed. The proposed decoding algorithm, referred to as the BICM-ISPA, is based on generalized distributive law and derived from the generalized symbol SPA under certain rational assumptions. And the BICM-ISPA can asymptotically converge to the MAP decoding solution algorithm. Simulation results show that the BICM-ISPA decoder jointly optimizes the decoding error performance and the computational complexity of the LDPC code over the additive white Gaussian noise channel. Compared with the BICM-SPA decoder, the advantage of the BICM-ISPA is quite significant with a large modulation size and in the scenario where Gray mapping cannot be used.

Feedback iterative decoding of sparse quantum codes

Decoding sparse quantum codes can be accomplished by syndrome-based decoding through using the sum-product algorithm (SPA). We significantly improve this decoding scheme by developing a new feedback adjustment strategy for the standard SPA. In our feedback strategy, we exploit not only the syndrome but also the values of the frustrated checks on individual qubits of the code and the channel model. Consequently, our decoding algorithm, on the one hand, can break the symmetric degeneracy, and on the other hand, can feed back more useful information to the SPA decoder to help the decoder determine a valid output, thereby significantly improving the decoding ability of the decoder. Moreover, our algorithm does not increase the measurement complexity compared with the previous method, but takes full advantage of the measured information.

Low-floor decoders for LDPC codes

One of the most significant impediments to the use of LDPC codes in many communication and storage systems is the error-rate floor phenomenon associated with their iterative decoders. The error floor has been attributed to certain subgraphs of an LDPC code's Tanner graph induced by so-called trapping sets. We show in this paper that once we identify the trapping sets of an LDPC code of interest, a sum-product algorithm (SPA) decoder can be custom-designed to yield floors that are orders of magnitude lower than floors of the the conventional SPA decoder. We present three classes of such decoders: (1) a bi-mode decoder, (2) a bit-pinning decoder which utilizes one or more outer algebraic codes, and (3) three generalized-LDPC decoders. We demonstrate the effectiveness of these decoders for two codes, the rate-1/2 (2640,1320) Margulis code which is notorious for its floors and a rate-0.3 (640,192) quasi-cyclic code which has been devised for this study. Although the paper focuses on these two codes, the decoder design techniques presented are fully generalizable to any LDPC code.