Subtractor Cell Research Articles

Modified restoring array-based power efficient approximate square root circuit and its application

In this paper, the authors present an investigation into the benefits of approximate computing in energy-efficient error-resilient applications. It proposes an approximate square root (SQR) circuit based on the modified restoring array square root (MRAS) architecture. The MRAS design incorporates strategic elimination, optimization, and simplification of restoring subtractor cells (SC) within a conventional restoring array SQR circuit. As a result, the proposed MRAS circuit efficiently computes the square root of a 2n-bit unsigned integer, offering a 27 percent reduction in area, 13 percent faster computation, and 50 percent lower power consumption compared to the exact SQR design. To introduce approximation, configurable SCs are integrated into the MRAS circuit, enabling dual operation modes for both accuracy and approximation. This feature allows the proposed approximate modified restoring array SQR (AMRAS) design to cater to both error-resilient and error-sensitive applications. The evaluation involves a thorough analysis of accuracy and design metrics for 16-bit unsigned exact, state-of-the-art, and proposed square rooters. The designs are implemented on Artix7 FPGA using Verilog-HDL and simulated in the Xilinx Vivado simulator. The results demonstrate that the proposed AMRAS achieves a good trade-off between accuracy and hardware, presenting an impressive 80 percent reduction in power consumption and a 36 percent faster computation. Additionally, the paper showcases the practical application of the proposed AMRAS square rooters in the Sobel edge detection for image processing.

Hardware-Efficient Approximate Dividers for Image Processing in WSN Edge Devices

This paper proposes a hardware-efficient implementation of division, which is useful for image processing in WSN edge devices. For error-resilient applications such as image processing, accurate calculations can be unnecessary overhead, and approximate computing that obtains circuit benefits from inaccurate calculations is effective. Since there are studies showing sufficient performance with few bit operations, this paper proposes a combinational arithmetic circuit design of 16 bits or less. The proposed design is an approximate restoring division circuit implemented with a 2-dimensional array of 1-bit subtractor cells. The main drawback of such a design is the long “borrow-chain” that traverses all of the rows of the 2-dimensional subtractor array before a final stable quotient result can be produced, thereby resulting in a long delay and excessive power dissipation. This paper proposes two approximate subtractor cell designs, named ABSC and ADSC, that break this borrow chain: the first in the vertical direction and the second in the horizontal direction, respectively. The proposed approximate divider designs are compared with an accurate design and previous state-of-the-art designs based on accuracy and hardware overhead. The proposed designs have accuracy levels that are close to the best accuracy levels achieved by previous state-of-the-art approximate divider designs. In addition, the proposed ADSC design had the lowest delay, area, and power characteristics. Finally, the implementation of both proposed designs for two practical applications showed that both designs provide sufficient division accuracy.

Bit significance based reconfigurable approximate restoring dividers and square rooters

Approximate computing has received significant recognition for enhancing energy-efficiency in error-resilient applications. This paper proposes bit significance based reconfigurable approximate restoring dividers and square rooters for improved energy-efficiency. Configurable subtractor cells (CSCs) which can function both accurately and approximately are proposed along-with a simplified and scalable overflow detection hardware as major design units. These units are subsequently integrated to form complete divider and square rooter architectures. The CSCs are used to maneuver the input bits based on their progressive significance which affects the accuracy of the design. The proposed approximate designs have the ability to switch between the approximate and accurate operating modes making it suitable for both error-resilient and error-sensitive applications. For 16/8 division the proposed approximate divider reduces energy by 49% with normalized mean error distance of 0.45% when synthesized on CMOS 45-nm technology node. The 16-bit proposed approximate square rooter shows an energy reduction of 36% with marginal accuracy loss. Extensive simulation results of approximate designs are provided and compared with the state-of-the-art approximate designs. The effectiveness of the proposed approximate designs for image processing applications is demonstrated and evaluated.

READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency

Energy efficiency has emerged as one of the most essential design parameters in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes Reconfigurable Energy-efficient Approximate Divider (READ) that achieves several energy–quality configurable modes using fixed restoring array divider architecture. Conventional approximate binary dividers require various divider hardware configurations to achieve distinct energy–quality trade-off points, which decreases the hardware flexibility, especially for modern embedded systems. READ accomplishes energy efficiency while meeting the dynamically varying accuracy requirements of the targeted application. READ uses reconfigurable subtractor cells that can work in either accurate or approximate mode using a subtractor cell controller logic. The paper also introduces the design of overflow detector using minimal hardware resources. A comprehensive accuracy and hardware evaluation on CMOS 45-nm technology node are performed for the proposed dividers as well as other state-of-the- art divider designs. Compared to the accurate 16∕8 divider design, the proposed divider shows an improvement of 49% in terms of energy efficiency and is 1.26x faster, while introducing minimal errors. The proposed divider design is demonstrated for its efficacy in image processing tasks and shows nominal effect on the output quality.

CNTFET-Based Design of Ternary Arithmetic Modules

Multiple-valued logic such as ternary logic has attracted the digital system designers attention in recent years as it offers the benefits of reduced interconnects, higher operating speeds and smaller chip area. A goal of multi-threshold circuit design could be easily achieved by incorporating the scalable threshold voltage values of carbon nanotube field effect transistors (CNTFETs). This paper proposes a novel design of low-power and high-performance ternary adder and subtractor circuit design by combining the futuristic ternary and conventional binary logic design approaches. The simplified design of ternary to a binary decoder based on negative ternary inverter and positive ternary inverter outputs, and further transmission gate-based ternary multiplexer implementation facilitates the low power consumption and energy efficiency in the implementation of the complex arithmetic circuits. Extensive HSPICE simulations are conducted with the standard 32 nm CNTFET technology in order to evaluate the performance metrics of the realized circuits. According to the simulation results, proposed ternary adder and subtractor cells show the significant improvement in energy consumption (PDP) as compared to their counterparts under different test conditions. Moreover, the ripple adder structure is realized using the proposed adder circuit in order to test the practicability of given circuits in cascaded structures.

Influence of structure of 2 dimensional 2 dot 1 electron QCA cells in design of a pipelined subtractor

Quantum dot cellular automata i.e. QCA is risen as a result of tremendous examination made by scientists to discover a productive nanoscale substitution of CMOS technology. The nanoscale execution of CMOS additionally experiences high power dispersal. In this present article a thorough study has been made to discuss the benefits of square sturctured 2 dot 1 electron (2:1) QCA cell over the conventional rectangular cell. As a contextual investigation, a half subtractor and in addition a full subtractor has been proposed utilizing 2:1 QCA and an examination has been done concerning the cell structure. The plan of the half subtractor comprises of just 25 many number of 2:1 QCA cells. Then again, the full subtractor configuration contains 54 many number of cells. Utilizing this outline approach, we have accomplished upto 67% and 63% of effectiveness as for the cell number over the current half and full subtractor cell usage, utilizing 4 dot 2 electron (4:2) QCA separately. A pipelined subtractor architecture has also been developed using the proposed full subtractor layout as basic building block.

On the Design of Approximate Restoring Dividers for Error-Tolerant Applications

This paper proposes several designs of approximate restoring dividers; two different levels of approximation (cell and array levels) are employed. Three approximate subtractor cells are utilized for integer subtraction as basic step of division; these cells tend to mitigate accuracy in subtraction with other metrics, such as circuit complexity and power dissipation. At array level, exact cells are either replaced or truncated in the approximate divider designs. A comprehensive evaluation of approximation at both cell- and array (divider) levels is pursued using error analysis and HSPICE simulation; different circuit metrics including complexity and power dissipation are evaluated. Different applications are investigated by utilizing the proposed approximate arithmetic circuits. The simulation results show that with extensive savings for power dissipation and circuit complexity, the proposed designs offer better error tolerant capabilities for quotient oriented applications (image processing) than remainder oriented application (modulo operations). The proposed approximate restoring divider is significantly better than the approximate non-restoring scheme presented in the technical literature.

English

This paper deals with design of controlled adder /subtractor cell using Shannon based full adder with pass transistor logic. The proposed adder used only 14 transistors for full adder implementation. Simulations were performed by Microwind 3.1 and DSCH 2 VLSI CAD tools and BSIM 4 for parametric analysis of various features. The analysis is done on the basis of power consumption, delay and area occupied and theses are compared with previous papers and we are good to enhance these parameters.

A Cellular Array for the Nonrestoring Extraction of Square Roots

An alternative cellular array design is described for nonrestoring extraction of square roots. The array uses a single type of adder/ subtractor cell with a near-iterative connection pattern.