Subthreshold Voltage Reference Research Articles

A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference

—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the ΔVGS of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm2. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.

A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation

A subthreshold CMOS voltage reference (CVR) with low temperature coefficient (TC) over a wide temperature range and low power is proposed in this paper. The proposed CVR utilizes the ΔVGS of different-threshold and same-threshold nMOS pairs to generate complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages, respectively. To compensate for the low-temperature and high-temperature segments of the temperature characteristic curve, the nonlinear compensation currents generated by the exponential-like relationship between the drain current and the gate-source voltage of two MOSFETs work in the subthreshold region is used. Based on a 0.18-μm CMOS process, post-layout simulation results show that the proposed CVR achieves an average output voltage of 263 mV. The power supply ripple rejection (PSRR) is −75 dB at 10 Hz and the line sensitivity (LS) is 0.0069 %/V when the supply voltage varies from 0.8 V to 2.5 V. The average TC is 8.83 ppm/°C for a wide temperature range of −40 °C–120 °C, and the minimum TC is only 3.65 ppm/°C.

A 1.65‐nW 11.14‐ppm/°C self‐biased subthreshold CMOS voltage reference with temperature compensation circuit

SummaryThis paper presents a subthreshold CMOS voltage reference (VR) that utilizes self‐biased circuits. This voltage reference includes temperature compensation circuits to expand its operating temperature range and reduce its temperature coefficient. The proposed CMOS voltage reference is designed using a standard 0.18‐μm CMOS process and has a small area of only 0.005 mm2. Post‐layout simulation results demonstrate that the power consumption of the circuit at room temperature (25°C) is only 1.65 nW at a power supply voltage of 1 V. In this case, the voltage reference output is 316.56 mV, with an average temperature coefficient (TC) of 11.14 ppm/°C in a wide temperature range from −40°C to 140°C. Furthermore, the line sensitivity (LS) of the circuit is 0.024%/V, and the power supply rejection ratio (PSRR) of the circuit is −86.5 dB at 10 Hz. In summary, the subthreshold CMOS voltage reference structure proposed in this paper demonstrates excellent performance characteristics, such as low power consumption, a small area, and high‐temperature stability. These features make it a promising candidate for voltage reference for low‐power applications with significant changes in environmental temperature.

A MOSFET subdivision, MOSFET-only subthreshold voltage and current reference for LDO applications

This paper proposes a MOSFET-only voltage and current reference circuit, which can simultaneously provide a 2 V reference voltage and 300 nA reference current. This design is mainly used in a low-power Low-Dropout Regulator (LDO) project, after simulation verification, which works well in LDO applications. The circuit is performed by SMIC.18 CMOS technology and simulation with the Cadence platform, with different threshold voltage MOSFET circuit design. The whole circuit works in the subthreshold area, and the overall circuit consists of the start-up circuit, the current reference circuit, the voltage reference circuit, the MOSFET subdivision circuit, and the current mirror output circuit. The circuit has the characteristics of high precision and low power consumption, with a layout size of only 0.015 mm2. Under a temperature range of -30 to 70 °C and a power voltage of 3.3 V, the simulation and post-simulation temperature coefficients (TC) of the circuit are 5.4 ppm/°C and 19.4 ppm/°C, respectively. The post-simulation output reference voltage at room temperature is 2.0008 V, and the working power voltage within the circuit error range is 3.2 V to 3.4 V. Excluding the current mirror output circuit part of the Current-Quiescent (IQ) being 530 nA, the power consumption is 1.75 μW when the supply voltage is 3.3 V, and the design goal is reached.

A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation.

This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is -54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of -20 to 80 °C, with a projected area of 0.003 mm2.

A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique

A High-Order Temperature-Compensated Subthreshold Voltage Reference Using Channel Length Modulation Compensation Technique

A 0.6-V, 1.56-nW, 5.87-ppm/°C, 0.23%/V CMOS-Only Subthreshold Voltage Reference with the Threshold Voltage Difference

A 0.6-V, 1.56-nW, 5.87-ppm/°C, 0.23%/V CMOS-Only Subthreshold Voltage Reference with the Threshold Voltage Difference

A picowatt, 3.88 ppm/°C, 0.011%/V subthreshold CMOS voltage reference biased by GSCC current source

A picowatt, 3.88 ppm/°C, 0.011%/V subthreshold CMOS voltage reference biased by GSCC current source

3.48-nW 58.4ppm/°C Sub-threshold CMOS Voltage Reference with Four Transistors and Two Resistors

In this paper, an ultra-low power CMOS voltage reference capable of operating at sub-1[Formula: see text]V input supply is proposed. Four transistors biased in weak inversion are used to generate the required complementary-to-absolute-temperature (CTAT) and proportional-to-absolute-temperature (PTAT) voltages of the proposed circuit. Self-biasing of nature of the proposed configuration in the form of operational amplifier (opamp)-free ensure nano-power operation and eliminate the need for lateral bipolar junction transistors (BJTs) and offset cancelation techniques. A prototype of the circuit is designed and simulated in a standard 0.18-[Formula: see text]m CMOS process. Post-layout simulation results show that the circuit generates a reference voltage of 494[Formula: see text]mV with temperature coefficient (TC) of 58.4[Formula: see text]ppm/∘C across [Formula: see text]C to 85∘C; while the consuming power is lowered to 3.48[Formula: see text]nW at the minimum supply of 0.8[Formula: see text]V. The line sensitivity is 0.7%/V for the supply voltages from 0.8[Formula: see text]V to 1.8[Formula: see text]V, whereas the power supply ripple rejection (PSRR) is [Formula: see text]49.06[Formula: see text]dB at 1[Formula: see text]Hz. Monte Carlo simulation results of the voltage reference show a mean value of 497.2[Formula: see text]mV with [Formula: see text]/[Formula: see text] of 1.7%, demonstrating the robustness of the generated reference voltage against the process variations and mismatch.

A 2.1 ppm/°C, 0.55–2.4 V, 5.6 nW, 235 mV, CMOS-only subthreshold voltage reference

This study presents a high-precision, ultra-low-power, and CMOS-only subthreshold voltage reference. VPTAT with a positive temperature coefficient (TC) and VCTAT with a negative TC were generated to obtain a low-temperature dependence voltage reference. VPTAT was implemented using two standard-threshold voltage (STV) transistors working in the subthreshold region, while, VCTAT was implemented by a high-threshold-voltage (HTV) transistor and an STV transistor biased in the subthreshold region to obtain a ΔVGS with a negative TC. The voltage reference circuit was implemented via a standard 0.18-μm CMOS process with the core size around 0.022 mm2. The pre and post simulation results showed an average output reference voltage of around 235 mV with different supply voltages. Under a temperature range of −30 to 80 °C and the supply voltage of 0.55 V, the best TCs were as low as 2.1 and 7.6 ppm/°C for pre and post simulations, respectively. The total power consumption was only 5.6 nW when the supply voltage is 0.55 V.

An All-MOSFET Voltage Reference-Based PUF Featuring Low BER Sensitivity to VT Variations and 163 fJ/Bit in 180-nm CMOS

In this article, a novel subthreshold voltage reference (VR)-based physical unclonable function (PUF) is presented. With two native nMOS transistors stacked on top for providing bias current and two bottom low threshold voltage (LVT) nMOS transistors forming the self-cascode MOSFETs structure, a 4T all-MOSFET VR is proposed, which features low power consumption and high stability under largely varied VT conditions for the wide range of Internet of Things (IoT) applications. By integrating a pair of the proposed VRs and a digital voltage comparator in each PUF cell, the mismatched output voltages of the VR pair can be locally compared and digitized immediately with the system's power on, leading to ultrashort signal path and maximized immunity to the influence of temporal noise. Fabricated using standard 0.18- μm CMOS process, the proposed PUF design is validated based on extensive measurement results of 20 PUF chips. By passing the widely exploited bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test, the proposed PUF's excellent randomness is well-verified. In addition, the uniqueness is measured to be 49.92%, and the bit error rate (BER) sensitivities in terms of BER per 10 °C and BER per 0.1 V are averaged and reported to be 0.39% and 0.26%, for the temperature range of -40 °C-120 °C and supply voltage range of 1.2-1.8 V, respectively. Moreover, by operating the proposed implementation at a throughput of 50 Mb/s, the measured overall energy consumption is reported to be as low as 163 fJ/bit.

All–MOS self-powered subthreshold voltage reference with enhanced line regulation

A nano-watt self-powered voltage reference configuration has been developed for the integrated microsystems in standard CMOS technology. The circuit is highly immune to temperature variations, and can be made very insensitive to the power supply glitches originating from the simple regulation mechanisms used to harvest energy from the environment. The proposed reference is an all-MOS topology without operational amplifier or on-chip resistors, generating a stable output with excellent line regulation owing to the modifications proposed to suppress the line voltage variations. All the MOS devices are working in weak inversion to ensure operation at nano-ampere current levels. Simulated in 0.18-µm standard CMOS process, a prototype of the proposed reference consumes an overall power of 14 nW at 0.7 V minimum supply. The average voltage reference is 255 mV with an average temperature coefficient of 17.05 ppm/°C across −40 °C to +125 °C. The line regulation is 0.00797%/V and 0.00456%/V, respectively, when the reference is subjected to a line voltage of 0.9–2.0 V and 1.0–2.0 V. The power supply rejection ratio is −110 dB, −91 dB and −68 dB for 0.1 Hz, 10 Hz, and 1 MHz at room temperature, respectively.

A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation

In this paper, a 0.6 V subthsheshold CMOS voltage reference (CVR) achieving wide temperature range and high power supply ripple rejection (PSRR) is presented. The proposed CVR structure can compensate the high temperature leakage and current mirror induced mismatches so as to increase the operating temperature range. The generated reference voltage of the proposed CVR circuit is the threshold voltage difference of two NMOS transistors, leading to relatively small variations. Moreover, the enhanced current source helps achieve high PSRR. The proposed CVR circuit is implemented in a standard 0.18-μm CMOS technology. Measurement results show that, with one single trimming, a mean output of 344 mV with standard deviation of only 2.89 mV and average TC of 44.6 ppm/°C over a wide temperature range from −40 °C to 125 °C is achieved. The measured PSRR is −68 dB, −52 dB and −52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.06%/V with a power supply from 0.6 V to 2 V while consuming 19.8 nW at 0.6 V supply. The active area is 0.019 mm2.

A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS

This paper presents a low-power, low-voltage, and low-temperature-coefficient (TC) MOSFET-only subthreshold voltage reference circuit based on a standard 0.18-μm n-well CMOS process. The circuit consists of two novel current generators and an I/V conversion circuit with temperature compensation. Under the control of a proposed pMOS-bulk-driven (PBD) temperature compensation circuit, two pMOSFETs operating in a linear region act as resistors with different TCs and can be used for PTAT and CTAT current generation. Owing to the PBD technique and the subthreshold operating method, these two current generators and the I/V conversion circuit can operate at low voltage. The proposed reference circuit is realized with only standard V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (SVT) MOS devices. The measurement results show that it can operate at a minimum supply voltage of 0.5 V. The line sensitivity is 0.09% for supply voltages between 0.5 and 1.8 V. The PSRR measured at 100 Hz is 51.8 dB. A measurement of 20 samples indicates that the average TC is 35.7 ppm/°C across a temperature range of -40 to 85 °C. The proposed circuit consumes 17.6 nW from a 0.5-V power supply and occupies an active area of 0.0092 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2. The obtained average reference current is 6 nA having a slope of 5.5pA/°C.

A 48 pW, 0.34 V, 0.019%/V Line Sensitivity Self-Biased Subthreshold Voltage Reference With DIBL Effect Compensation

This paper presents a self-biased subthreshold CMOS voltage reference for low-power and low-voltage applications. To achieve near-zero line sensitivity and high PSRR, a compensation structure utilizing the drain-induced-barrier-lowering (DIBL) effect is proposed to sink a supply dependent current from the output branch of a self-biased CMOS reference, which cancels the bias current’s dependence on the supply voltage due to the DIBL effect. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology, the measurement results demonstrate that the proposed circuit could operate under a minimum supply voltage of 0.34 V and generate a reference voltage of 147 mV, while consuming only 48 pW power. The PSRRs measured at 1 Hz and 10 kHz are −70.6 dB and −50.2 dB, respectively. For 39 measured samples, the mean line sensitivity is 0.019%/V in a supply voltage range from 0.34 to 1.8 V, and the average temperature coefficients before and after trimming are 64.81 and 10.06 ppm/°C in 0 ~ 100 °C temperature range, respectively. The total area of the voltage reference circuit is 0.0332mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Low Power Low Supply MOS-Only Subthreshold Voltage Reference for Wide Temperature Range

A Sub-1V, MOS-only Voltage Reference Circuit (VRC) has been proposed with the utmost of transistors working as subthreshold region for low-supply and low-power applications. A supply-insensitive current is passed to Active Load Circuit (ALC) for supply and temperature independence at the output reference voltage. It has four current mirrors connected in a closed loop configuration to generate a supply-independent current which is passed through the ALC resulting supply and temperature insensitive output reference voltage. The ALC has a combination of two subthreshold NMOS transistors having different threshold voltages. The presented VRC is simulated using standard 90 nm CMOS model for 0.25-1 V supply voltage range. The simulation result gives minimum operating voltage required as 0.25 V for which all transistors work in their respective region of operation. For the supply range of 0.25-1 V, the obtained mean voltage reference is 100.4 mV with the line regulation of 0.186 mV/V. The temperature coefficient (TC) of 51ppm/°C is achieved for a wide temperature range of -50 to 135°C with the given minimal operating supply voltage. The power dissipation for minimal supply voltage at room temperature is 33 nW. The proposed VRC exhibits a high PSRR of -52.5 dB at 100Hz and -29 dB at 1 MHz.

0.55–1.8 V, 7.5 nW, 225.5 mV, CMOS‐only subthreshold voltage reference

This Letter presents a wide supply voltage range, ultra-low power, and CMOS-only subthreshold voltage reference. A complementary-to-absolute-temperature (V CTAT ) generator implemented by a standard V TH transistor and a high V TH transistor is used to obtain a negative temperature coefficient (TC) voltage. While, a proportional-to-absolute-temperature (V PTAT ) generator adopts a unbalanced differential pair to achieve a positive TC voltage. With both V CTAT generator and V PTAT generator, the CMOS-only voltage reference circuit is proposed, which is implemented in a standard 0.18 μm CMOS process. The simulation results show that the mean output reference voltage is 225.5 mV at room temperature with a supply voltage as low as 0.55 V, meanwhile the output reference voltage achieves a TC of 21.9 ppm/°C with a temperature range from -20 to 80°C. With a supply voltage of 0.55 V and at room temperature, the current consumption is 13.6 nA and the power consumption is only 7.5 nW. The reference circuit correctly works with a supply voltage ranging from 0.55 to 1.8 V, and it obtains the line regulation of 0.0022%/V.

A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body Biasing

A low-voltage and low-power all-MOSFET voltage reference is presented having most of the transistors working in subthreshold region. The basic beta-multiplier with cascode transistor provides a supply-independent current utilized by the active load circuit to generate an output reference voltage using body biasing. The proposed circuit is simulated using standard SCL 180-nm CMOS technology for the supply voltage ranging from 0.75[Formula: see text]V to 1.8[Formula: see text]V. The simulation obtains an average output voltage reference of 450.4[Formula: see text]mV for the given supply range at room temperature. The minimum power dissipation at room temperature is 54.37[Formula: see text]nW. The temperature coefficient (TC) of 28.13[Formula: see text]ppm/∘C is achieved having the temperature range of [Formula: see text]10–87∘C for the minimum operating supply voltage. It has the PSRR values of [Formula: see text]39.4[Formula: see text]dB at 100[Formula: see text]Hz and [Formula: see text]12[Formula: see text]dB at 1[Formula: see text]MHz. Also, the active area of the proposed circuit is 0.014[Formula: see text]mm2.

A 0.6-V Minimum-Supply, 23.5 ppm/°C Subthreshold CMOS Voltage Reference With 0.45% Variation Coefficient

In this brief, a low-voltage low-temperature- coefficient (TC) subthreshold CMOS voltage reference (CVR) is presented. The proposed CVR employs the ${\Delta }\text{V}_{\mathbf{GS}}$ of different-threshold and same-threshold nMOS transistor pairs to generate the complementary-to-absolute-temperature and proportional-to-absolute-temperature voltages, respectively. Low TC with small variations and high power supply ripple rejection (PSRR) are achieved. The proposed design is fabricated in a standard 0.18- $ {\mu }\text{m}$ CMOS process. It measures an average reference voltage of 218.3 mV with a deviation of 0.97 mV and variation coefficient of 0.45%. It achieves an average TC of 23.5 ppm/°C for a temperature range of −40 °C to 125 °C. The measured PSRR is −66.4 dB, −42.4 dB and −42.3 dB at 10 Hz, 1 kHz and 10 MHz, respectively. The measured line sensitivity is 0.40%/V for 0.6 V to 2.0 V supply. The consumed power is 30.5 nW at 0.6-V supply.