Two-dimensional (2D) materials are promising candidates for next-generation nanoelectronics in the post-Moore era. However, simultaneously scaling the channel length (Lch) and contact length (Lc) in transition metal dichalcogenide-based field-effect transistors remains a challenge. Here, we introduce an all-2D vertical metal-semiconductor field-effect transistor featuring an MoS2 channel that contacts the sidewall of a graphene (source)-hBN (insulator)-graphene (drain)-hBN (insulator) heterostructure. A self-aligned TiS2-MoS2 Schottky junction ensures full-gate control over the channel. The Lch and Lc are determined by the thicknesses of the bottom hBN and the graphene electrodes, respectively. Consequently, the Lch and Lc can be simultaneously scaled to sub-10 nm with a vertical pitch size of sub-30 nm. The typical device exhibits an on/off ratio > 107 at an operating voltage of ~0.5 V, a subthreshold swing of ~62 mV/Dec, a drain-induced barrier lowering of ~33 mV/V, and an on-state current density of ~144 μA/μm at 1 V. Sentaurus technology computer-aided design simulations further verify the good electrostatic control provided by the full-gate configuration and the bottleneck-free transport within the channel. These results highlight the potential of 2D materials for high-density and low-power integrated circuits.

The electrical performance and driving capability of monolithically integrated oxide thin-film transistor (TFT)-quantum-dot light-emitting diode (QLED) pixels are strongly affected by the dielectric environment formed during backplane-emitter integration. In this study, three interdielectric configurations─single-layer Al2O3, single-layer SiO2, and an Al2O3/SiO2 bilayer─were systematically investigated to elucidate the influence of dielectric composition and interfacial chemistry on the stability of indium-tin-zinc oxide (ITZO) TFTs and QLED driving behavior. Although the Al2O3-only device exhibited the best intrinsic TFT performance, hydrogen diffused into the Al2O3/SiO2 bilayer during the plasma-enhanced chemical vapor deposition of SiO2, which generated donor-like defects in the ITZO channel and negatively shifted the threshold voltage. Nevertheless, the bilayer simultaneously provided superior current leakage suppression and compatibility with the subsequent solution-processed QLED fabrication, enabling stable pixel operation. The bilayer-based TFT achieved a mobility of 24.82 cm2 V-1 s-1, a subthreshold swing of 0.09 V dec-1, and an on/off ratio of 8.78 × 109. When used to drive InP QLEDs, the integrated pixel reached a peak luminance of 9,488.8 cd m-2, a maximum current density of 285.3 mA cm-2, and an external quantum efficiency of 7.15%, while maintaining an unchanged electroluminescence spectrum when driven by TFTs. These results demonstrate that interdielectric layer engineering, particularly the balance between hydrogen-induced voltage threshold shifts and process robustness, is critical for achieving reliable monolithic TFT-QLED operation for next-generation active-matrix display technologies.

The dual-material gate junctionless FinFET (DMG JLFinFET) has emerged as a promising device in semiconductor technology due to its enhanced capability to suppress short-channel effects (SCEs). This work presents a comprehensive study on how temperature variations affect the electrical behavior of DMG JLFinFETs, particularly for devices scaled to the 7nm technology node. Essential DC parameters-such as subthreshold swing (SS), drain-induced barrier lowering (DIBL), and the ION/IOFF ratio-were evaluated over a temperature span of 200 to 400K. In addition, the study examines how temperature impacts key analog and radio frequency (RF) parameters, including gate-to-drain capacitance (Cgd), gate-to-source capacitance (Cgs), total gate capacitance (Cgg), transconductance (gm), cutoff frequency (ft), transconductance generation factor (TGF), intrinsic delay (τ), gain-bandwidth product (GBW), and transconductance frequency product (TFP). The investigation also addresses how thermal conditions influence linearity performance, focusing on metrics such as second-order transconductance (gm2), third-order transconductance (gm3), voltage intercept points (VIP2, VIP3), third-order input intercept point (IIP3), and the 1 dB compression point. The findings of this investigation demonstrate that the DMG JLFinFET exhibits promising electrical, analog, and RF performance characteristics, making it a viable candidate for advanced communication applications.

As silicon transistors scale toward future technology nodes, three-dimensional architectures-including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs)-require channel widths in the tens of nanometers to meet density targets. Monolayer transition metal dichalcogenides (TMDs), with their atomically thin bodies, are promising channel materials for these architectures, yet most TMD-based FETs remain limited to micrometer-scale widths. Here, we show that channel width scaling of monolayer MoS2 nanoribbon transistors not only preserves but also enhances device performance. Reducing the channel width from hundreds of nanometers to ~30-40 nm increases the median on-current density by ~42% and reduces the median subthreshold swing by ~16%, with a champion device reaching 995 µA µm-1 at a drain-to-source voltage of 1 V and an overdrive voltage of 2.5 V. We attribute these improvements to three mechanisms: minimal edge-induced disorder, enhanced gate electrostatics at ribbon edges, and more efficient side-contact injection, together reducing contact resistance from ~860 Ω µm to ~270 Ω µm. Extending the platform to n-type WS2 and p-type WSe2 FETs, we achieve WSe2 p-FET on-currents of 357 µA µm-1. These findings suggest that monolayer TMD nanoribbon FETs are promising candidates for future ultra-scaled electronics.

Volatile threshold switching (TS) devices are critical selector components for suppressing sneak path currents in high-density crossbar arrays. However, active-metal-based TS devices often face the challenge of stochastic conductive filament overgrowth. In this work, we report a high-performance TS device based on a Graphene/CuInP₂S₆/h-BN/Au van der Waals heterostructure. By utilizing hexagonal Boron Nitride (h-BN) as an atomic-scale ion sieve, we achieve atomic-scale geometric confinement of Cu filament growth. The device exhibits excellent unipolar switching characteristics, featuring a high on/off ratio (>105), ultra-low off-state leakage current (∼pA), and a steep subthreshold swing (<15 mV dec-1). Mechanistic investigations reveal that the h-BN layer confines the filaments to the atomic scale, causing the metastable filaments to spontaneously rupture upon bias removal due to Rayleigh instability, thereby enabling rapid self-resetting. This interface engineering strategy effectively addresses the filament overgrowth issue, providing a reliable solution for low-power neuromorphic computing hardware.

Monolithic 3D integration of oxide thin-film transistors provides an approach to continue Moore's Law. Crystalline indium oxide (In2O3) is particularly attractive owing to its high electron mobility and low contact resistance. However, its practical deployment is hindered by the difficulty of fabricating crystalline In2O3 under BEOL-compatible conditions and by the intrinsic instability of surface oxygen. In this work, we demonstrate an atomic-layer-deposition-enabled stabilization strategy that simultaneously achieves high mobility, strong electrostatic control, and exceptional stability in crystalline In2O3 transistors. The afforded devices exhibit a high electron mobility of 92.8 cm2/V·s, a positive threshold voltage of 0.67 V, a steep subthreshold swing of 64.5 mV/dec, and fairly small threshold voltage shifts of -5.6 and 18.6 mV under negative- and positive-bias stress, respectively. Furthermore, the devices show good resistance to forming gas annealing, with small threshold voltage shifts and no degradation in subthreshold swing or on-current. This work not only provides valuable insight into the origin of instability for crystalline oxide semiconductors, but also demonstrates a practical fabrication approach at CMOS BEOL-compatible temperatures to achieve both high performance and high stability for oxide transistors, thereby highlighting the high promise of indium oxide transistors for advanced M3D integration.

High-mobility amorphous indium-tin-gallium-zinc oxide (ITGZO) thin-film transistors (TFTs) with hafnium dioxide (HfO2) dielectric films are fabricated via continuous atomic layer deposition (ALD) using a liquid delivery system . The ITGZO TFTs prepared with a single cocktail precursor exhibit improved interfacial characteristics owing to the low surface roughness of the gate dielectric and channel layers and their high proportion of metal-oxygen bonding structures. A high field-effect mobility (up to 150 cm2 V-1 s-1), high on/off current ratio (>108), and low subthreshold swing (<0.07 V dec-1) at operating voltages within 1 V are achieved. To the best of our knowledge, this work is the first to report the highest mobility of 1 V-operable metal-oxide TFTs even with an amorphous-phase channel, which is comparable with those of polycrystalline silicon-based TFTs. The origin of the exceptional electrical characteristics of the resulting devices is analyzed by investigating the role of continuous ALD and Sn incorporation into the IGZO film. Low activation energies (∼15 meV) and density of trap states (∼9.3 × 1021 eV-1 cm-3) are determined, indicating superior charge-transport properties compared with other reported ALD-based metal-oxide TFTs.

Accurate and energy-efficient gas sensing remains a key challenge for next-generation artificial olfactory systems, particularly in applications such as unmanned aerial vehicles, wearable electronics, and humanoid robotic actuators. Inspired by the inherent selectivity and low-power information-processing mechanisms of biological olfactory neurons, we report an integrated olfactory sensory neuron (OSN) that simultaneously achieves high sensitivity and selectivity, signal stability, and neuromorphic spiking output. The device combines iodine-passivated colloidal quantum dots (CQDs) as molecular receptor layers with a wafer-level high-electron-mobility transistor (HEMT) transduction platform. The intrinsically low subthreshold swing and high on/off ratio of the HEMT enable efficient amplification of gas-induced charge modulation and allow the direct generation of spike-like signals. The artificial OSN achieves an ultralow detection limit of 0.5 ppb for NO₂ and successfully differentiates NO₂ from NO via principal component analysis (PCA). These results establish a scalable approach for neuromorphic olfactory modules, providing greater degrees of freedom for AI-driven olfaction and enabling compact, high-performance sensing in robotics, environmental monitoring, and healthcare applications.

Negative capacitance field-effect transistors (NCFETs) have emerged as potent contenders for next-generation electronics, capable of surmounting Boltzmann's tyranny that limits the minimum subthreshold swing (SS) to 60 mV dec-1 at room temperature. Despite these advances, most precedents beyond silicon channels employ unconventional channels such as 2D van der Waals materials or 1D carbon nanotubes, whose tenuous CMOS compatibility hampers uniformity in large-scale fabrication and exacerbates concerns about reproducibility. Functional oxides, such as oxide semiconductors and high-k oxides, offer a breakthrough to these obstacles, especially with CMOS-compatible methods like atomic layer deposition (ALD). Here, we demonstrate NCFETs with all components fabricated by ALD, featuring Ga-doped HfO2 (HGO) as the ferroelectric layer, undoped HfO2 as a paraelectric buffer, and indium gallium zinc oxide (IGZO) as the channel. The fabricated devices exhibit an average SS of 46 mV dec-1 at room temperature over nearly two decades of drain current, clearly surpassing the thermionic limit. All 27 devices deliver SS values below 60 mV dec-1, attesting to device-to-device uniformity and high fidelity enabled by the ALD process. We preset the ferroelectric HGO layer and tailor the capacitance of the paraelectric buffer to ensure hysteresis-free, ultralow SS operation of the NCFET. Additionally, the NCFET successfully serves as the driver transistor in a resistive load inverter, achieving a voltage gain of 25.7 and consuming ∼18 pW μm-1 at VDD = 1 V. These findings establish an all-oxide, ALD-compatible NCFET platform that mitigates the scalability, uniformity, and reliability bottlenecks of the previous approaches and is adequate for wafer-scale, energy-efficient logic.

Attogram per milliliter detection of prostate cancer biomarker using polymer dots-based electrolyte-gated organic field-effect transistor.

Cylindrical FE–FE–DE heterostructure-assisted MOSFET for improved ON/OFF ratio and subthreshold swing

Optimizing arsenide/nitride interface for high-performance dissimilar length and width tfets with charge plasma modulation

The practical implementation of two-dimensional (2D) transistors is fundamentally limited by the lack of gate dielectrics that can simultaneously deliver a high dielectric constant, a wide bandgap, strong breakdown strength, and long-term environmental stability-an often-overlooked yet critical requirement for reliable device integration. Here, we report 2D single-crystalline TbOCl nanosheets as gate dielectrics that uniquely reconcile these competing demands. TbOCl exhibits a high dielectric constant (12.5), an ultrawide bandgap (∼6.6eV), and a high breakdown field (11.9 MV cm-1). MoS2 field-effect transistors (FETs) gated by TbOCl exhibit excellent electrostatic control, yielding a near-ideal subthreshold swing of 72mV dec-1, a small hysteresis of only 8mV, and an ultra-low gate leakage current of ∼10-13 A. Notably, TbOCl-based devices maintain ultrastable electrical performance after more than 9 months of ambient storage with negligible performance degradation. The superior stability originates from an intrinsic dual-antioxidation mechanism that effectively suppresses oxidative degradation of the dielectric. Furthermore, logic inverters fabricated with TbOCl gate dielectrics exhibit fast switching behavior, with rise and fall times of 80 and 16 µs, respectively. Together, these results establish TbOCl as a stable, high-performance 2D dielectric platform, offering a viable pathway toward reliable 2D electronic devices.

A cylindrical gate-all-around (GAA) carbon nanotube field-effect transistor (CNT FET) utilizing a semiconducting zig-zag (19,0) nanotube channel is developed for sub-10-nm technology applications. The device incorporates a conformal high-k lanthanum oxide gate dielectric forming a wrap-gate architecture, enabling strong electrostatic confinement under aggressive device scaling. To regulate carrier transport and mitigate short-channel effects, underlap engineering is systematically introduced with lengths ranging from 0 to 5nm, resulting in six device configurations (Devices A-F). Self-consistent quantum transport simulations based on the non-equilibrium Green's function (NEGF) formalism reveal a distinct trade-off between drive capability and electrostatic integrity within the device. Performance evaluation is conducted using key electrostatic and carrier transport metrics. Compared with the non-underlap configuration (Device A), the optimized 3nm underlap device (Device D) exhibits a 50.7% reduction in off-state leakage current, a 23.7% improvement in subthreshold swing, and a 26.5% suppression in drain-induced barrier lowering, while enhancing the switching ratio by 84.5% with minimal degradation in drive current. Furthermore, linearity and harmonic distortion analysis indicates reduced higher-order components, confirming improved analog stability under RF operating conditions for advanced nanoelectronic applications.

This study demonstrates high performance Ω-shaped-gated single-crystal In2O3 field-effect transistors (Ω-SC In2O3 FETs), which push the performance boundaries of oxide-based electronics. To showcase these capabilities in a demanding application, a capacitorless two-transistor (2T0C) dynamic random-access memory (DRAM) cell is fabricated based on Ω-SC In2O3 FETs. Specifically, a high average field-effect mobility of 321.7 cm2/V·s with an on-off ratio above 109 and a steep subthreshold swing (SS) of 64.6 mV/dec are obtained for Ω-SC In2O3 FETs due to the single-crystal In2O3 channel as well as effectively enhanced electrostatic control of the Ω-shaped gate structure. The robust gate bias temperature stress stabilities, including positive and negative bias-temperature stresses, are achieved with a threshold voltage (VTH) shift value of −121 and 41 mV for 104 s, respectively, which is attributed to low defect density. Moreover, the high-performance capacitorless 2T0C DRAM cell based on Ω-SC In2O3 FETs is constructed, which presents long data retention of 105 s, ultrafast access speed of 5 ns, endurance of 1012 cycles, and storage of 3 bits.

In this paper, we report a tunnel field-effect transistor (TFET) based on a zigzag antimonene nanoribbon (ZSbNR) with a 12nm channel length, simulated using density functional theory (DFT). This study investigates the effects of the drain pocket (DP), underlap, and lightly doped drain (LDD) techniques on ambipolar current and overall performance in short-channel TFETs utilizing low-dimensional materials. However, the first two methods increased short-channel effects (SCEs), indicating limited effectiveness in short-channel TFETs. The third technique, LDD, despite decreasing the OFF-current, reduced the ambipolar current by only about 40 times. This motivated the adoption of a hybrid approach to mitigate both SCEs and ambipolar current simultaneously. The DP method shows strong capability in reducing ambipolarity. A 4nm DP decreases the ambipolar current by two orders of magnitude, and further increasing the DP length enhances this effect. However, it also leads to a sharp increase in the OFF-current, degrading the subthreshold swing and severely limiting its applicability. The underlap method, by contrast, has a weaker influence on ambipolar suppression but causes less degradation in the OFF-state characteristics. When combined with the LDD technique, the underlap's suppression effect is significantly enhanced, while its adverse impact on the OFF-current is mitigated. Specifically, employing a 3nm underlap together with a 4nm LDD with a modified doping concentration reduces the ambipolar current by more than 600 times, while keeping the OFF-current nearly unchanged compared to the initial TFET. Finally, the proposed hybrid approach reduces the intrinsic delay time by more than threefold, demonstrating its substantial effectiveness in improving the overall device performance.

This research examines GaSb/Si-based source-pocket vertical heterojunction tunnel field-effect transistors (SP-H-V-TFET) both with and without ferroelectric oxide layers (SP-Fe-H-V-TFET), refined through Silvaco TCAD modeling for low-power electronics. The ferroelectric variant delivers a subthreshold swing (SS) of 26 mV/dec and I ON/I OFF of 7.5 × 1011 at V DS = 0.5 V, markedly surpassing the baseline non-ferroelectric SP-H-V-TFET (SS: 43 mV/dec, I ON/I OFF: 3.2 × 1010) with ∼1.6× steeper SS and ∼23× higher current ratio, driven by negative capacitance in the HfO2-like ferroelectric film. The GaSb source boosts band-to-band tunneling at the type-II heterojunction, complemented by source-pocket optimization for enhanced electrostatics. Analyses of temperature sensitivity, analog/RF figures-of-merit, and circuit-level transient/DC responses validate the ferroelectric design’s excellence in stability, speed, and efficiency, establishing its potential for advanced ultra-low-power systems.

This work presents a comprehensive analysis of a Palladium (Pd)-gated graphene nanoribbon field-effect transistor (GNRFET) as a high-sensitivity potential hydrogen sensor under idealized conditions, focusing on the structural and environmental control of multimetric sensitivity. Hydrogen adsorption is modeled through pressure-dependent work-function modulation and interface coverage, including competition with oxygen. For hydrogen gas at a pressure of Torr without O2, the sensor exhibits a maximum threshold voltage sensitivity of about 300 mV, which is reduced to roughly 40 mV under an oxygen partial pressure of 152 Torr, quantifying the impact of background gas on response. Band diagrams, transmission spectra, local density of states, and transfer characteristics are examined over wide ranges of H2 pressure, temperature, gate length, and nanoribbon width. Sensitivity is evaluated using drain current change, threshold voltage shift, and average subthreshold swing variation. Results showed that the sensitivity based on current is high for ultralow hydrogen pressures, whereas it is low in higher levels of pressure compared to the sensitivity based on subthreshold. Also, uncertainty analysis revealed that the threshold voltage metric remains largely geometry-independent and thus tolerant to fabrication variations.

Achieving both steep-slope switching and robust non-volatile memory within a single transistor would enable new device concepts for low-power and logic-in-memory architectures. Conventional negative-capacitance FETs (NC-FETs) are designed to suppress ferroelectric bistability to enable hysteresis-free sub-thermionic switching, whereas ferroelectric FETs (Fe-FETs) exploit bistable polarization to provide non-volatile memory, leaving the two operating regimes largely separate in practice. Here, we report a van der Waals ferroelectric negative-capacitance transistor (FeNC-FET) that simultaneously realizes stabilized negative capacitance and intrinsic bistable polarization by employing a CIPS/h-BN/α-In2Se3 trilayer gate stack. Landau-Khalatnikov analysis and polarization-voltage measurements confirm complementary ferroelectric roles in which CIPS provides static negative curvature, h-BN enables charge compensation, and α-In2Se3 supplies non-volatile polarization. This cooperative mechanism enables steep sub-threshold swings of 35mV/dec (forward) and 51mV/dec (reverse), a ∼3V memory window, long retention (>104 s), and endurance exceeding 2500 cycles. The device further performs AND, OR, and majority logic-in-memory operations using 10 µs pulses with clear ON/OFF separation. These results establish the FeNC-FET as a compact platform that combines steep-slope switching with non-volatile programmability in a single device, enabling low-bias readout, short-pulse programming, and robust logic-in-memory operation.

HighlightsSystematic elucidation of annealing-temperature-dependent evolution of oxygen vacancies, M–O network densification, and crystallisation behaviour in sol–gel HfO2, directly correlating with TFT electrical performance and band alignment.All-solution-processed HfO2 high-K gate insulator and IZO active layer are achieved via the sol–gel method, eliminating expensive vacuum equipment.The optimised 85 nm HfO2 insulator annealed at 400 °C delivers outstanding device metrics (Ion/off = 1.11 × 106, SS = 0.53 V/dec, Vth = −1.1 V), proving that solution-derived HfO2 is a viable and scalable alternative to conventional SiO2 for TFT miniaturisation without performance trade-off.With the continuous advancement of display technology and advanced integrated circuits, oxide thin-film transistors (TFTs) have become core devices due to their high mobility, low leakage current and excellent large-area uniformity. To achieve low power consumption, high performance and high reliability, the introduction of high-k gate insulating layers is crucial. Among the numerous high-k materials, hafnium oxide (HfO2) has attracted significant attention due to its excellent dielectric properties and good compatibility with CMOS processes. In this paper, uniform and dense HfO2 films were successfully fabricated using the sol–gel method to serve as insulating layers for TFT devices. Through experimental analysis, 400 °C was determined to be the optimal annealing temperature. At this temperature, the effects of replacing SiO2 with HfO2 as the insulating layer, as well as the impact of reducing film thickness, on TFT devices were investigated. Ultimately, at an annealing temperature of 400 °C, an 85 nm-thick HfO2 film achieved the highest on/off current ratio (Ion/off = 1.11 × 106), the lowest subthreshold swing (SS = 0.53 V/dec), the lowest threshold voltage (Vth = −1.1 V) and the lowest off-current ratio (Ioff = 2.5 × 10−12 A). It was confirmed that replacing SiO2 with HfO2 as the insulating layer is a viable approach for reducing the volume of TFT devices.