Subthreshold Source-coupled Logic Circuits Research Articles

Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits

This article explores the effect of device parameter variations on the performance of subthreshold source-coupled logic (STSCL) circuits. A test chip has been fabricated in a standard CMOS 90 nm technology to study the matching properties of STSCL circuits. Both process variations and device mismatch have been included in this study. The performed analysis shows that while the STSCL topology is very robust against global variations mainly thanks to the adoption of an on-chip bias generator circuit, special design techniques are required to compensate for the effect of device mismatch. Proper device sizing as well as creating intentional mismatch in the biasing condition of STSCL gates are two effective approaches that have been investigated to overcome the variation related issues. Both die-to-die (D2D) and within-die (WID) variations in the delay of STSCL gates have been characterized and validated through measurements. A comprehensive analysis of timing jitter in STSCL-based ring oscillators is also presented.

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

The performance of subthreshold source-coupled logic (STSCL) circuits for ultra-low-power applications is explored. It is shown that the power consumption of STSCL circuits can be reduced well below the subthreshold leakage current of static CMOS circuits. STSCL circuits exhibit a better power-delay performance compared with their static CMOS counterparts in situations where the leakage current constitutes a significant part of the power dissipation of static CMOS gates. The superior control on power consumption, in addition to the lower sensitivity to the process and supply voltage variations, makes the STSCL topology very suitable for implementing ultra-low-power low-frequency digital systems in modern nanometer-scale technologies. An analytical approach for comparing the power-delay performance of these two topologies is proposed.