Subset Of VHDL Research Articles

A Compiler Project with Learning Progression

We describe the design of an undergraduate compilers course for computer engineering students in which the projectis to write a simulator and synthesizer for (a subset of) VHDL. The traditional project for such a course is to write a compiler for (a subset of) some procedural programming language. The choice of source language is superficially intended to drive student engagement for computer engineers. The main pedagogical advantage of this project is that item bodies a learning progression: repetition with increasing complexity.This project involves two additional languages: a regular language for boolean waveforms (used for circuit simulator inputand output), and a context-free language for boolean formulas. Parsing and transformations are performed on these simpler languages before attempting them on the subset of VHDL. At the end of the project the students can simulate and synthesize simple circuits such as a ripple-carry adder or a multiplexer.

HML, a novel hardware description language and its translation to VHDL

We present hardware ML (HML), an innovative hardware description language (HDL) based on the functional programming language SML. Features of HML not found in other HDL's include polymorphic types and advanced type checking and type inference techniques. We have implemented an HML type checker and a translator for automatically generating VHDL from HML descriptions. We generate a synthesizable subset of VHDL and automatically infer types and interfaces. This paper gives an overview of HML and discusses the translation from HML to VHDL and the type inference process.

Oversampling ΣΔ Analog-to-Digital Converters Modeling Based on VHDL

The paper presents a VHDL model of an oversampling ΣΔ analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital part is described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

A formal refinement calculus targeted at system-level descriptions in the IEEE standard hardware description language VHDL is described here. Refinement can be used to develop hardware description code that is “correct by construction”. the calculus is closely related to a Hoare-style programming logic for VHDL and real-time systems in general. That logic and a semantics for a core subset of VHDL are described. The programming logic and the associated refinement calculus are shown to be complete. This means that if there is a code that can be shown to implement a given specification, then it will be derivable from the specification via the calculus.

VHDL synthesis description portability: The need for Level synthesis subsets

Abstract Synthesis represents today one of the most important applications of VHDL with a high user demand. Nevertheless, VHDL lacks a standard synthesis methodology and, as a consequence, each synthesis tool imposes its own synthesis methodology on the user. This fact has many disadvantages; the main one is the lack of portability. In this paper, the activities of the European VHDL Synthesis Working Group towards the definition of a Level-0 synthesis subset will be described. The Level-0 subset will constitute a standard subset of VHDL for synthesis applications which will allow description portability between tools as well as design reusability. Their contents will be described and their advantages and limitations commented on.

A formalization of a subset of VHDL in the Boyer-Moore logic

We present a mathematical definition of a hardware description language that admits a semantics-preserving translation to a subset of VHDL. The language is based on the VHDL model of event-driven simulation and includes behavioral and structural circuit descriptions, the basic VHDL propagation delay mechanisms, and both zero and nonzero delays. It has been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. We prove a number of basic properties of the simulator, which we apply to the analysis of gate-level designs of a one-bit adder and a d-flip-flop.

Denotational semantics of a synchronous VHDL subset

A denotational definition for a single clock synchronous subset of VHDL is proposed. The different domains for variables and signals, the elaboration of static environments, and the formulation of a simulation algorithm for the sub-language characterize this definition, and distinguish it from more traditional denotational semantics of programming languages.

An asynchronous model for high-level synthesis

This paper presents an asynchronous interface model designed for high-level synthesis. The model represents hardware as a set of sequential processes communicating by level-sensitive asynchronous protocols. Based on this interface model, a synthesizable subset of VHDL for input specification to high-level synthesis is defined. During synthesis, a simpler representation of the design is required; for this purpose, an extended data flow graph is proposed which supports the same interface model. Finally, a compatible RTL model is defined for the synthesis output. Conversion from the input language to RTL structures is examined, and a simple example is given.

A language for describing boundary scan devices

Boundary scan (IEEE Standard 1149.1-1990) technology is beginning to be embraced in chip and board designs. One key need is a way to simply and effectively describe the feature set of a boundary scan compliant device in a manner both user friendly and suitable for software to utilize. A language subset of VHDL is proposed here for this purpose. As with any new standard, the industry is learning how to apply its rules and mistakes will occur. A derivative effect of the language proposed here is that if a device is not describable by the language, then that device does not comply with the 1149.1 standard. While the converse is not true, the language still allows a syntactic check for compliance as well as a number of semantic checks.