Submicron CMOS Process Research Articles

Composite Gate Oxide Method for Improving the Reliability and Leakage Performance of Deep Submicron CMOS Processes

This article aims to address the issues of gate oxide reliability failure and leakage loss in SRAM circuits caused by the introduction of additional high-voltage devices in the 90 nm standard process. It investigates the corner thinning phenomenon using different gate oxide scheme. It analyzes the corresponding relationship between composite gate oxide and reliability and tests the leakage of the SRAM circuit. Research has shown that the use of composite gate oxide can effectively improve corner thinning. The ratio of thermal oxide to HTO in composite gate oxide directly affects GOI/TDDB. At the same time, the use of composite gate oxide also decreases device leakage to a certain extent. The standby leakage of SRAM circuits(Isb) can be reduced from 200 nA to less than 10 nA.

A Subcircuit-Based Model for the Accumulation-Mode MOS Capacitor

The accumulation-mode metal-oxide-semiconductor (MOS) capacitor is commonly employed to implement MOS varactors in frequency-tuning circuits for radio frequency (RF) and analog applications. A subcircuit model for the accumulation-mode MOS (AMOS) capacitor based on the Berkeley Short-channel IGFET Model (BSIM) for the MOS field effect transistor (MOSFET) is presented. The proposed model accurately fits the capacitance-voltage (C-V) characteristics of an AMOS capacitor fabricated in a submicron CMOS process over the full range of operating gate voltages. The model also accounts for the impact of the distributed series resistance on the transient response of the AMOS capacitor. Notably, the gate capacitance and the associated series resistance are modeled as a distributed resistor-capacitor (RC) network to derive a subcircuit-based model with the bias-dependent resistance of the accumulation layer modeled as a voltage-controlled resistor (VCR). The proposed model is evaluated based on SPICE simulation of the intrinsic transient response of the AMOS capacitor using a basic circuit, representing the distributed RC network associated with the MOS device structure. Fine tuning of the effective series resistance in the subcircuit model can be achieved by fitting the measured data characterizing the charge–discharge behavior of the AMOS capacitor to the simulated data characterizing the intrinsic transient response generated by SPICE.

An input controlled leakage restrainer transistor‐based technique for leakage and short‐circuit power reduction of 1‐bit hybrid full adders

SummaryThe sharp increase in the leakage part of the total power of the very large scale integration (VLSI) circuits is a significant concern in the deep submicron CMOS process. The NOT gates, Gate Diffusion Input (GDI) cells, restorer NMOS–PMOS transistors for full‐swing operation, and any path from the power voltage to the ground are the main sources of leakage power dissipation as well as short‐circuit in the VLSI CMOS circuits/chips. The input controlled leakage restrainer transistor (ICLRT) is a new circuit‐level method that is proposed in this paper. The ICLRTs can be deliberately added to any VLSI CMOS circuit to largely diminish the total power dissipation especially by the reduction of its leakage and short‐circuit parts. The full adders are vital parts in various VLSI circuits/systems, especially in circuits used for fulfilling arithmetic operations. Those are often placed in the critical paths for multiplication and division, so influence the throughout the efficiency of the system. To test the proposed technique, ICLRTs added to five best 1‐bit hybrid full adders in the deep submicron process to fit the needs of the day. The efficiency of the proposed method is evaluated using SPICE simulations in 22‐nm CMOS BSIM4 process. Evaluation outcomes with 1‐V power supply verified that the power dissipation and power‐delay product (PDP) of the hybrid full adders based on ICLRT technique relative to corresponding original designs are reduced 65.67–95.7% and 35.85–87.37%, respectively. Mismatch analysis and Monte Carlo simulations prove the robustness and stability of the presented circuits in the presence of the process, voltage, and temperature (PVT) variations.

Modeling the impacts of heavy charged particles on electrical characteristics of n-MOSFET device structure

The use of microelectronic products in outer space is possible if protection is provided against special external influencing factors, including radiation effect. For digital integrated circuits manufactured using submicron CMOS processes, the greatest influence is exerted by radiation effects caused by exposure to a heavy charged particle. The use of special design tools in the development of dual-purpose microcircuits, with increased resistance to the impact of heavy charged particles, prevents single events from occurring. Thus, the use of modern software products for device and technological modeling in microelectronics when developing the element base of radiation-resistant microcircuits for space purposes will cut the time to develop new products and make it possible to modernize (improve performance) already existing device and circuitry solutions. The paper delivers the results of modeling the impacts of heavy charged particles with a magnitude of linear energy transfer equal to 1.81, 10.1, 18.8, 55.0 MeV·cm2/mg, corresponding to nitrogen ions 15N+4 with an energy E = 1,87 MeV; argon 40Ar+12 with an energy E = 372 MeV; ferrum 56Fe+15 with an energy E = 523 MeV; xenon 131Xe+35 with an energy E = 1217 MeV, on electrical characteristics of n-MOSFET device structure. The dependences of the maximum drain current IС on the motion trajectory of a heavy charged particle and the ambient temperature are shown.

TCAD tools in undergraduate studies: A laboratory work for learning deep submicron CMOS processes

This article discusses one exemplary and one original laboratory work from the micro- and nano-electronics manufacturing process laboratory works cycle. These laboratory works have been successfully introduced into the undergraduate programme and have been attended by students for several years at Vilnius Gediminas Technical University, Faculty of Electronics. This laboratory work is unique in that it consistently displays and graphically depicts practically all CMOS transistor manufacturing processes: from the preparation of the silicon wafer to the final passivation. Silvaco TCAD tools are used in order to simulate these technological processes. This type of laboratory works provides students with the necessary knowledge of chip manufacturing processes and TCAD tools without the use of costly manufacturing equipment specific to each technological process in the fabrication chain, long-term experiments and a large amount of human resources. This article also presents and discusses student feedback statistics over several years of studies, the advantages of this laboratory work, recommendations for further improvement and formulates conclusions.

A macro model of RF Schottky diode in 22-nm CMOS and its application

RF Schottky Barrier Diode (SBD) device can be compatible with deep submicron CMOS process, which is a research edge-cutting technology in the field of microelectronics. An accurate device model is highly required by the relevant circuit simulation work. In this paper, a macro device model of SBD in 22 nm CMOS node is developed based on the actual device structure. To increase its accuracy, a novel iterative algorithm is employed during the model parameter extraction. The simulation results are consistent with experimental data in frequency range from 10 MHz to 10 GHz, indicating that the developed SBD model can accurately reflect the DC and RF characteristics of the 22 nm device. Moreover, the application of the developed RF SBD device model is verified based on RF energy harvesting circuit in terms of the output voltage and efficiency, showing the feasibility of the developed SBD model in RF integrated circuit.

Various Issues and considerations for the Static Power Consumption in NANO-CMOS: Design Perspective

Now a days designing techniques are very much concerned about the leakage currents reduction at different stages of abstraction.Leakage reduction strategies can be categorized on the basis of their effectiveness and output rate of 3 major classes: enhanced devices, trade off techniques, and leakage management. Static power consumption by the leakage currents is the main issue in CMOS ICs with gate lengths of 90 nm and less than that. Generally, the procedure allied with deviation may extensively amplify the whole amount of static current usage rate. The prime sources of variability are changes in: (i) changes in channel dimensions, (ii) changes in oxide thickness (iii) changes in channel doping profiles. Channel aspect of transistor in profound submicron technologies are subjected to the “classical” optical resolution bound. The 90 nm or 65 nm channel length is defined with wavelength of lower UV of 193 nm (or 157 nm). Static current expenditure has turn out to be extremely significant issue for the developers of lower submicron CMOS process and for designers of circuits. As the length of gate and threshold voltage reduces the subthreshold drain current rises significantly. Other components of the total static current consumption, such as gate tunneling currents, also come into existence. These issues have been covered in this work very effectively from designing perspective

Parametric Study of p-n Junctions and Structures for CMOS-Integrated Single-Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) have emerged as the primary solid-state photodetectors for use in time-resolved imaging and very low light optical detection for their high sensitivity, fast impulse response, and CMOS process compatibility. For each application, diode structure and size must be optimized empirically, where device performance is difficult to predict theoretically. To assist in this iterative design process, this paper presents side-by-side characterization of multiple SPAD structures implemented using different p-n junctions in a single, deep sub-micron CMOS process. Detailed characterization of the sensors enables comparative analysis of important performance parameters, such as dark count rate and spectral response, across multiple p-n junction types, device structures, and SPAD size variants. A new approach for experimental analysis of after-pulsing is also presented. The characterized SPAD test array comprises multiple size and structural variants implemented in a general purpose 180nm CMOS process.

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links.

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM's Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.

RNM Calculation of 6T SRAM Cell in 32nm Process Node based on Current and Voltage Information

Objectives: This work aims to analyze the the dependency of VDD, T and CR (Cell Ratio) on cell stability in terms of Read Noise Margin (RNM) in 32nm technology by the N- curve and butterfly graphical methods. The advantages of considering both voltage and current information for SRAM cell stability measurement have been reported. Methods/Statistical Analysis: The cell stability calculation of SRAM is a central concern in submicron CMOS process nodes, as they reason for increase in dies variability and voltage scaling. The cell Stability of the SRAM is typically calculated by Static Noise Margin (SNM). As it varies with different operating modes of a cell, a detailed analysis is required. In this article, the RNM of SRAM cell is computed by N curve, which compares with the SNM by bufferfly method. SRAM with PMOS access transistor for improved read stability and low voltage application is also presented. Findings: Results show that proposed SRAM gives 50% cell stability in read mode of operation over conventional SRAM cell for CR=3. Application/Improvements: The typical SRAM bit cell with PMOS access transistor shows improved read stability at low voltage application than standard SRAM cell.

The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach

With continued process scaling, CMOS has become a viable technology for the design of high-performance low noise amplifiers (LNAs) in the radio frequency (RF) regime. This paper describes the design of RF LNAs using a geometric programming (GP) optimization method. An important challenge for RF LNAs designed at nanometer scale geometries is the excess thermal noise observed in the MOSFETs. An extensive survey of analytical models and experimental results reported in the literature is carried out to quantify the issue of excessive thermal noise for short-channel MOSFETs. Short channel effects such as channel-length modulation and velocity saturation effects are also accounted for in our optimization process. The GP approach is able to efficiently calculate the globally optimum solution. The approximations required to setup the equations and constraints to allow convex optimization are detailed. The method is applied to the design of inductive source degenerated common source amplifiers at the 90 nm and 180 nm technology nodes. The optimization results are validated through comparison with numerical simulations using Agilent’s Advanced Design Systems (ADS) software.

Use It or Lose It

Moore's Law scaling continues to yield higher transistor density with each succeeding process generation, leading to today's many-core chip multiprocessors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep submicron CMOS process technology is marred by increasing susceptibility to wear. Prolonged operational stress gives rise to accelerated wearout and failure due to several physical failure mechanisms, including hot-carrier injection (HCI) and negative-bias temperature instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic, a single fault in the interprocessor network-on-chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this article, we study HCI- and NBTI-induced wear due to actual stresses caused by real workloads, applied onto the interconnect microarchitecture and develop a critical path model for NBTI-induced wearout. A key finding of this modeling is that, counter to prevailing wisdom, wearout in the CMP's on-chip interconnect is correlated with lack of load observed in the NoC routers rather than high load. We then develop a novel wearout-decelerating scheme in which routers under low load have their wear-sensitive components exercised without significantly impacting cycle time, pipeline depth, area, or power consumption of the overall router. A novel deterministic approach is proposed for the generation of appropriate exercise-mode data, ensuring design parameter targets are met. We subsequently show that the proposed design yields an ∼2,300× decrease in the rate of wear.

A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator

In this paper, a time-domain high-order ΔΣ analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order ΔΣ ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.

Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS

This paper describes design considerations for a digital inductive-switching DC/DC converter suitable for direct battery connection in a deep sub-micron CMOS process. Digital control techniques and robust circuit design methods take advantage of the advanced process technology while avoiding the barriers to direct battery connection and high efficiency, high power density voltage conversion. The approach is verified on a prototype converter, implemented in 40 nm standard bulk CMOS. The design achieves a peak efficiency of 95% for an input range of up to 5.5 V. The transient response is optimized for typical mobile SoC operating conditions and achieves step response times as fast as 35 μs/V under load.

Recent progress in the development of 3D deep n-well CMOS MAPS

In the deep n-well (DNW) monolithic active pixel sensor (MAPS) a full in-pixel signal processing chain is integrated by exploiting the triple well option of a deep submicron CMOS process. This work is concerned with the design and characterization of DNW MAPS fabricated in a vertical integration (3D) CMOS technology. 3D processes can be very effective in overcoming typical limitations of monolithic active pixel sensors. This paper discusses the main features of a new analog processor for DNW MAPS (ApselVI) in view of applications to the SVT Layer0 of the SuperB Factory. It also presents the first experimental results from the test of a DNW MAPS prototype in the GlobalFoundries 130 nm CMOS technology.

A true single-phase clocked flip-flop with leakage current compensation

A true single-phase clocked (TSPC) flip-flop, which compensates for the leakage current generated at dynamic nodes, is proposed to cover a wide operational frequency range in submicron CMOS processes. To implement the proposed TSPC flip-flop, three feedback circuits composed of a gated inverter (GI) are added to the conventional TSPC flip-flop. The GI is controlled by a clock and the internal signal of the conventional flip-flop, without an external control signal or a complementary clock signal. Furthermore, the strength ratio of the normal path to the feedback path does not need to be considered for the proposed TSPC flip-flop since the feedback circuit is only enabled when the dynamic node acquires a floating state. The proposed TSPC flip-flop is designed using a 1-poly 6-metal 65nm CMOS process with a 1V supply voltage. The simulation results show that the proposed TSPC flip-flop, which is optimized for normal operation at an operational frequency of 2GHz, exhibits an error-free operation at low operational frequencies such as 1MHz. The three added feedback circuits increase the power consumption by 8.8% as compared to that of the conventional TSPC flip-flop and occupy 12.28% of the proposed flip-flop.

Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Processes for Mixed-Signal Integrated Circuits

Many bipolar linear integrated circuits have been shown to exhibit enhanced low dose rate sensitivity (ELDRS), where a product may have worse total ionizing dose (TID) performance when exposed to ionizing radiation at a low dose rate (LDR) than when exposed at a high dose rate (HDR). Recent studies on test cells have suggested that submicron CMOS processes may also exhibit ELDRS. Some CMOS products, although not considered to be BiCMOS, do contain active bipolar elements using the parasitic bipolar structures present in all bulk CMOS processes. Three mixed-signal CMOS products, one digital-to-analog converter (DAC) and two analog-to-digital converters (ADC), using different submicron CMOS processes and using active parasitic bipolar structures were put through LDR TID testing to determine if actual products exhibit ELDRS. MIL-STD-883 TM1019 contains a test method to qualify products that fail HDR TID testing for LDR environments by using HDR testing along with a room temperature anneal. This test method was previously demonstrated on supermicron process nodes. It has been suggested that this test method is not valid for submicron processes. The test method was validated on a submicron CMOS product using the LDR test data from one of the products in this study.

Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp

Building on the technique of correlated level shifting (CLS), Split-CLS is introduced as a viable way to enable the design of high performance, high resolution A/D converters in deep submicron CMOS processes. One possible implementation of Split-CLS is presented, which achieves very high effective gain, and combines the fast, high efficiency charging of a zero-crossing based circuit (ZCBC) with the high-accuracy, low power settling of a double-cascode telescopic opamp. A dynamic zero-crossing detector (ZCD) conserves power in the ZCBC by only creating high bandwidth in the ZCD near the zero-crossing instant. Measured results are presented from a pipelined A/D converter fabricated in 0.18 m CMOS. Using the Split-CLS structure, an opamp with 300 mV output swing is used to produce a pipeline stage output swing of 1.4 V. The proof-of-concept test chip achieves 68.3 dB SNDR (11.1b ENOB) and 76.3dB SFDR while sampling at 20 MHz, and consumes 17.2 mW at 1.8 V supply.

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS Process

A 800μW 1GHz Charge Pump Based Phase-Locked Loop in Submicron CMOS ProcessDemand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. Technical possibilities for clock generation using classical oscillator based on a quartz filter is limited to tens of megahertz. Thus, 1 GHz clock generation is not possible without a frequency multiplier system. It is difficult to achieve, because in submicron process, where the integration of analog and digital blocks poses serious challenges. The proposed solution is a low power charge pump phase-locked loop (CPPLL) with the center frequency of 1 GHz. It combines various modern circuit techniques, whose main aim is to lower power consumption, which is below 800 μW for the whole PLL, while maintaining good noise properties, where the jitter rms is 8.87 ps. The proposed phase-locked loop is designed in 0.18 μm CMOS process.

Design and Performance of a DNW CMOS Active Pixel Sensor for the ILC Vertex Detector

The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. The chip has been designed in a 130 nm triple-well CMOS process and fabricated by STMicroelectronics. This first prototype includes a 16 times 16 DNW-MAPS matrix with sparsified readout architecture, an 8 times 8 matrix with digital output and selectable access to the analog output in each cell, and a 3 t 3 matrix with all the analog outputs available at the same time. The analog front-end has been characterized and the digital readout circuits have been successfully tested at frequencies up to 50 MHz. The circuit design and the performance of SDR0 are discussed in this paper.