Subthreshold Slope Values Research Articles

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt), Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Performance improvement of low-temperature a-SiGe:H thin-film transistors

This paper presents the study of an interface preparation procedure in the source/drain regions of the active layer, prior to deposit the n+ a-Ge:H contact layer in the fabrication process of low-temperature a-SiGe:H thin-film transistors. The devices were fabricated on corning 1737 substrates at 200°C. The improvement in metal–semiconductor interface by the interface preparation procedure was demonstrated. This interface improvement translates in higher mobility and better values of off-current, on/off-current ratio, subthreshold slope and threshold voltage.

Characteristic comparison of AlGaN/GaN enhancement-mode HEMTs with CHF3 and CF4 surface treatment

In this study, enhancement-mode (E-mode) AlGaN/GaN HEMTs that underwent CHF3 and CF4 plasma treatment beneath the gate metal were fabricated. These treatments were applied because, although previous studies have formed AlF3 compound layers after fluorine-based plasma treatment to suppress the polarization-induced charge density, the surface negative charges still influenced the device gate leakage current and trap density. In the device in this study, unlike in previous CF4 plasma-treated GaN E-mode devices, the hydrogen atoms of the CHF3 plasma were introduced to compensate for vacancies by donating an electron to a vacancy acceptor level, thereby reducing the number of vacancy induced traps. Based on the measured subthreshold slope (SS) and the effective interface state density (Dit) results, the SS value of a CHF3-treated HEMT was 80 mV/decade and the Dit was 1.23 × 1012 cm−2. Moreover, the CHF3-treated HEMT exhibited a current gain cut-off frequency, a maximum oscillation frequency, and an output power of 6.7, 26, and 14.8 dBm (302 mW/mm), respectively. The 1/f noise measurement results of the CHF3-treated HEMT indicated that the flicker noise-induced generation-recombination noise and gate leakage-induced generation-recombination noise were also improved. Therefore, the CHF3-treated HEMT has great potential for use in low-distortion power amplifiers and logic control circuits.

From planar to vertical nanowires field-effect transistors

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

Electrical-Stress-Induced Threshold Voltage Instability in Solution-Processed ZnO Thin-Film Transistors: An Experimental and Simulation Study

In this paper, we present the experimental and simulation results of the stress-recovery characteristics of solution-processed ZnO thin-film transistors under gate bias and current stress conditions. Under both stress conditions, we invariably observed a positive threshold voltage shift (Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> ) that is initially associated with changes in the values of subthreshold slope and off-current, which later becomes constant on prolonging the stress time. However, Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> was less for current stress, compared with gate bias stress. This stress-induced Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> is speculated to be caused by defect creation in the active layer and charge trapping at the semiconductor-dielectric interface. Following a stretched exponential model, at room temperature, a characteristics time of 1.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -3.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> s during stress and 7.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> -15.7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> s during recovery was obtained under all gate bias and current stress conditions. The Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> -time measurements performed under various temperatures yield an activation energy of ~ 0.5 and ~ 0.7 eV for the stress and recovery periods, respectively. The device simulation indicates that Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VT</i> is mainly caused by the increase in accept or like defects of the density of states in the ZnO channel layer. Furthermore, it was found that the deep lying states are responsible for the change in the value of inverse subthreshold slope.

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Improved Drive Current in RF Vertical MOSFETS Using Hydrogen Anneal

This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications. A hydrogen anneal at 800°C is shown to give a 30% improvement in the drive current of 120-nm n-channel transistors compared with transistors with out the hydrogen anneal. The value of drive current achieved is 250 μA/μm, which is a record for thick pillar vertical MOSFETs. This improved performance is obtained even though a sacrificial oxidation was performed prior to the hydrogen anneal to smooth the pillar sidewall. The values of subthreshold slope and DIBL are 79 mV/decade and 45 mV/V, respectively, which are significantly better than most values reported in the literature for comparable devices. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> anneal is also shown to decrease the OFF-state leakage current by a factor of three.

Analysis of subthreshold conduction in short-channel recessed source/drain UTB SOI MOSFETs

Abstract The subthreshold conduction regime in short-channel recessed source/drain (ReS/D) ultra-thin body (UTB) silicon-on-insulator (SOI) MOSFETs is studied. A physics-based model for the subthreshold slope of ReS/D UTB SOI MOSFETs is developed, based on an analytical solution of 2-D Poisson’s equation for the front-gate and back-gate potential distributions. In order to verify the accuracy of the model, the calculated subthreshold slope values are compared with the results obtained by Medici 2-D numerical device simulator over a wide range of different device structures, and very good agreement is obtained down to channel lengths of sub-30 nm. The model is given in explicit form without any fitting parameters and requires no iterative calculation, thus making it ideally suitable for fast prediction and evaluation of device design criteria for optimal scaling of the ReS/D UTB SOI MOSFETs.

Low-voltage solution-processed n-channel organic field-effect transistors with high-k HfO2 gate dielectrics grown by atomic layer deposition

High performance solution-processed n-channel organic field-effect transistors based on [6,6]-phenyl C61 butyric acid methyl ester with low operating voltages (3 V) are demonstrated using a high-k hafnium dioxide gate dielectric grown by atomic layer deposition. Devices exhibit excellent n-channel performance with electron mobility values up to 0.14 cm2/V s, threshold voltages of ∼0.3 V, current on/off ratios &amp;gt;105, and very low values of subthreshold slope (∼140 mV/decade).

Low-operating voltage organic field-effect transistors with high-k cross-linked cyanoethylated pullulan polymer gate dielectrics

The performance of organic field-effect transistors (OFETs) with high-k cross-linked cyanoethylated pullulan (CLCEP) polymer as a gate dielectric was studied. The optimized film spin-coated from the polymer blend showed high dielectric constant (13.4), high capacitance (53.4 nF cm−2, at 1 MHz), and negligible hysteresis enabling reliable and low-voltage OFET operations (−3V). With optimized cross-linking temperature, a field-effect mobility of 1.32 cm2V−1 s−1, an on/off current ratio (Ion/Ioff) of ∼105 and a threshold voltage (Vth) as low as −1.05 V were obtained. Also a low inverse subthreshold slope (SS) of 89 mV dec−1 was obtained which is close to the theoretical value of 57 mV dec−1 at room temperature. The number of trap states was estimated from threshold voltage shift and SS values, and was confirmed to be related to the OH intensities measured via FT-IR. The morphology and microstructure of the pentacene layer grown on CLCEP dielectrics were also investigated and correlated with OFET device performance.

Analysis of quasi double gate method for performance prediction of deep submicron double gate SOI MOSFETs

In this paper, we analyse for the first time the effectiveness of the quasi-double gate (QDG) method for performance prediction of short channel double gate (DG) silicon-on-insulator metal–oxide–semiconductor field-effect transistors (MOSFETs) over the entire operating region. An analytical model has been developed to explain the abnormally low values (≪60 mV/decade) of subthreshold slope that are obtained in QDG devices. We extract the low field mobility (μo), subthreshold slope (S), threshold voltage (Vth), transconductance-to-drain current ratio (gm/Ids) and peak transconductance (gm)max in linear and saturation regions for deep submicron QDG devices. We demonstrate that the QDG method can accurately predict gm/Ids, (gm)max and μo values for a deep submicron real DG device in the linear and strong inversion regions.

수소 처리시킨 N-채널 다결정 실리콘 TFT에서 스트레스인가에 의한 핫캐리어의 감지 특성

플라즈마, <TEX>$H_2$</TEX>와 <TEX>$H_2$</TEX>/플라즈마 공정에 의해 수소 처리시킨 n-채널 다결정실리콘 박막트랜지스터(TFT)를 제작하였다. 전압 바이어스 스트레스로 게이트 산화막에 유기된 감지 특성들을 분석하였다. 수소 처리시킨 소자에서 전기적 스트레스 조건에 의해 야기된 인자적 감지 특성들은 드레인전류, 문턱전압(Vth), 문턱전압 아래기울기(S), 그리고 최대 전달 컨덕턴스(Gm) 값을 측정하여 조사하였다. 분석 결과로서, 수소화 처리시킨 n-채널 다결정 실리콘 박막 트랜지스터에서 감지된 열화특성은 다결정실리콘/산화막의 계면과 다결정 실리콘의 그레인 경계에서 실리콘-수소(Si-H) 본드의 해리에 의한 현수 본드의 증가가 원인이 되었다. 게이트 산화막내 트랩의 생성은 채널 영역에서 게이트 산화막 속으로 핫 전자 주입에 의해 야기되었다. The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, <TEX>$H_2$</TEX> and <TEX>$H_2$</TEX>/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage(<TEX>$V_{th}$</TEX>), subthreshold slope(S) and maximum transconductance(<TEX>$G_m$</TEX>) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/<TEX>$SiO_2$</TEX> interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.

Electrical Instabilities and 1/f Noise in Organic Pentacene Thin Film Transistors

ABSTRACTWe report on the influence of Bias-Temperature Stress (BTS) on the pentacene Thin Film Transistors (TFTs) electrical characteristics and on their 1/f noise level. The gate BTS primarily affects the TFT threshold voltage, leaving both mobility and sub-threshold slope values almost unchanged. The degree of the threshold voltage shift induced by the positive or negative BTS depends on the TFT design and the BTS parameters. The current-voltage characteristics time dependence of the organic TFTs, subjected to the BTS, resembles that for amorphous-Si TFTs. The results of the 1/f noise measurements in the organic TFTs allowed us to conclude that the gate BTS primarily affects the TFT contact regions, resulting in the increase of both the contact noise and the contact resistance.