Subthreshold Region Research Articles

Guest editorial: Introduction to the special section on sustainable security solutions for Internet of Vehicles (VSI-iov)

A new current conveyor for Static Random Access Memory current sense amplifier is proposed for dual read bit-line cells. The first stage of sense amplifier is current conveyor that turns to a latch with substrate bias assistance, also reduces leakage during no sense period. Regenerative action is improved for faster latching action and operation at lower supply voltages. Simulation is performed using TSMC 65 nm, BSIM level 54 and results compared with the earlier suggested current sensing schemes. The proposed circuit consumes average power of 6.54µW for typical capacitance of 100fF bit-line and data-line capacitance and maximum power of 8.07μW at bit line capacitance as high as 200fF. Leakage current when sense amplifier is disabled, is only 80.4fA which is 2 × 10−5 × the latch-type circuit. The proposed circuit offers improved current sensitivity by 56% than the earlier suggested schemes and latching action at 0.2 V supply ensuring subthreshold SRAM operation. The delay of proposed circuit is just 12% of the conventional latch type circuit. Higher sensitivity of the proposed circuit ensures small memory cell size while maintaining basic stability and reliability. The proposed circuit was simulated for various memory sizes and 1 GHz clock frequency and exhibits reduced supply voltage operation, average power consumption, leakage power dissipation, immunity to temperature variation and memory size when compared with the earlier suggested sensing schemes.

A low leakage substrate bias-assisted technique for low voltage dual bit-line SRAM

A new current conveyor for Static Random Access Memory current sense amplifier is proposed for dual read bit-line cells. The first stage of sense amplifier is current conveyor that turns to a latch with substrate bias assistance, also reduces leakage during no sense period. Regenerative action is improved for faster latching action and operation at lower supply voltages. Simulation is performed using TSMC 65 nm, BSIM level 54 and results compared with the earlier suggested current sensing schemes. The proposed circuit consumes average power of 6.54µW for typical capacitance of 100fF bit-line and data-line capacitance and maximum power of 8.07μW at bit line capacitance as high as 200fF. Leakage current when sense amplifier is disabled, is only 80.4fA which is 2 × 10−5 × the latch-type circuit. The proposed circuit offers improved current sensitivity by 56% than the earlier suggested schemes and latching action at 0.2 V supply ensuring subthreshold SRAM operation. The delay of proposed circuit is just 12% of the conventional latch type circuit. Higher sensitivity of the proposed circuit ensures small memory cell size while maintaining basic stability and reliability. The proposed circuit was simulated for various memory sizes and 1 GHz clock frequency and exhibits reduced supply voltage operation, average power consumption, leakage power dissipation, immunity to temperature variation and memory size when compared with the earlier suggested sensing schemes.

Performance analysis of silicon nanotube dielectric pocket Tunnel FET for reduced ambipolar conduction

This work presents a novel structure of Nanotube Tunnel FET in which a high-k dielectric pocket is placed at the drain side to improve DC performance of the device. Using 3D TCAD simulation, it is shown that when a dielectric pocket (DP) is inserted at partially scaled drain region of Nanotube Tunnel FET at channel-drain interface then tunneling width at the output tunneling interface attains a maximum value for an optimum length and diameter of DP (i.e., 30 and 3 nm, respectively) which eventually reduces the ambipolar current up to a large extent. Furthermore, the subthreshold leakage current is also found to be reduced with the inclusion of DP in Nanotube Tunnel FET, thereby improving the current switching ratio (ION/IOFF). Additionally, the impact of varying k-value of DP on various DC parameters of the proposed device is demonstrated in this work and it is found that DP with high k-value reduces the ambipolar and subthreshold leakage current more as compared to the low-k DP. Moreover, the inclusion of DP dose not degrade the ON-state performance of Nanotube Tunnel FET as it has no significant impact on the rate of charge carriers tunneling through channel-drain interface during On-state.

A Novel 65 nm Active-Inductor-Based VCO with Improved Q-Factor for 24 GHz Automotive Radar Applications.

The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of −112.43 and −133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V.

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis

Accurate standard cell modeling is significant for circuit timing analysis and yield estimation. With voltage decreasing to near-threshold, cell delay distribution becomes asymmetrical and has a longer tail due to various process variation effects. In this brief, we propose a novel statistical model to fit the shape of the cell delay by using log-extended-skew-normal (LESN) distribution. It estimates the values of mean, standard deviation, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\sigma $ </tex-math></inline-formula> delay precisely by matching the kurtosis of the cell delay distribution. By changing the parameters of the LESN model, it can be used for up to the normal voltage region (1.1V) and down to the sub-threshold voltage region (0.4V). Considering the effect of load capacitances, the parameters of LESN distribution are further modeled so that the model can be used for different fanout constraints. Tested by INV, NAND2, and NOR2 with 28 nm technology, the average error of estimating the skewness is less than 6%, while the error for the kurtosis is less than 4%. Meanwhile, the average errors of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-3\sigma $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+3\sigma $ </tex-math></inline-formula> delay estimation are about 1.27% and 1.82% from 0.4V to 1.1V, respectively.

A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM

This paper presents a half-selected robust 12T bitcell with built-in write-assist for sub-threshold SRAM. The proposed 12T bitcell is robust enough in bit-interleaving architecture to enhance soft-error immunity combined with error correction code. The read stability of the proposed bitcell is improved by read decoupled. The writability is improved by data-dependent supply-cutoff write-assist. Both row and column f-selected bitcells can hold data stably during write operations. Simulation results based on a standard 55nm CMOS technology show that the read static noise margin of the proposed bitcell is 16.13x as that of the conventional 6T bitcell. Moreover, the write failure in the sub-threshold region is eliminated. In addition, the leakage consumption is improved by 15.7% compared with 6T bitcell.

A Computationally Efficient Model for FDSOI MOSFETs and Its Application for Delay Variability Analysis

This paper proposes a compact, physics-based current model for fully depleted silicon-on-insulator (FDSOI) MOSFETs and applies it to delay variability analysis. An analytical method is applied to avoid the numerical iterations required in the evaluation of surface potential, which directly improves the computational efficiency. The accuracy of the explicit surface potential approximation is 190.3 nV, which allows for fast convergence. Surface potential and current calculations achieve 1.8× and 1.4× acceleration compared with BSIM-IMG, respectively. To establish the relationship between delay and underlying process parameters, we introduce the effective current and propose a process variation-aware delay prediction model. Higher-order derivatives are calculated to compensate the nonlinearity of delay variations with respect to process parameters. Experiments show a significant improvement in the prediction accuracy with higher-order derivatives, which are proved to be able to handle nonlinearity under process variations. The front gate work function contributes the most to the nonlinearity of the delay variation and the accuracy of the third-order prediction is 4.07%. Under the variation in the channel length and width, front and back gate oxide thickness and body thickness, delay variations have similar characteristics and the second-order prediction is found to be sufficient to model the nonlinearity with a maximum relative error of 1.22%. The delay prediction model only requires a single-point HSPICE DC or transient simulation and is universal for different voltages and different cells. Compared with the Monte Carlo (MC) simulation, the accuracy of the first-order prediction in the above-threshold region (0.8 V) is 0.94%. In the sub-threshold region (0.3 V), a prediction accuracy of 2.01% can be obtained while achieving a 21× reduction in computational time.

AlN/GaN/InGaN coupling-channel HEMTs with steep subthreshold swing of sub-60 mV/decade

This work reports an AlN/GaN/InGaN high electron mobility transistor (HEMT) with a steep subthreshold swing (SS) of sub-60 mV/dec utilizing a coupling-channel architecture. The fabricated transistors show a negligible hysteresis, a SS of 39 mV/dec, a large gate voltage swing of &amp;gt;4.2 V, and achieving an excellent quality factor Q = gm/SS of 6.3 μS-dec/μm-mV. The negative differential resistance effect was found in the subthreshold region in the gate current–voltage (Ig–VGS) curve. The hot carrier transfer mechanism that occurred in the turn-on/pinch-off progress of the CC-HEMT under the dual-directional sweep, proved by the VDS- and Lg-dependent bi-directional transfer I–V characteristics, can be responsible for these excellent device performances. This work is believed to encourage further study of the AlN/GaN platform to power the future group III-nitrides CMOS technology.

A Sense Amplifier Based Modified Low Voltage Two Stage Flip-Flop with CNTFETs

The transformation from the event of enabling technology to the assembly of consumer-centric semiconductor products has empowered the designers to consider characteristics like robustness, compactness, efficiency, and scalability of the merchandise as implicit precursors. The Carbon Nanotube Field Effect Transistors (CNTFETs) are nowadays popular emerging technology. The paper proposes the sense amplifier-based two-stage flip-flop working within the sub-threshold region. the primary stage produces full swing conditional inputs for the latch stage. The proposed circuit has been designed using 16 CNTFETs. This circuit contains a significantly low clock load which reduces the power consumption. An improvement in the propagation delay and power delay product has also been achieved. Comparisons with other flip-flop designs manifest the robustness of the proposed circuit. The HSPICE software is used for simulating and verifying the theoretical results.

Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

An aggressively scaled triple self-aligned split-gate floating-gate (FG) NOR-type Dual-bit/cell (NORD) flash cell was studied and fabricated at 55-nm node technology. Both FG- and selected-gate (SG-) length, for the first time, were scaled down to sub-80 nm and sub-60 nm in NORD flash, respectively. In this paper, performance of aggressively scaled cells were demonstrated by measurements. Firstly, the cell’s characteristics were presented by discussing FG- and SG-transistor’s drain-induced barrier lowering (DIBL) effects and SG-FG coupling effect. It was experimentally revealed that excellent immunity of DIBL effect was still obtained in this highly scaled SG-transistor due to the fully isolated SG-channel. Then, optimization from process for FG-transistor had been discussed. It was shown that the properties of subthreshold region of FG-transistor has been improved by introducing dual pocket implants for the half-isolated FG-channel. Thirdly, reading biases were also studied to expand the window of read currents. A novel cell structure was also proposed to further improve the aggressively length-scaled NORD flash cell without sacrificing bit-area. Finally, the reliability characteristics were also presented.

Threshold damage mechanisms in brittle solids and their impact on advanced technologies

Threshold damage mechanisms in brittle covalent–ionic solids are outlined. Fracture and deformation modes are analyzed in terms of classical contact mechanics. Distinctions are made between brittle, ductile and quasiplastic mechanisms in both axial and translational contact. Special attention is devoted to the relatively unexplored subthreshold region where macrofracture is largely suppressed, a region of increasing relevance in the relentless move toward ever smaller devices and precision shaping technologies in the manufacturing sector. Cross-section micrographic images illustrate the fundamental nature of shear events within the hardness deformation zone responsible for crack initiation and propagation. Basic analytical relations for the strengths of surfaces with contact-induced damage in the postthreshold and subthreshold regions are presented, with emphasis on concept rather than fine detail. Strength data for a prototypical brittle material after sharp-indenter damage are presented to highlight the vital role of microstructure in determining transitions between brittle and quasiplastic responses. Pristine defect-free solids are shown to be highly vulnerable to contact damage, even in the subthreshold region. Heterogeneous solids with granular microstructures have lower initial strengths, but are more flaw tolerant. Brittle solids are also highly susceptible to degradation by surface removal processes in wear and machining settings, to a large extent depending again on microstructure. Implications of these findings concerning advanced technological applications of covalent–ionic solids are discussed.

Leakage Current Stability Analysis for Subthreshold SRAM

Low-power memories typically operate in the subthreshold region of the device; however, as the supply voltage continues to decrease, the impact of leakage current on SRAM stability becomes more significant. The traditional method of measuring static noise tolerance only considers the effect of voltage, and the measurement results are not accurate enough. Therefore, this paper proposes a leakage-current-based stability analysis that provides better metrics, reads current noise tolerance (RINM) and writes current noise tolerance (WINM) to measure the stability of subthreshold SRAMs. Both currents and voltages were taken into account. The results demonstrate that the method is more accurate than the conventional method under subthreshold levels.

2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory

This article presents a low random noise, a low-power, and a high-speed 2-mega pixels (Mp) global-shutter (GS)-type CMOS image sensor (CIS) using an advanced dynamic random access memory (DRAM) technology. GS CIS is one of the alternatives to solve image distortion issues caused by a conventional rolling-shutter (RS) CIS operation, since a 2-D image data can be simultaneously sampled by the in-pixel analog memory. To achieve a high-performance GS CIS, we proposed a novel architecture for digital pixel sensor (DPS) which is a high-speed GS operation CIS with a pixel-wise analog-to-digital converter (ADC) and an in-pixel digital memory. The major technologies of the proposed DPS can be summarized as follows: 1) two large coupling capacitors with mature DRAM technology; 2) extremely narrow pitch Cu-to-Cu (C2C) bond; and 3) finally low-powered ADC with a near sub-threshold operation. A perfect auto-zero operation for ADC is implemented using two DRAM capacitors, and a large number of transistors have to be integrated in the single pixel for realizing pixel-level ADC. Thus, each pixel has two fine-pitch C2C interconnections. This makes it possible to realize wafer-level stacked unit pixel. The proposed DPS with low-power consuming analog circuits has been successfully designed and developed for extremely fast-readout speed of max. 1200 frames per second (fps) and high sensitivity for low-illumination conditions.

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

We demonstrate SONOS (silicon-oxide-nitride-oxide-silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt; 10\times $ </tex-math></inline-formula> gain in energy efficiency over state-of-the-art digital and analog inference accelerators.

The Design Considerations and Challenges in MOS-Based Temperature Sensors: A Review

This review paper categorizes the state-of-the-art MOS (metal oxide semiconductor)-based temperature sensors according to their thermal sensing principles, including: type I, the logic, saturation and linear MOS-based temperature sensors; type II, the subthreshold MOS-based temperature sensors; and type III, the gate leakage-based temperature sensors. It also discusses in detail the design considerations and challenges of MOS-based temperature sensors, in terms of area, energy efficiency, supply voltage, inaccuracy, noise, as well as process and power supply variations. Based on the aforementioned discussions, the paper concludes that the future MOS-based temperature sensors will mostly likely be based on subthreshold MOS operation, with better trade-offs between area, energy efficiency and accuracy, and with reduced power supply sensitivity and level, as well as a lower-cost, fewer-point calibration method.

A Sub-1-V CMOS Voltage Reference with High PSRR and High Accuracy

This paper presents a novel sub-1-V CMOS voltage reference with high power supply rejection ratio (PSRR), low line sensitivity, and low supply voltage. CMOS voltage references available in the literature use a self-biased cascode branch consisting of two MOS transistors operating in the subthreshold region to generate the proportional-to-absolute-temperature (PTAT) voltage only, whereas extra circuitry is required to generate the complementary-to-absolute-temperature (CTAT) voltage for temperature compensation. But in the proposed sub-1-V CMOS voltage reference, both the PTAT and CTAT voltages are generated using a single self-biased cascode branch. Two operational amplifiers in negative feedback topology are used to convert the PTAT and CTAT voltages into PTAT and CTAT currents, respectively, which help to enhance the stability and PSRR of the proposed voltage reference. The proposed voltage reference has been designed and simulated in 180-nm standard CMOS technology using Cadence Virtuoso Analog Design Environment. The proposed voltage reference achieves an output reference voltage of 424.85[Formula: see text]mV with a temperature coefficient of 29.5[Formula: see text]ppm/∘C for the temperatures ranging from [Formula: see text]C to 125∘C at a supply voltage of 0.8[Formula: see text]V. A line sensitivity of 0.0035%/V is achieved for the supply voltage varying from 0.8[Formula: see text]V to 5[Formula: see text]V at nominal temperature (27∘C). A PSRR of [Formula: see text]91.69[Formula: see text]dB is observed for the frequencies ranging from 1[Formula: see text]Hz to 10[Formula: see text]kHz at nominal conditions without using any capacitive filter. Also, the output noises of the proposed design at nominal conditions for the frequencies of 1[Formula: see text]Hz and 10[Formula: see text]kHz are obtained as 2.37[Formula: see text][Formula: see text]V/[Formula: see text]Hz and 45.26[Formula: see text]nV/[Formula: see text]Hz, respectively.

A current reference with wide temperature operation range and low temperature drift

This work introduces a current reference with wide temperature operation range and low temperature drift, which can be used in high-performance intelligent power driver ICs. The core idea of the design is to use the non-linear characteristics of the drain current of MOSFET working in the sub-threshold region to realize the compensation of the reference current in low temperature and high-temperature section, then to reduce the fluctuation of reference current in the whole temperature range (TR). Compared with conventional structures, the temperature drift coefficient of this design is reduced by one order of magnitude. The proposed circuit is designed and verified under a 0.18 μm BCD technology, which occupies a footprint of about 0.085 mm2. Measured data shows that the output reference current at 1 μA has a temperature coefficient of 53.5 ppm/℃ during TR of −40–150℃.

Interfacial charge analysis and temperature sensitivity of germanium source vertical tunnel FET with delta-doped layer

The influence of interface trap charges (ITCs) and reliability of the Germanium source vertical tunnel field effect transistor with delta-doped layer (GSDD vTFET) is investigated in this paper. The analysis is carried out on the GSDD vTFET by evaluating the analog/RF performances under the consideration of donor and acceptor ITCs and temperature variations. The presence of interface trap charges at the silicon channel/gate oxide interface changes the flat-band voltage, affecting the analog and RF performances of the GSDD vTFET. The study is carried out at distinctive donor and acceptor interface trap charges. The findings indicate that as the interface trap charge densities increases, the device's output changes drastically. The off-state current of the GSDD vTFET deteriorates significantly from an order of 10−14 A to 10−8 A in the presence of positive ITC of 1012/cm2. The temperature variations over a wide range shows that OFF-state current as well as subthreshold region gets deteriorated due to dominance of Shockley–Read–Hall effect and the superthreshold region is less affected owing to dependence of band-to-band tunneling. The results reveal that when the temperature is raised from 200 K to 400 K, the ION/IOFF current ratio degrades tremendously from ~1014 to ~108 in the existence of donor ITC. It is also observed that the GSDD vTFET is less susceptible to acceptor interface trap charge in comparison with donor ITC in a temperature sensitive environment. Quantum correction (QC) of GSDD vTFET with ITC shows the same type of variations as the condition without considering QC.

5-nm Gate-All-Around Transistor Technology With 3-D Stacked Nanosheets

A comprehensive computational study of gate-all-around (GAA) devices with 3-D stacked silicon nanosheets (also known as nanoribbons or nanowires) is presented in this article. Technology development guidelines are provided for low-power applications in 5-nm CMOS technology node and beyond. The 3-D stacked nanosheet devices lower the subthreshold swing, drain-induced barrier-lowering, and subthreshold leakage current by up to 20.75%, 38.89%, and 88.53%, respectively, when compared to a silicon-on-insulator (SOI) FinFET with 5-nm physical gate length and identical silicon area at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DD}} = {0.6}$ </tex-math></inline-formula> V and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T} = {80}\,\,^{\circ }\text{C}$ </tex-math></inline-formula> . The voltage gain of a minimum-sized CMOS inverter is increased by up to 157% with the 3-D stacked nanosheet devices, thereby providing robust operation with wider noise margins when compared to the SOI-FinFET technology. Furthermore, by scaling the supply voltage to 0.49 V, the energy consumption of a CMOS inverter is reduced by 53.81% with the GAA 3-D stacked nanosheet devices while providing similar output transition speed when compared to the SOI-FinFET technology.