Sub-10nm Node Research Articles

Work Function Tuning in Strain Induced Double Gated Junctionless Transistor: A Device to Circuit Performance Study for Sub-20nm Nodes

Work Function Tuning in Strain Induced Double Gated Junctionless Transistor: A Device to Circuit Performance Study for Sub-20nm Nodes

Power Reduction in Advanced Technology Nodes Using Multi-Bit Flip-Flops and Banking Techniques in Physical Design

As technology advances into sub-10nm nodes, power consumption remains one of the most challenging constraints in VLSI (Very Large Scale Integration) designs. In this paper, we explore how multi-bit flip-flops (MBFFs) and multi-bit banking techniques can be used effectively to achieve significant power reduction while maintaining high performance and low area overhead. Through extensive simulation results and design comparisons at 7nm and 5nm technology nodes, we show that MBFFs combined with optimized banking provide a compelling solution for power efficiency. Our findings demonstrate that these techniques reduce dynamic power consumption by up to 30% compared to traditional flip-flops, without significant performance degradation. This research highlights the potential of combining architectural changes with advanced node design considerations to enable energy-efficient systems.

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

A Voting Approach for Adaptive Network-on-Chip Power-Gating

Scalable Networks-on-Chip (NoCs) have become the standard interconnection mechanisms in large-scale multicore architectures. These NoCs consume a large fraction of the on-chip power budget, where the static portion is becoming dominant as technology scales down to sub-10nm node. Therefore, it is essential to reduce static power so as to achieve power- and energy-efficient computing. Power-Gating as an effective static power saving technique can be used to power off inactive routers for static power saving. However, packet deliveries in irregular power-gated networks suffer from detour or waiting time overhead to either route around or wake up power-gated routers. In this article, we propose <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fly-Over (</i> <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flov</small> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">)</i> , a voting approach for dynamic router power-gating in a light-weight and distributed manner, which includes <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flov</small> router microarchitecture, adaptive power-gating policy, and low-latency dynamic routing algorithms. We evaluate <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flov</small> using synthetic workloads as well as real workloads from PARSEC 2.1 benchmark suite. Our full-system evaluations show that <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Flov</small> reduces the power consumption of NoC by 31 and 20 percent, respectively, on average across several benchmarks, compared to the baseline and the state-of-the-art while maintaining the similar performance.

Single Event Transients in Sub-10nm SOI MuGFETs Due to Heavy-Ion Irradiation

We compare and report in this work heavy-ion irradiation induced single event transients (SETs) in sub-10nm node SOI multiple gate FETs with the help of calibrated 3-D TCAD simulations. Our analysis includes the nanosheet FET (NSFET), nanowire FET (NWFET), and FinFET along with two different device design modes based on the doping profiles, namely the inversion (INV) and junctionless mode (JL). We have also analyzed the impact of heavy-ion strike direction and angle of incidence on SET performance of various MuGFETs. Heavy-ion induced SET current has also been compared for multiple-sheet/wires of NSFET and NWFET. In addition to this, different locations of heavy-ion strike have also been considered in this work. Further, we have collated the simulation trends to propose empirical models that predict the impact of heavy-ion radiation on various MuGFETs. Our models include some of the device design parameters and heavy-ion exposure conditions as the input to the model. The proposed models are shown to correlate well with the TCAD simulation results for the set of model parameters that we have reported here. These models not only expedite the analysis, but these can also accurately predict SETs in advanced MuGFETs under heavy-ion irradiation.

Improved leakage current and device uniformity for sub-20 nm N-FinFETs by cryogenic Ge pre-amorphization implant in contact

Improved leakage current and device uniformity for sub-20 nm N-FinFETs by cryogenic Ge pre-amorphization implant in contact

A Novel Fabrication of Vertically Stacked Gate-all-around Silicon Nanowire Arrays

It is well known that the top-down fabricated gate-all-around (GAA) silicon nanowire transistor with vertically stacked arrays is promising candidates to replace Finfet devices in sub-10nm nodes. The structure offers optimal electrostatic control, thereby enabling ultimate CMOS device scalability. Silicon nanowire (SiNW) transistors have shown promising potential to revolutionize the area of electronic, optical, chemical, and biological device applications. However, the fabrication of vertically stacked SiNW arrays in a controllable manner remains challenging due to complex topography and geometry characteristics. Top-down controlled nanowire patterning methods have been developed mostly by Bosch-based process combined with successive stress-limited oxidation. Recently, a more controllable method has been demonstrated to fabricate stacked horizontal nanowires using an epitaxial growth such as Si/SiGe/Si/SiGe structures, but the process requires careful heteromaterial interface handling. In this work, we propose a simple top-down method to fabricate vertically stacked nanowires arrays on bulk silicon substrates by originally developed process based on a conventional etch tool. Then, the stress-limited oxidation process can be introduced to achieve a uniform shape in a controllable fashion from a bulk silicon wafer. And also, we will discuss some challenges and innovations associated to such structure fabrications. Figure 1

Mark van de Kerkhof: Enabling sub-10nm node lithography: presenting the NXE:3400B EUV scanner with improved overlay, imaging, and throughput

Mark van de Kerkhof: Enabling sub-10nm node lithography: presenting the NXE:3400B EUV scanner with improved overlay, imaging, and throughput

Ben Tsai: Inspection and Metrology to Support the Quest for Perfection: Photolithography for the Sub-10nm Nodes

Ben Tsai: Inspection and Metrology to Support the Quest for Perfection: Photolithography for the Sub-10nm Nodes

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in Ion/Ioffand reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm FinFETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation.

Middle of Line (MoL) Cleaning Challenges in Sub-20nm Node Device Manufacturing

In advanced technology nodes (sub 20nm), the gate &amp; active contact architecture has become very complex. This architecture not only introduced new materials but also integrated additional patterning mask layers. This necessitated a separate Middle of Line (MoL) zone whereas conventionally contact integration used to be a Front End of Line (FEoL) process. This paper discusses wet cleaning challenges in MoL that were unforeseen with conventional contact architecture. Typical chemistries such as Sulfuric Peroxide Mixture (SPM), dilute Hydrofloric Acid (dHF), Aqua Regia, Standard Clean 1 (SC1), etc. that were used for contact cleaning or in salicidization process are found to be too aggressive due to smaller process window, shrinking Critical Dimensions (CD), and other challenges arising from overall tighter tolerances. As a result of device scaling, most of the MoL mask patterning is done with immersion lithography and double patterning techniques such as Litho-Etch Litho-Etch (LELE) are also needed. Immersion lithography is very sensitive to pre-litho backside and frontside particles which make pre-litho cleaning in MoL very critical as well. Also due to lack of high aspect ratio features in MoL (mostly contact holes), physical particle removal techniques such as droplet spray and MegaSonic can be very effectively used to achieve higher Particle Removal Efficiency (PRE). This paper summarizes such different scenarios &amp; related challenges.

Design and development of low activation energy based nonchemically amplified resists (n-CARs) for next generation EUV lithography

Design and development of low activation energy based nonchemically amplified resists (n-CARs) for next generation EUV lithography

(Invited) TmSiO As a CMOS-Compatible High-k Dielectric

High-k/metal gate stacks have been a core enabler of CMOS technology for almost a decade, allowing sub-nm equivalent oxide thickness (EOT) while keeping the gate leakage current density at acceptable levels [1]. State-of-the-art high-k/metal gate stacks employ a Hf-based high-k dielectric (typically HfO2) deposited on top of a thin interfacial layer (IL), which usually consists of chemical oxide (SiOx) and whose presence is crucial in order to guarantee the overall electrical quality of the gate stack [2]. It has indeed been shown that a thinner IL, while desirable from the point of view of EOT scaling, leads to problematic degradations in channel mobility [3], threshold voltage control [4], and device reliability [5]. Further scaling of high-k/metal gate stacks has been a central subject in recent research, and is usually addressed by replacing HfO2 with a higher-k material and/or by replacing SiOx with a high-k IL. The latter strategy is especially interesting, since the IL contributes ~1/2 of the total EOT of a scaled gate stack and since there are viable options to replace SiOx with a dielectric exhibiting significantly higher dielectric constant (~3x), whereas the same is not true for higher-k dielectrics. Lanthanide silicates have especially been shown to provide controllable thickness of the IL in the sub-nm regime and device-grade interface state density, rendering them extremely interesting as a potential replacement for SiOx IL [6]. Careful consideration of the material properties from the point of view of achieving controllable and reproducible formation of a sub-nm interfacial layer has led to the identification of thulium silicate (TmSiO) as a promising candidate IL for sub-10nm CMOS nodes. A straightforward process flow, compatible with industry-standard gate-first and gate-last integration schemes, has been demonstrated for integration of TmSiO in a high-k/metal gate stack, achieving EOT of the IL of 0.25±0.15 nm and interface state density ~1·1011 cm-2eV-1 [7]. Integration of TmSiO in Hf-based gate stacks has also been shown to be compatible with threshold voltage control techniques commonly used in gate-first and gate-last integration schemes [8], and gate-last MOSFETs achieving sub-nm EOT, 10 year device reliability and higher mobility than state-of-the-art SiOx/HfO2 devices have been demonstrated [9-10]. Replacing the SiOx IL with TmSiO can be especially advantageous in terms of channel mobility and device reliability, since both device properties have been shown to degrade strongly with decreasing IL thickness. Reliability in TmSiO/HfO2 MOSFETs has been investigated from the point of view of time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI), achieving expected lifetimes of 10 years for both nFETs and pFETs at EOT~0.8 nm and gate voltage ~1V (compatible with supply voltage in sub-10nm CMOS nodes). The effect of TmSiO on channel mobility has been analyzed by measuring electron mobility at high temperature and after constant voltage stress and comparing the observed trends with published data on SiOx/HfO2 devices, with the conclusion that replacing the SiOx IL with TmSiO can improve mobility by 20% at high effective field due to reduced remote phonon scattering. In this talk, the main advantages and challenges in the adoption of TmSiO as interfacial layer in scaled CMOS technology nodes will be addressed. [1] K. Mistry et al., IEDM Tech. Dig., pp. 247–250, 2007. [2] T. Ando, Materials, vol. 5, no. 3, pp. 478–500, 2012. [3] L.-Å. Ragnarsson et al., Int. Symp. VLSI Technol. Syst. Appl., 2011. [4] T. Ando et al., IEEE Electron Device Lett., vol. 34, no. 6, pp. 729–731, 2013. [5] E. Cartier et al., IEDM Tech. Dig., pp. 441–444, 2011. [6] T. Kawanago et al., IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 269–276, 2012. [7] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3271–3276, 2013. [8] E. Dentoni Litta et al., Solid-State Electron., vol. 108, pp. 24-29, 2015. [9] E. Dentoni Litta et al., IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 934–939, 2015. [10] E. Dentoni Litta et al., IEEE J. Electron Devices Soc., vol. 3, no. 5, pp. 397–404, 2015.

(Invited) Beyond-CMOS Device and Interconnect Technology Benchmarking Based on a Fast Cross-Layer Optimization Methodology

Moore’s Law scaling has last for almost half century, leading to a tremendous performance/area improvement and cost reduction. Unfortunately, in the past decade, severe challenges have been faced by the CMOS technology as the technology node enters sub-100nm region. To sustain the growing transistor performance and density, many novel device technologies are proposed in the past decade to augment or even replace the conventional Si CMOS technology with Cu interconnect. For the device innovation, ever since the discovery of graphene with excellent physical and electrical properties, much interest has been drawn in the electron-device community and graphene-based FETs have been introduced. Based on the property of the angular dependent transmission probability of electrons observed in GPNJs, an enhanced device structure is presented. More elaborate physical models are also developed to better evaluate the upper limit of delay and power consumptions of GPNJ circuits, including ON resistance, leakage current, contact resistance, and footprint area. For the low-power applications, TFETs show promise in overcoming the power wall faced by thermionic FETs by allowing significant reduction in the supply voltage. The analytical device-level models for TFETs are developed to efficiently evaluate the overall system-level metrics. It is demonstrated that the IV characteristics of a TFET behaves like a Si CMOS switch, but it provides much lower leakage current and ultra-low supply voltage at the cost of low ON current. For the interconnect technology, as the conventional Cu interconnect scales, the resistance per unit length increases dramatically because of 1) the smaller cross-sectional area and 2) the severe size effects at sub-20nm nodes. To alleviate the interconnect challenge, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed and benchmarked against their copper counterpart in terms of energy and energy-delay product. Alternatively, carbon-based interconnects, such as graphene sheets and carbon nanotubes, are also potential candidates because of their outstanding electrical properties. However, graphene is a two-dimensional structure, and increasing the interconnect pitch does not lower the resistance as fast as it does in copper interconnects. Hence, comparing graphene and copper interconnects strongly depends on the interconnect pitch. As a result, system-level analyses are essential to better understand and evaluate the overall benefits of graphene interconnects. Different from existing system-level performance simulators that are based on cycle-accurate simulations, the present methodology employs three hierarchies of compact analytical models on material, device and interconnect, and system levels, respectively. Significant acceleration is achieved in the simulation speed, making multi-parameter optimization feasible. This run-time efficiency is crucial because many novel device concepts have fundamentally different operational principles, and their on/off currents and input capacitances vary drastically in accordance with their design parameters. This methodology allows technologies to evaluate various trade-offs among key design parameters and to maximize the overall chip throughputs or energy efficiencies of processors in a highly efficient way. For the validation of the proposed methodology, simulation results are compared and well matched with eight commercially available Intel multi-core processors across three technology generations from 65nm to 32nm technology nodes. For the GPNJ-based processors, the proposed design methodology is applied to efficiently perform device-, circuit-, and system-level co-optimization. For given power density and die size area budgets, various device-level parameters, including supply voltage, control voltage, gap distance, and oxide thickness, are optimized for a GPNJ core, where 2.1X throughput improvement is observed for a sharp-corner GPNJ core. This advantage is predominantly because of the smaller output resistance, which reduces both device and interconnect delay and saves the power for repeaters. For the TFET based processors, the results indicate that TFETs have excellent performance at the low power density range due to the low supply voltage. The limitations imposed by the interconnects and the large leakage current at high supply voltage restrict the driving current, leading to a lower performance of the TFETs at a high power density. For the emerging interconnect technology, the proposed Al-Cu hybrid interconnect technology is evaluated by replacing short narrow local signal interconnects by Al interconnects. Six interconnect architecture options are analyzed and their optimal aspect ratio and chip frequency are predicted for five technology generations. The optimization and benchmarking results indicate that the potential improvement in chip clock frequency can be between 50 to 100% for the 7nm technology node. A comprehensive optimization/benchmarking is also performed for the multi-layer graphene interconnects. The results show that a single core using graphene interconnects have a higher throughput within the same power density and die size area because of the power saving offered by the low capacitance graphene interconnects.

(Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics

Triple-gate finFET manufacturing implementation has been successfully enabling continuance of CMOS scaling and Moore’s law [1], but it faces increased scaling challenges for sub-10nm nodes. Gate-all-around (GAA) nanowire (NW) FETs with the thin-body of the device, in a lateral or vertical configuration, fully wrapped around by the gate can be considered the ultimate scaling limit of finFETs [2-4]. They have the potential to offer superior short-channel electrostatics, and are thus regarded as one of the most promising candidates to further support the CMOS roadmap. In this work, we report a comprehensive evaluation of these two different device architectures from a device and circuit perspective, focusing on the key topics of gate stack integrity, leakage, reliability and noise performance and on the impact of the process options used. For simplicity, all devices were built on SOI substrates, with GAA lateral NWFETs obtained via a fins release process at replacement metal gate (RMG) module, which is high density compatible, and wherein diluted-HF was used to remove the BOX under the fins in areas previously covered by the dummy-gates [while the rest of the wafer is covered by the inter-layer dielectric level-zero oxide (ILD0)]. The gate stack used consists of: interfacial layer (IL)-SiO2/HfO2 followed by the effective work function (EWF)-metal (TiN or a TiAl-based stack) and W fill-metal. Examples of TEM images taken across a wire (GAA-NWFET) or a fin (triple-gate finFET) after full processing are shown in Fig.1 [4]. Intrinsic transistor performance (ITP) characteristics show that GAA-NWFETs clearly outperform finFETs when normalizing ION-IOFF per footprint. Furthermore, an evaluation of several doping strategies for both type of devices, using ion implantation (I/I), allowed a comparison of inversion-mode (IM) FETs built with conventional junctions or an extensionless (Extless) scheme [4,5] vs. junctionless (JL) transistors [4,6]. To note that the latter are particularly advantageous in their process simplicity (no junction formation requirements) and compatibility with lower thermal budget flows. Reliability wise, optimized JL and Extless can be very attractive options thanks to a lower oxide field (Eox) at operating conditions. This is indeed confirmed by the GAA-NWFETs in Fig.2. Control of the lateral BOX recess during the fins release process in the GAA flow, and hence of the lateral bottom-gate overlap, is important not only for parasitic reasons but also for reliability purposes. Indeed, TCAD predicts a higher Eox at the bottom-gate edges in case of excessive lateral BOX recess which can lead to degraded BTI behavior for GAA-NWFET vs. finFET. The impact is however considerably less for Extless and JL, increasing the robustness of these devices against process variations in the lateral BOX recess. JL devices were also seen to have improved on and off state hot carrier (HC) reliability behavior as compared to other IM GAA-NWFETs [7]. Interestingly, improved subthreshold slope (SS) values after HC stress were also measured in some JL GAA-NWFETs as a result of the improved electrostatic control and the generation and location of acceptor type of interface traps in the wires of slightly concave sidewalls shape. Low-frequency (LF) noise analysis results suggest to a first order no significant impact of the device architecture on the gate stack integrity in regards to traps/defects. In addition, in agreement with BTI and HC results, JL GAA-NWFETs also show reduced noise. These characteristics, together with the devices smaller IOFF values yielding ring oscillators with substantially lower power dissipation, indicate JL can be an attractive option for low power circuits. Improvements in noise, reliability and mobility performance were also obtained in GAA-NWFETs by introduction of a TiAl-based EWF-metal [4,8], in line with the results previously reported in [9] on finFETs using Al diffusion mechanisms for EWF modulation.

Fan-in WLP: Technology and Market Trends

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&amp;D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

III-V Tri-Gate Quantum-Well Mosfet for 10nm Technology and Beyond

With sub-10nm node technology approaching fast, counteracting short channel effects (SCEs), sub-threshold conduction, reducing transistor off-current and gate leakage current have become aspects of real concern. Integration of III-V semiconductors in multigate device architectures has become a topic of intense research and study for low power logic implementation [1]. Multigate device architectures like FinFETs, GAA FETs provide better control over channel carrier accumulation and improved short channel performance over planar structures. Recently, In0.53GA0.47As Quantum-Well (QW) Tri-Gate MOSFET with bi-layer high-k dielectrics of Al2O3/HfO2 has been reported with channel width and height scaled down to 30nm and 20nm respectively and gate length scaled down to 60nm [2]. In this work, we present a simulation study of inversion Capacitance-Voltage (C-V) and Threshold (VTH) characteristics of a III-V tri-gate device (Fig.1 inset) using self-consistent modeling. The device structure used for modeling in this study incorporates 2nm Al2O3 with In composition kept at 0.7 in the undoped InGaAs QW channel. The In0.52Al0.48As back barrier thickness is kept at 60nm. In this study TiN has been used as the gate metal. In all these studies, temperature is considered to be fixed at 300K. Finite Element Method (FEM) has been used to solve Schrodinger-Poisson equations in a coupled manner applying proper boundary conditions, using COMSOL Multiphysics and MATLAB, taking into account wave function penetration and other quantum mechanical effects. 2D Schrodinger equation is solved using effective mass approximation and open boundary condition to determine electron wave functions and eigen states in the quantum well. Using carrier wave functions in the tri-gate channel, inversion carrier concentration is determined by applying 1D density of states and Fermi-Dirac distribution function. The effect of fixed oxide charges, interface trap charges and oxide border trap charges is not taken into account. The developed simulator is also benchmarked with the simulation results obtained for a III-V GAA nanowire transistor [3]. A quantum definition of threshold voltage for multigate FETs is available in literature [4]. According to this definition, the threshold voltage can be presented as a combination of classical and quantum terms. Here, peak electron concentration npeak(x,y) and average electron concentration navg are used to define threshold voltage of the device. At threshold point, the profile of npeak(x,y)/navg would show a change in slope which results from shift in carrier accumulation as device operation moves from subthreshold to inversion mode [4]. In this study, same definition of threshold voltage has been used. The simulation reveals strong carrier accumulation at the corners of the oxide/semiconductor interface which is expected for multigate device structures (Fig. 1). The simulation also reveals strong subband quantization in the QW channel (Fig. 2). Occupied subbands below the Fermi level contribute to the carrier concentration. As the device dimension is shrunk, volume inversion effect becomes more and more significant and carriers begin to accumulate at the middle portion of the tri-gate channel. This phenomenon leads to an increase in carrier concentration in the middle portion of the QW fin as channel dimension is scaled (Fig. 3). This phenomenon shifts channel formation towards the middle portion of the tri-gate QW fin. Simulation also reveals higher inversion capacitance at lower In composition in the channel which may be attributed to higher density of states effective mass at lower In composition (Fig. 4). Although variation of top gate oxide thickness reveals effect on inversion capacitance, the threshold voltage remains mostly unchanged with top gate oxide thickness. Study of variable channel dimension while keeping WFin=HFin reveals lower carrier accumulation in the device cross section per unit channel length which may lead to lower inversion capacitance with lower channel dimension (Fig. 5). Lowering channel dimension results in stronger quantum confinement and subband splitting which eventually leads to an increase in threshold voltage (Fig. 6). Lowered In composition in the channel also increases threshold voltage of the device (Fig. 6). In this work, a simulation study of a III-V tri-gate quantum well device for 10nm technology and beyond is presented. The outcome of this work would be useful in the implementation of III-V multigate device structures for high speed and low power logic applications.

Exploring the limits of scanning electron microscopy for the metrology of critical dimensions of photoresist structures in the nanometer range

Exploring the limits of scanning electron microscopy for the metrology of critical dimensions of photoresist structures in the nanometer range

Invited: SOI-Type Bonded Structures for Advanced Technology Nodes

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28nm and 22nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to 10nm node. Innovations will be necessary for lowest node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication (Fig. 1). High mobility materials are expected to replace silicon as the channel material: attention has been focused recently on the III-V and the Ge materials (Fig.1). Indeed, III-V semiconductors (such as GaAs, InP, InGaAs and InAs) have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass [3]. In order to avoid short channel effects, these “new” materials have to be transferred as thin layers on buried oxide layers. SOI substrates are fabricated using the Smart CutTM technology. This process, based on hydrogen implantation and wafer bonding, made it possible to transfer a thin layer of crystalline material from a donor substrate to another substrate. This versatile technique for thin layer transfer enables the fabrication of hetero-substrates with a large choice for the crystalline superficial layers, the buried layers and even the handle substrates (Fig. 2). For More Moore applications, this leaves the freedom to transfer Ge or III-V thin layer on an optimized buried oxide layer.In this paper, we will present our latest work on advanced SOI substrates for sub-28nm technology node and on novel “on insulator” substrates for sub-10nm node. We developed GeOI (Fig. 3) and InGaAs-OI (Fig. 4) substrates in 300mm. It is otherwise possible, thanks to low temperature direct bonding, to combine 3D CMOS integration (thereby increasing transistor density) and high mobility channel devices : a monolithic and vertical co-integration of GeOI pMOSFETs stacked on SOI nMOSFETs [4] or a III-V-OI nMOSFETs stacked on a SiGeOI pMOSFETs [5] have already been demonstrated with functional inverters and SRAM cells.Acknowledgments: the authors acknowledge financial support from the European Commission via the FP7-COMPOSE3 and from the French Government's Investissement d'Avenir program (eXact projet).[1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] S. Takagi, IEEE TED, 2008 [4] P. Batude, VLSI 2009 [5] T. Irisawa, VLSI, 2013.

Development of Silicon Polish on 450mm CMP Tool

It is becoming more difficult, as the semiconductor technology shrinks, to maintain historical cost reduction trends due to rapidly increasing technology complexities. The progression toward 450mm wafer integration is one of the greatest opportunities to both reduce the die cost and enable greener manufacturing. However, the raw wafer cost may increase by > 2X compared to the 300mm, and 450mm wafer reclaim chain can have a tremendous impact by limiting the number of new fabs built1. To make 450mm processes cost effective, we need to lower development costs on 450mm wafers by developing 450mm silicon polishing process to reclaim 450mm wafers. Transition of the CMP platform from 300mm to 450mm The major concerns of CMP process from 300mm to 450mm are considered to be the slurry distribution and the uniformity control by polish head. To fulfill the 450mm wafer planarization within a tight specification for sub-20nm nodes, some innovations or changes in both hardware and consumables are thought to be a must. The schematic view of figure 1 shows the concept of the transition. For example, more zone control is required for profile tuning; higher efficiency dressing or bigger disk design is required for compensating the extra pad size; higher slurry flow rate or multiple-slurry-dispenser is required for better slurry distribution. From the consumable perspective, the characteristics of slurry, e.g. the concentration of additive, may significantly affect the wafer uniformity which may not be seen in 300mm CMP process. Surely, pad groove design for better slurry distribution, lower slurry usage and sub-pad material selection for wafer uniformity are all key factors for 450mm CMP applications. Improvement of recycled wafer Based on the 450mm wet clean process results2, surface roughness might be an issue for specific film-stripped wafer, e.g. Poly-Si/SiO2 film or wafers with several wet clean processes history. To improve the surface roughness of those wafers, some CMP process sequences were evaluated. Here, bulk polish was fulfilled by fumed silica and buff polish was fulfilled by colloidal silica on one hard pad. SC-1 and H2O2 were used for the cleaning step. By increasing the buff polish down force, the surface roughness trends down slightly. The same trend can be seen if the process time increases from 1 min to 3 min at the buff polish down force of 2 psi. The roughness can be improved around one order (see figure 2). Regarding the particle performance after silicon CMP, particles can be reduced by increasing the buff polish time as shown in figure 3. However, the particle is extremely high when polishing wafers with bulk slurry. When the particle count of a full process (bulk and buff polish), is compared with buff only process, the difference is more than one order. The particles caused by bulk polish may remain before buff polishing. If the bulk polishing is required for improving some scratches, 2 steps polishing would be a reasonable idea to optimize the defect result. Further consumable study will be done for improve the recycled wafer to M76 specification.The data, charts, and illustrations in this paper were created by the authors.