Stress-induced Voiding Research Articles

Reliability of the hybrid bonding level using submicrometric bonding pads

Hybrid bonding is a major enabler for devices requiring 3D stacking with high interconnection density. An in-depth reliability study is performed for the specific Cu/SiO2 integration to identify the potential failure mechanisms. A high robustness is evidenced down to bonding pitch 0.81 μm for the standard reliability tests such as Thermal Cycling (TC) tests, High Temperature Storage (HTS) test, Stress induced Voiding (SiV), Time Dependent Dielectric Breakdown (TDDB) or electromigration. The hybrid bonding interface is stable under thermal stress with no atomic or ionic Cu diffusion observed through the hybrid bonding interface. The role of the thin self-formed cuprous oxide at the Cu/SiO2 interface in the case of misaligned bonding pads is believed to play a major role in the high robustness to reliability tests.

Examining fluid flow and solute transport through intersected rock fractures with stress-induced void heterogeneity

In this study, fluid flow and solute transport processes are assessed in three-dimensional (3-D) intersected rock fractures with stressed-induced void heterogeneity. Specifically, flow behaviors are examined in the intersected fractures with flow directions perpendicular and parallel to the intersection orientation. Then, transport behaviors are analyzed considering the classic continuous flow condition, and a new mixing ratio is proposed to better quantify the mixing process. Last, applicability of two-dimensional (2-D) representations of rock fractures for analyzing flow and transport is assessed by result comparison with the 3-D cases. The results show that fracture intersecting can enhance transmissivity of the single fracture as a result of locally enlarged aperture at the intersection and generation of more conducive flow paths, with latter being the main mechanism especially when under high stress. Moreover, it is found that transport behaviors can differ evidently in intersected fractures due to stress-induced void heterogeneity and anisotropy. For intersected fractures with obvious directional void heterogeneity, solute transport can become more nonuniform with occurrence of forced mixing caused by scattered flow channeling from the intersection. Compared to the actual 3-D cases, adopting the 2-D representations is generally found to produce transmissivity overestimation and mixing underestimation, due to inaccurate quantification of the 3-D flow and transport features. Considering the realistic stress-induced void heterogeneity for rock fractures, the findings of this work can further broaden our understanding of the flow and transport processes in underground fractured rock formations.

Physics-based simulation of stress-induced and electromigration-induced voiding and their interactions in on-chip interconnects

A novel physics-based simulation model of electromigration (EM) and stress-migration (SM) induced degradation of electrical characteristics of on-chip interconnects is developed based on the coupled evolution of stress and voiding resolved by means of finite element simulations (FEM). The void evolution tracked with the phase field methodology, is linked with the evolution of EM/SM induced stress, which are generated in the metal segments by the interaction of the inelastic deformations due to divergences of atomic fluxes with the rigid confinement. Accounted atomic exchange between the metal and void surface removes a limitation on the void volume conservation. Developed simulation methodology allows to predict effects of the metal segment architecture and geometry, metal morphology and texture, as well as atomic diffusivities along the variety of migration venues on voiding-induced degradation of interconnect electrical conductance. Results of performed simulation indicate that the pre-existed stress induced voids (SIV) can evolve under the action of applied electric current and affect interconnect reliability. The developed physics-based simulation methodology can help to address reliability concerns by optimizing the properties of interconnect materials and modifying the physical design of the interconnect layouts in order to achieve EM resistant on-chip interconnects.

An Experimental Study on the Thermal Stability of Mg2Si/Ni Interface under Thermal Cycling

Mg2Si is a promising eco-friendly thermoelectric material, and Ni is suited for electrical contact on it. In this study, Bi-doped Mg2Si ingots with Ni contacts were fabricated by co-sintering, and thermal stability was investigated by long-time (500 h, 500 cycles) temperature cycling from 25 °C to a peak temperature (Th = 400 and 450 °C) in N2. The as-sintered Ni/Mg2Si interfacial region is a multilayer consisting of Mg3Bi2, a series of MgxSiyNiz ternary compounds (ω, ν, ζ, and η-phases), and MgNi2. In the complex microstructure, the MgNi2 / η-phase interface was vulnerable to stress-induced voiding at Th = 450 °C, which arises from the mismatch of the thermal expansion coefficients. Interfacial voiding was avoided by adding 10 mol% Ag in Ni, which is probably due to the suppression of vacancy migration by the Ag-containing 2nd phase formation at the MgNi2/η-phase interface.

Stress Migration Modeling Using Probabilistic Physics of Failure

It is now well accepted that the unbiased isothermal resistance drift and latent open-via failures in Al and Cu metal interconnects is due to the formation and growth of stress induced voids (SIVs). While the basic description of SIV was established early on, it remains an important task to characterize process and design variations and their impacts on reliability. The physics-of-failure arises from the geometrical confinement and the mismatch in coefficients of thermal expansion of the back-end of line (BEOL) materials with subsequent diffusive relaxation. The basic physics must be updated to include the effects of patterned structural features, microstructure, elastic anisotropy, adhesion, and nonlocal interactions. Also, due to the relaxation of the stress with time, it is found that the failure rate diminishes as the driving force reduces, leading to a probabilistic immortality very similar to the Blech effect in electro-migration. However, in some cases, the approach to this saturation is very slow and some failures may “heal.” At great age, the cumulative failure (hazard) saturates the value which is proportional to the void initiation density. With the assumption of a non-zero surface energy, the observed reverse resistance drift can be modeled as well as the open failure recovery as a void sintering effect. From the probabilistic physics of the failure model for SIV, we can derive predictions of the failure-free lifetime and immortal fraction as well as scaling laws for linewidth, microstructure, film and via adhesion, and via-size. The model also provides some insight on the physics behind the super-redundancy effect of additional via placement. The model is fit to standard high-temperature storage (125 °C to 200 °C) data, as well as long-term (>3 years) data at 30 °C, from a 110-nm Cu/Ta/TaN/low-k BEOL process.

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 μm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.

Numerical Modelling of Interconnect Electromigration Under Non-DC Stressing Conditions

A numerical model of the equivalent time conversion to DC stressing for electromigration failures under various current waveforms is proposed based on the vacancy diffusion and damage healing theory. The Joule heating effect and the intrinsic stress-induced voiding are included in the calculation of interconnect reliability. The simulation results show that the cumulative lifetimes are strongly affected by current frequency and vacancy lifetime and a frequency shift to the right occurs for small vacancy lifetimes under AC stressing. For pulsed-DC stressing, the temperature rise dependent on the current frequency dominates the interconnect reliability. The average temperature rise due to Joule heating is reduced by two times when the frequency is larger than approximately the reciprocal of the thermal time of interconnect structures.

Finite element analysis of multi-level interconnection under cyclic thermomechanical loads

In manufacturing processing, using copper wire for connecting each micro-device and constructing logical circuit to reduce RC time delay is a major technique. However, during fabrication, the thermo-mechanical mismatch between materials generate high stress, which lead to stress-induced voids, cracks, and interface delamination, all of which we strongly affect the reliability of integrated circuits. This study utilizes materials mechanics, fracture mechanics, and the finite element method to analyze cracking and interfacial delamination of thin films and interconnect structures and to determine the strain energy release rate within such structures under cyclic thermal loading. In addition, parametric studies that analyze the influence of each physical parameter (e.g., temperature, geometry, and properties of low-k materials) on the stress, strain energy release rate, and crack growth. Based on these investigations, we optimize size parameters of the interconnect structure. The results show that mismatch of thermo-mechanical behavior between different materials and spaces on wires are significant factors for generating high stresses. It is also found that selecting the low-k materials with higher Young’s modulus and lower coefficient of thermal expansion can avoid caused high stress. The temperature range is on focus improve the reliability of interconnect structures, and variations energy release rate could prevent interfacial delamination of thin films.

Electromigration: Void Dynamics

The detailed knowledge of the void evolution is helpful to understand and interpret traditional electromigration (EM) lifetime experiments. As void formation and subsequent evolution is highly dynamic, an in situ observation experiment was employed using an SEM allowing for void detection down to a few nanometers in diameter. For void nucleation, it has been suggested that due to the large anisotropy in modulus in Cu, incompatible grain boundaries can act as stress concentrators for both stress-induced and EM-induced voiding. In addition, during growth, the shape change and migration have been associated with the microstructure. To better understand void formation and evolution, we examined the Cu microstructure using EBSD during the experiment without interruption. We tested interconnects consisting of Cu-based damascene (M1) drift type structures, capped with SiCN. Void formation could be confirmed to be associated with features such as incompatible grain boundaries in some instances. In other cases, triple points and grain boundary/sidewall intersections were found as void nucleation sites. Void growth and migration is found strongly correlated with the driving current density. We show conditions under which void migration takes place or is suppressed. In particular, a critical current density of approximately 10 $\mbox{mA}/\mu\mbox{m}^{2}$ is observed, below which no void migration occurs. At current densities of 15 $\mbox{mA}/\mu\mbox{m}^{2}$ and above, all voids migrated at a net drift velocity proportional to the current density. Independent of migration, all voids are observed to grow at rates consistent with published data for a mixed near bamboo microstructure and interface diffusion.

Detection and analysis of stress-induced voiding in Al-power lines by acoustic GHz-microscopy

The formation of voids in metal layers upon stress-induced migration is a well-known defect mechanism in integrated circuits. This phenomenon largely accelerates with increasing ambient temperature. Consequently, the occurrence and the growth of voids result in an increased electrical resistivity which once more leads to an acceleration of the growth rate highly impacting the reliability and the life span of the device. Technological improvements aim at the minimization of stress induced voiding. However, for understanding and optimization of process related factors non-destructive methods for screening and systematic monitoring of the void formation e.g. during stepwise reliability testing are required. In the current paper, the formation of voids induced by repetitive thermal loads has been assessed and evaluated semi-destructively by employing Scanning Acoustic GHz-Microscopy. Prior to the acoustic inspection, sophisticated semi-destructive preparation was required to provide access to the region of interest. Voids with sizes below the acoustic resolution limit have been detected. The relative number and the size of appearance have been analysed using a custom made analysis software tool.

Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field.

Effects of thicknesses of Si/Al/Si composite films and annealing temperature on metal-induced si crystallization efficiency, voids, and electrical properties

Specimens with amorphous silicon (a-Si)/aluminum (Al)/a-Si composite film were prepared to evaluate the effects of the thickness variation of these three film thicknesses and annealing temperature on the Al-induced crystallization (AIC) efficiency of a-Si and the quantity of stress-induced voids. These thin films were arranged in sandwich form for the purpose to improve the AIC efficiency via Al diffusions into the two adjacent Si films and reduce the defect of voids. The PC parameter is defined as the product of the crystalline fraction and the grain size of Si crystallization, and R* is a parameter defined as the area fraction of nanovoids in a unit area. The influence of these two parameters on Si crystallization is governed by the annealing temperature (T) and thus the stress change, σf –σan (σf : stress after annealing; σan : stress during annealing), and the thickness ratio, tAl/(tSi1+tSi3) (tAl: Al film thickness; tSi1, tSi3: thicknesses of the 1st and 3rd layers (a-Si), respectively). Si crystallization doesn't happen when tAl/(tSi1+tSi3) is less than 4% and the annealing temperature is lower than 600°C. The sandwich structure contains voids if tAl/(tSi1+tSi3) is greater than 6% and the negative stress change (σf –σan) is lower than −500MPa. A rise in σf –σan decreases R* but increases PC, if the specimens contain voids. The carrier mobility of specimen is elevated by increasing the negative σf –σan or the PC value. At a fixed PC, the carrier mobility of the specimen without forming voids is higher than that of the specimen with voids. The electrical conductivity of specimen increases with decreasing specimen band gap. Appropriate choices in the film thicknesses of the sandwich structure and the annealing temperature can increase the Hall carrier mobility and electrical conductivity to be much higher than those of the Al/a-Si structure.

Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms

Back-end wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework that contains modules for back-end time-dependent dielectric breakdown, electromigration, and stress-induced voiding is proposed to analyze circuit layout geometries and interconnects to estimate state-of-the-art microprocessor lifetime due to each mechanism. Our methodology incorporates the detailed electrical stress temperature, linewidth, and cross-sectional areas of each interconnect/via within the microprocessor system. Different workloads are considered to evaluate aging effects in single-core microprocessors running applications with realistic use conditions.

Comprehensive reliability and aging analysis on SRAMs within microprocessor systems

A framework is proposed to analyze the impact of both Front End of the Line (FEOL) and Back End of the Line (BEOL) wearout mechanisms on memories embedded within state-of-art microprocessors. Our methodology finds the detailed electrical stress and temperature of each SRAM cell within a memory by running a variety of standard benchmarks. Combining the stress/thermal profiles and the wearout models, the performance degradation of SRAM cells for each wearout mechanism is studied. The lifetimes of the SRAM cells are then obtained when the performance metric degrades to a predefined threshold. The proposed work introduces a method to deal with the large volume of SRAM cells whose stress is non-uniform by partitioning the SRAM cells into different stress states, and generates the lifetime distribution of the memory system due to each wearout mechanism by combining the lifetimes of the cells, whose distributions vary with the stress received. Seven wearout mechanisms have been studied, namely, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate oxide breakdown (GOBD), backend dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV).

Putting the past behind us: Social stress-induced urinary retention can be overcome

To study the pathophysiology of dysfunctional voiding, we have previously developed a model of stress-induced voiding dysfunction. We have shown that cyclosporine A (CsA), an inhibitor of the Ca(2+)-calmodulin complex, can prevent social stress-induced urinary retention. However, treatment with cyclosporine has not had an effect on the increase in the stress peptide corticotrophin-releasing factor (CRF) in Barrington's nucleus, which is involved in the micturition pathway. We now investigate whether cyclosporine administered after stress can reverse the abnormal voiding phenotype, and whether it has effects on the bladder wall itself, or on the stress response within Barrington's nucleus. Six-week old Swiss-Webster mice were exposed to aggressor males for 1 h a day, followed by 23 h of barrier separation. In a long-term trial, 1 month of stress was followed by single-cage housing for 6 months. In a separate CsA reversal trial, mice either received CsA in drinking water or had plain drinking water during 1 month of single-cage housing during recovery. Bladder contractile function was examined on a Guth myograph. Nuclear translocation of myocyte enhancing factor (MEF)-2 and NFAT (nuclear factor of activated T cells) in the bladder was assessed using electrophoretic mobility shift assays (EMSAs). The expression of CRF was determined in Barrington's nucleus using in situ hybridization. Voiding dysfunction persisted for up to 6 months after stress exposure while mice recovered in single-cage housing. In the CsA reversal trial, voiding patterns improved when they received CsA in water during single-cage housing following stress, whereas those that underwent single-cage housing alone had persistent abnormal voiding (Fig. A). There was no difference between CRF levels in Barrington's nucleus between reversal groups (p = 0.42) (Fig. B), possibly indicating a direct effect on the bladder rather than a persistent stress effect. There were no differences in the contractility of bladder wall muscle. CsA decreased the nuclear translocation of MEF-2 and NFAT induced by stress (Fig. C,D). CsA reverses stress-induced urinary retention, but does not change the stress-induced CRF increase in Barrington's nucleus. Furthermore, bladder smooth muscle contractility is unchanged by CsA; however, there are changes in the levels of the downstream transcription factors MEF-2 and NFAT. We suspect that additional CsA responsive neural changes play a pivotal role in the abnormal voiding phenotype following social stress.

Role of W and Mn for reliable 1X nanometer-node ultra-large-scale integration Cu interconnects proved by atom probe tomography

We used atom probe tomography (APT) to study the use of a Cu(Mn) as a seed layer of Cu, and a Co(W) single-layer as reliable Cu diffusion barriers for future interconnects in ultra-large-scale integration. The use of Co(W) layer enhances adhesion of Cu to prevent electromigration and stress-induced voiding failures. The use of Cu(Mn) as seed layer may enhance the diffusion barrier performance of Co(W) by stuffing the Cu diffusion pass with Mn. APT was used to visualize the distribution of W and Mn in three dimensions with sub-nanometer resolution. W was found to segregate at the grain boundaries of Co, which prevents diffusion of Cu via the grain boundaries. Mn was found to diffuse from the Cu(Mn) layer to Co(W) layer and selectively segregate at the Co(W) grain boundaries with W, reinforcing the barrier properties of Co(W) layer. Hence, a Co(W) barrier coupled with a Cu(Mn) seed layer can form a sufficient diffusion barrier with film that is less than 2.0-nm-thick. The diffusion barrier behavior was preserved following a 1-h annealing at 400 °C. The underlayer of the Cu interconnects requires a large adhesion strength with the Cu, as well as low electrical resistivity. The use of Co(W) has previously been shown to satisfy these requirements, and addition of Mn is not expected to deteriorate these properties.

Voiding Phenomena in Copper-Copper Bonded Structures: Role of Creep

For its good resistivity and reliability, copper remains the most widely used material for metal interconnections since the early 1990s [1]. Concerning the 3D-integration technological transition for next generation integrated circuits, copper still remains interesting as a bonding material. In this specific configuration, this metal allows wafer or die level assembly of active component strata with high bonding strength and it also ensures interlayer electrical conduction, reducing interconnection delays and increasing overall performances [2-3]. In the process temperature range from 300°C to 400°C, the voiding mechanism that drives the structure failure [4-5] shows similar characteristics to stress-induced voiding previously reported in basic encapsulated copper interconnections [6]. However, regardless of the bonding technique, void density, shape and location exhibit variations which cannot be explained by the mechanisms previously established. In this paper, we investigate several factors, including copper surfaces roughness, copper layer microstructure and bonding processing parameters to weight their impact on the voiding phenomenon. Better understanding of void formation has enabled the achievement of wafer assemblies exhibiting much higher reliability and bonding quality.200mm thermally oxidized silicon substrates are used in this study. 500nm-thick copper layer are then deposited on a 20nm-thick titanium nitride layer which is used to prevent copper diffusion into silicon substrate. Copper-copper bonding is studied through two different bonding techniques: direct bonding at room temperature under atmospheric pressure after surface activation by chemical and mechanical polishing (CMP activated bonding) and thermocompression bonding (TC bonding) using a combination of a thermal budget and compressive stress. In both cases, additional post-bonding annealing is accomplished under nitrogen atmosphere.In our bonded copper layers configuration, voiding phenomenon is supposed to have different origins:- Residues of the copper surface roughness which is brought into contact during bonding process and trap some volume- Presence of metal oxide on sample surfaces and its subsequent degradation by annealing- Nucleation and growth of cavities due to standard metallurgical creep mechanisms of copper layers during its thermomechanical loadingIn order to evaluate roughness impact on the voiding phenomenon, bonding was performed thanks the two different techniques on copper surfaces exhibiting identical surface topology properties (post CMP treatments) (Fig. 1a). In order to aggravate void creation, TC bonding was also performed with extreme parameters in terms of pressure values and copper surface roughness (Fig. 1b). Void densities and volumes were estimated by high resolution Secondary Electron Microscopy (SEM) cross-sections observations (Fig. 2). A special attention was paid to imaging conditions and analysis. Indeed we operated data collection over large sections of about 40µm. In the context of this study we were able to appreciate significant differences between bonded samples. More specifically we focused on volume variations and size distributions which enabled us for instance to highlight the role of roughness in voiding phenomenon.Other possible causes for void generation were also investigated using dedicated experiments:- Gold-gold TC bonding was performed as a bonding reference system involving oxide free metallic layers- Bonding of copper layers carefully deposited on copper bulk substrates to highlight the influence of thermomechanical stress (Fig. 3)In the light of these results, the impact of the different factors will be discussed and the main source of voiding due to creep deformation will be demonstrated. FIGURES CAPTIONS Fig 1 : 20 x 20 µm² AFM scans of copper surface. a- In CMP bonding configuration: RMS roughness is 0.2 nm. b- In TC bonding configuration: RMS roughness is 22 nm. Fig 2 : SEM cross section. a – On CMP activated bonding after a post bonding annealing at 400°C. b – On TC bonding performed at 400°C under a pressure of 2.9 MPa on high-roughness surfaces. Voids are arrowed. Fig 3 : SEM cross section of TC bonding involving copper layers deposited directly on copper bulk substrate. Voids are arrowed. ACKNOWLEDGEMENTS The authors would like to thanks the French Direction Générale de l’Armement (DGA), the French Direction Générale de la Compétitivité de l’Industrie et des Services (DGCIS) and SOITECSA for its financial support. REFERENCES [1] P. C. Andricacos, et al., IBM J. Res. Dev., vol. 42, no. 5, pp. 567–574, Sep. 1998.[2] N. Sillon, et al., pp. 1 –4., IEDM 2008. [3] R. Taibi, et al., pp. 219–225, ECTC 2010.[4] C. S. Tan, et al., Appl. Phys. Lett., vol. 87, no. 20, pp. 201909, 2005.[5] P. Gondcharton, et al., MRS Online Proc. Libr., vol. 1559, 2013, doi : 10.1557/opl.2013.718.[6] H. Okabayashi, Mater. Sci. Eng. R Rep., vol. 11, no. 5, pp. 191–241, 1993.

Thermal stability, adhesion and electrical studies on (Ti,Zr)N x thin films as low resistive diffusion barriers between Cu and Si

In this study, we investigated the thermal stability, wettability, adhesion and reliability of (Ti,Zr)Nx films used as the diffusion barrier between Cu and Si. (Ti,Zr)Nx films were prepared by DC reactive magnetron sputtering from a Ti-5 at. % Zr alloy target in N2/Ar gas mixtures. A minimum film resistivity of 59.3 µω cm was obtained at an N2/Ar flow ratio of 2.75, which corresponds to the near stoichiometric composition (N/(Ti,Zr) ratio ∼0.95). The sheet resistance of Cu/(Ti,Zr)N0.95/Si was not significantly increased until annealing above 750°C, indicating good thermal stability. On the other hand, the adhesion energy between Cu and the (Ti,Zr)Nx film was reduced as the N/Ti ratio was increased. To obtain reliable performance on stress-induced-voiding (SIV) and electromigration (EM) tests, we proposed to use (Ti,Zr)/(Ti,Zr)Nx/(Ti,Zr) tri-layers. We suggest that the interfacial adhesion between barrier and Cu plays an important role in reliability. The proposed tri-layer structure may be a promising candidate for a barrier, as it exhibits excellent reliability without increasing resistance.

Genetic or pharmacologic disruption of the calcineurin-nuclear factor of activated T-cells axis prevents social stress-induced voiding dysfunction in a murine model

ObjectiveSocial stress can suppress the voiding reflex, with resultant diminished voiding frequency and increased volumes. The calcineurin-NFAT (nuclear factor of activated T cells) pathway is important in memory development. It was hypothesized that interruption of the calcineurin-NFAT pathway might prevent social stress-induced voiding dysfunction. MethodsMice were subjected to social stress in an established resident-intruder model for 1 h, followed by 23 h of barrier separation. NFATc3, NFATc4 knockout (KO) and wild-type (WT) mice were studied. At two weeks, voiding patterns were collected; this was followed by sacrifice. Corticotropin-releasing factor (CRF) mRNA expression in Barrington's nucleus (BN) was determined by in-situ hybridization. ResultsSocial stress decreased voiding frequency and increased voided volumes in WT strains. At baseline, NFATc3 KO mice showed decreased voids and increased volumes, while the NFATc4 KO mice resisted social stress. However, CRF mRNA increased in WT mice following social stress and was increased at baseline in NFATc3 KO mice. It was found that CRF mRNA did not increase following social stress in NFATc4 KO mice. The administration of CsA to WT mice normalized voiding patterns following social stress, albeit with no effect on CRF mRNA in BN. ConclusionDisrupting the calcineurin-NFAT axis by either genetic or pharmacologic approaches confers resistance to the development of social stress-induced voiding and dysfunction.

Lifetime prediction model of stress-induced voiding in Cu/low-κ interconnects

A lifetime prediction model of stress-induced voiding (SIV) has been developed to investigate the geometry dependence of lifetime in Cu/low-κ interconnects. A physical extrapolation model based on Cu ionic transport and time-dependent stress relaxation is proposed for obtaining an accurate estimation. The validity of the model is discussed from the viewpoints of linewidth and temperature dependences by comparison with an extrapolation using the empirical power law.