Stray Inductance Research Articles

A 15-kA Solid-State Circuit Breaker Research and Development for the Switch Network Unit of the EAST Tokamak

This article describes the research, development, and testing of a 15-kA solid-state circuit breaker (SSCB) prototype applied to the switch network unit (SNU) of the Experimental Advanced Superconducting Tokamak (EAST). The circuit scheme composed of parallel connected integrated gate-commutated thyristors (IGCTs) and the diode bridge to realize bidirectional breaker ability is presented first. In addition, the stray inductances of the bus bars and the heat sinks for the current sharing of each IGCT are also considered in detail. Through ANSYS Q3D parameters extraction, the influence of structure stray parameters on the current sharing of power device in parallel is analyzed. Finally, the operation performance of the SSCB has been successfully tested up to the rated current of 15 kA and the maximum interruption voltage of about 2.0 kV, these experiment results verified the current sharing of the parallel-connected devices and the reliability of the SSCB during current conduction and current commutation processes.

DC-Link Busbar Network Design and Evaluation Method for the Large-Capacity Power Electronic Converter

For the dc-link busbar in a high-capacity converter, the large-size laminated busbar is not adoptable due to the machining difficulty and limitation in current capability. In contrast, the regular nonlaminated busbar solution guarantees the required power capacity with a lower cost and easier installation. The main challenges exist in the large stray inductance and corresponding resonance phenomenon. Related analysis and accurate synthesis theory have not been reported. In this article, a matrix analysis method is proposed for the formed multiport and high-order network in a dc-link busbar. First, the multiport interaction and coupling are mathematically derived based on the subnetwork admittance matrix combination. The multipeak resonance phenomena are explained in detail. Meanwhile, it is manifested that proposed matrix method can be applied with the positive and negative sequence current analysis. Then accurate resonate currents can be obtained under the nonsinusoidal busbar current consideration. Finally, a resonance current gain (RCG) value is formed for the quantitative capacitor current evaluation and busbar design guidance. Proposed design and evaluation method is verified in a 315-kW converter system. More than 49% resonant current in the capacitor gets depressed by the enhancement. Its effect is close to the laminated busbar solution.

Updates on fast discharge resistor system for comprehensive research facility for fusion technology

When quench happens, the energy stored in the superconducting magnet is required to be transferred and consumed to fast discharge resistor (FDR) system in specific time by quench protection system (QPS). In the previous research, the design made of 1 mm SUS304 has a bad cooling effect due to the narrow wind channel. So, the updated design concerning the cooling problem as well as the stray inductance is asked. The updated FDR system focuses on the basis of solving thermal and inductance proportional inverse problem. The scaled model machine is developed to testify the design rationality. With the update, the newly developed FDR system can provide less heat accumulation and accelerate up the cooling-down speed without bringing more stray inductance.

The decreasing of the influence of parasitic inductance of tested object on the accuracy of its electrical capacitance measurement

This paper gives a description of measurement technique which can be used in practice of carrying out estimation of electrical capacitance of tested object with substantial stray inductance. Electrical capacitance is determined as a ratio of mean value of discharge current to the mean value of time derivative, taken from voltage on unknown capacitance. The decreasing of deleterious impact of stray inductance on accuracy of measurements is achieved by proper selection of the duration of analyzed signals. In proposed technique the duration is limited by instants of time that correspond to the maximum value of discharge current and to the termination of transient. The accuracy of described method for electrical capacitance estimation is affected by noisy components of obtained oscillograms. This deleterious impact can be alleviated by smoothing of time dependence by applying of least square method. Another reason for lost of accuracy is associated with possible influence of skin-effect in conductive elements of discharge circuit, which can cause time dependence of resistance and inner inductance of conductive parts of tested object and discharge circuit. Described technique, however, is based on taking into consideration independent on time parameters of equivalent lamped discharge circuit. Nevertheless, the example of practical implementation has shown that described approach allows to partially mitigate the influence of stray inductance on carried out measurements of electrical capacitance, as the value of relative error turned out to be equal to 2.04%

Low Inductance Design for Symmetrical Submodules in Hybrid HVDC Circuit Breaker

The diode bridge submodule (SM) is one of the basic units of a hybrid high-voltage dc circuit breaker. This article works on the low inductance design of a single SM and series SMs. For the layout design of a single SM, this article proposes a simple and clear +-shaped SM layout, the low inductance design is simplified to the optimization of two laminated busbars with a simple structure. Based on the +-shaped SM layout, this article further proposes an SM structure with holes in diodes region, the stray inductance is further reduced, and only one integrated laminated busbar is needed in a single SM. For the layout design of series SMs, this article makes full use of the layout of a single SM and the mutual inductances between the SMs, series SMs are alternately connected in reverse. The single SM layout proposed in this article is effective in reducing the stray inductance. The loop stray inductance in stage II reduced from 148.4 to 72.3 nH, a 51.3% reduction. When the two parallel IGBTs turn off a 6 kA fault current in 2 μs, the voltage spike is reduced from 786.1 to 423.4 V, a 46.1% reduction. And the stray inductance difference of the bidirectional current path is controlled to about 10 nH. The layout of series SMs proposed in this article is effective in reducing the length of the series SMs, the length is reduced by 16.7%. The experimental results show that the SMs layout proposed in this article is effective.

Analysis Of Modeling Methods Of Computer Engineering Digital Devices

When designing new digital instruments and devices, there are a vast variety of reasons why the finally designed devices will malfunction. To decrease the number of such failures and to increase design accuracy, various methods and systems for modeling digital devices are used. In these systems, various methods for describing signals in models of designed devices can be used. In this case, three-valued, four-valued, ..., nine-valued, thirteen-valued, as well as analog signal descriptions can be applied. Increasing signal and element models complexity in digital devices allows designing more accurate models. However, when modeling digital devices, multi-valued alphabets do not allow to increase the accuracy of modeling and research of dynamic processes in devices. This is due to the impossibility of taking into account processes and interference caused by both stray capacitances and inductances between separate components of the devices and conductors connecting them, as well as dynamic processes, caused by external electromagnetic fields affecting the device designed. Describing such processes using continuous or K-valued differential equations improves the accuracy of digital devices modeling. Nevertheless, the problems of automated testing of these devices and the automation of determining their performance remain unsolved. For automated recognition of failures in the designed digital devices, neural networks, in particular, adaptive resonant theory (ART) neural networks, can be applied, since they have an important property, the ability to retrain when additional information about failures occurs. However, neural networks also have an essential drawback: they do not allow getting more than one solution, although with K-valued differential calculus of digital devices, this can occur quite often, which makes it possible to recognize failures that can be attributed simultaneously to two or more different classes of errors, and, therefore, to recognize failures, which can be simultaneously assigned to two or more different classes, and consequently, get more accurate results. In this regard, it is necessary to develop neural networks that could recognize two or more possible solutions (or types of failures). This would expand the field of failures automated detection in the designed digital devices and determine the performance accuracy. Figs.: 3. Refs: 12 titles.

Commutation behaviour analysis of a 3L-ANPC-VSC phase-leg PEBB using 4.5kV and 3kA press-pack IGBT

Three-level Neutral-Point-Clamped voltage source converter is extensively used in high-power and Medium-Voltage applications. 3L-ANPC-VSC was put forward to conquer the unequal losses distribution and supply redundant switch states for zero-level output by replacing the clamping diode with IGBT in 3L-NPC-VSC. The stray inductance takes an important role in the commutation path of the switching current during the switching event. This paper shows two stacking methods of press-pack IGBT 3L-ANPC unit busbar have been designed. The main differences between the two structures are the positions of clamping IGBT(T5 and T6). The total switching power losses for all commutation paths are analyzed. The stray inductance of all the commutation paths have been extracted by means of Three-Dimensional Finite-Elements-Analysis simulations based on the theoretical analysis,. The optimal structures are obtained by optimizing structure according to simulation results. The calculated values have been compared with simulation results obtained from the performance of double-pulse tests for each commutation path. This paper presents all the analysis details of the 3L-ANPC-VSC commutation behavior using 4.5kV and 3kA press-pack IGBT modules.

Stray inductance extraction method based on interrupting transient process for power electronic component in hybrid DC circuit breaker

Stray inductance extraction method based on interrupting transient process for power electronic component in hybrid DC circuit breaker

Integrated Busbar Design for Stray Inductance and Volume Reduction in a High-Power SiC Traction Inverter

<div class="section abstract"><div class="htmlview paragraph">This paper presents a compact, partially laminated busbar design to connect the DC-link capacitor, high-voltage DC (HVDC) connector, and power module using a single integrated busbar. The proposed busbar design is designed for a high-power and high-voltage Silicon Carbide (SiC) traction inverter. The proposed solution eliminates the need for using separate busbars: one for the connection between the HVDC connector and the DC-link capacitor, and the other one between the connection of the DC-link capacitor and the power module. Incorporating two busbars in a single traction inverter increases the total volume of the inverter and the parasitic components. Thus, the main design goals in this paper are minimizing the parasitic inductances, increasing the power density, and achieving a uniform current distribution across the capacitor cores. Additionally, the compact busbar design allows a reduction in the parasitic resistance compared to two separate busbars and, hence, it reduces the power loss. The voltage overshoot and maximum allowable stray inductance of the busbar are investigated in detail. Current density and its effect on the busbar temperature rise are analyzed using 3D finite element analysis.</div></div>

Estimation of capacitors stray inductance by the analysis of overdamped discharge current curves

Wydawnictwo SIGMA-NOT wydaje czasopisma fachowe informujące swoich czytelników o najnowszych osiągnięciach naukowych i nowoczesnych rozwiązaniach technicznych w Polsce i na świecie, popularyzuje problemy techniczne oraz poszerza wiedzę i kulturę techniczną.

Optimization of a Gate Distribution Layout to Compensate the Current Imbalance Generated by the 3D Geometry of a Railway Inverter

The impact of the stray inductances originated from interconnects in power electronics becomes crucial with the next generation of SiC devices. This paper shows that the existing layout of a railway inverter, operating with Si IGBTs already exhibits a dynamic current imbalance between paralleled modules. This will not allow using this geometry with SiC MOSFETs. A complete investigation of the electromagnetic origin of this issue has been performed. A generic circuit model has been proposed to establish a cabling rule to design a Gate Distribution Printed Circuit Board (PCB) in such a way that it compensates the power dissymmetry. An optimization strategy has been used to obtain a new geometry of this PCB, which has been validated with a time domain simulation.

A New Dead Time Regulation Synchronous Rectification Control Method for High Efficiency LLC Resonant Converters

In low output voltage and high output current LLC resonant converter applications, a synchronous rectification (SR) is essential component for high efficiency and high power density. However, stray inductances in MOSFET package and printed circuit board (PCB) pattern make premature turn-off of SR gate and large SR dead time. To compensate the stray inductance effect and increase system efficiency, a hysteresis band dead time regulation control method is proposed. In the proposed control method, SR dead time is regulated to predetermined dead time target regardless of the stray inductances by using a mixed signal, which includes instantaneous drain voltage information and previous cycle dead time information. As a result, the proposed control method can provide lower conduction losses by the dead time regulation and better transient characteristic by the instantaneous drain voltage information. To verify the validity of the proposed control method, 234-W prototype is built and experimented with the proposed controller, which is implemented with 0.25-μm BCDMOS technology.

Channel current analysis of GaN HEMTs with source sense pin in DC/DC boost converters

The breakdown strength and electron mobility of gallium nitride (GaN) are almost ten and three times higher than those of the silicon devices. Wide band-gap devices have a higher thermal conductivity, higher switching frequency capability, lower on-state resistance and lower power dissipation. Detailed analytical models in the electrical network and channel current variations of these devices during switching intervals are still under investigation. The energy loss and heat dissipation on a power converter can be precisely estimated if the operational modes and the corresponding mathematical models of the device are accurately obtained. Depending on the instantaneous values of the channel current and voltage drops on the components computed from the model, the power dissipation and thermal response can be examined. Prediction of the switching losses of a GaN high electron mobility transistor (HEMT) with a source sense pin can be performed using the instantaneous variation of channel current. In this paper, a detailed analytical model including the stray inductances and parasitic capacitors is derived to obtain the channel current of GaN HEMTs with a source sense pin. The turn-on and turn-off transient energy losses during the switching of a single GaN HEMT device can be computed from the analytical model proposed in this paper using the channel current and drain-source voltage. Results of the derived analytical model, SPICE simulations and experimental work on the DC/DC boost converter are compared.

Revisited SCC Equivalent Resistance High-Frequency Limit Accounting for Stray Inductance Effect

Equivalent resistance of switched capacitor converter (SCC) is an important parameter that reflects the average conductivity loss. With the SCC switching frequency increase, it becomes necessary to account for the stray inductance effect that increases the equivalent resistance. The equivalent resistance high-frequency limit was previously reported to be proportional to the switching frequency and stray inductance. This article suggests that it is proportional to the squared switching frequency and squared stray inductance and inversely proportional to the circuit resistance. The accurate equivalent resistance and inductive switching limit (ISL) are calculated for different converters. The calculations are supported with simulation and experimental results.

Crosstalk Analysis and Suppression of Single Chip SiC MOSFET Half-Bridge Circuit

For the hard-switch applications of the half-bridge circuit based on SiC MOSFET, the crosstalk generation mechanism of the half-bridge circuit in the switching on and off process is analysed. The influence of the driving resistance and stray inductance of driving circuit on the crosstalk is simulated and analysed. In the single-chip half-bridge circuit, the Miller clamp method with BJT + diode is used. By increasing the driving resistance and reducing the clamp circuit inductance, the crosstalk suppression effect can greatly improve. It is an effective way to optimize the clamping circuit and reduce the clamp circuit inductance without affecting the switch speed.

A multi-input, multi-stage step-up DC-DC converter for PV applications

The paper introduces a step-up multiple-input multi-stage dc-dc converter with a soft-switching for Photovoltaic (PV) applications. The proposed topology is constructed from series connection of switched capacitor circuits to minimize the effects of partial shading and mismatch between PV modules. A soft switching is achieved for the entire switches in the converter with no need for additional components. The applied technique utilizes the stray inductance of PCB traces to create a LC circuit so that the zero current switching is achieved for all switches. Moreover, the converter will take advantage of the superior features of Wideband gap devices in order to operate at high switching frequency. As a result, bulky capacitors in switched-capacitor circuits are significantly reduced, hence, small size multilayers ceramic capacitors with high temperature capability will be employed. Furthermore, with the lower losses and the higher temperature capability of Wideband gap devices, the thermal requirements will be reduced and with fast reverse recovery time, the snubber circuit are not required. Simulation results are presented, laboratory prototype is constructed, and experimental results are given at rated power to validate the feasibility of proposed dc-dc converter under soft switching operation.

Electrothermal Modeling of the Insulated Gate Bipolar Transistor (IGBT) Using PSpice: Application to DC–DC Converter

In this paper, an improved electrothermal model of power IGBT was developed. The main local physical effects were taken into consideration. The suggested model is able to address the electrical and thermal effects. The model was confirmed through a comparison with other models having close characteristics for different circuits (DC–DC converter, turn-on and turn-off) and different temperatures. The IGBT model was implemented in the PSpice circuit simulation platform using PSpice standard components and analog behavior modeling (ABM) blocks. The IGBT switching performance was investigated under influence of different circuit elements (such as stray inductance, gate resistance and temperature) in order to study and estimate the on-state and switching losses pre-requisite for the design of various converter and inverter topologies. The comparison shows that these models are simple, tunable with the electric circuit software simulator. They are more capable of predicting the main circuit parameters needed for power electronic design. The transient thermal responses were demonstrated for the single pulse and repeat modes. The achieved results show that our model is suitable for full electrothermal simulations of power electronic circuits.

A low stray inductance laminated busbar for series-parallel capacitors

In the dynamic characteristics test circuit for high-voltage and high-power power electronic devices, the laminated busbar is the main connecting component. The stray inductance of the laminated busbar is one of the key factors that affect the accuracy of the dynamic characteristics. Therefore, a low stray inductance laminated busbar for series-parallel capacitors is proposed, from the perspective of reducing self inductance and increasing mutual inductance. Through finite element simulation, the result of extracting the stray inductance of the laminated busbar is 4.16nH. Compared with the most basic laminated busbar, this stray inductance is very small.

Silicon Carbide Multi-Chip Power Module for Traction Inverter Applications: Thermal Characterization and Modeling

Semiconductor power modules are the key hardware components of a traction inverter. It drives motor speed and torque, managing the energy exchange from battery to motor and viceversa. The increasing demand for electric and hybrid vehicle requests high performance power modules. Power semiconductor devices based on wide band gap compound, like silicon carbide (SiC), have excellent electrical properties in terms of on-state resistance, stray inductance and performance at high commutation frequency. One of the most promising solution is silicon carbide MOSFET power module in which each switch is made by several different dies placed in parallel. Embedded direct cooling system and novel materials with high conductivity (e.g., active metal brazed substrates) can be considered to enhance thermal performance. A robust method is needed to characterize and to predict power module temperature behavior considering the importance of the thermal performance to improve reliability and to optimize module weight and dimensions. According to several parallel dies inside each switch, classic method based on temperature electric sensitive parameter (TSEP) shall be validated with direct measurement. In this framework, it has been reported the thermal characterization of a power module for a traction inverter based on eight silicon carbide MOSFETs for each switch. Both TSEP and infrared measurements have been employed. Thermal behavior has been numerically reproduced, creating a simplified equivalent network and developing a predictive model by finite element method (FEM).

Complex circuit simulation and nonlinear characteristics analysis of GaN power switching device

Abstract To overcome the problem of energy losses in the electrical circuits and to improve the energy conversion efficiency, it is necessary to increase the power switch frequency and reduce the open resistance of the power switch. Moreover, based on energy saving, failure protection, circuit design and other aspects of the research of enhanced devices are also essential, a new static and dynamic model of GaN power transistor is proposed, and the steady-state and dynamic characteristics of GaN power transistors are simulated and tested. The GaN power transistor used in the test has a constant voltage of 450 V and a current of 4 A. By changing the driving power U, G (take 2, 3, 4V) and the stray inductance Ls (take 2 μH, 5 μH), the switching characteristics of the simulation model were studied, and the simulation was carried out by changing the absorption capacitance Cc (select 1.5 μF and 3.0 μF). This proposed simulation model can be used to analyze the protection effect of the buffer circuit under various stray inductors and help to guide the design of the buffer circuit. The simulation results of the static and dynamic models of the new GaN power transistor agree well with the experimental results. With the increase of Ug , the opening speed is faster, but the turn-off delay is longer. With the increase of Ls , the peak of the turn-off voltage increases. After increasing the absorption capacitance, the peak voltage during the turnoff is limited to the rated voltage, and the buffer circuit plays a protective role and the greater the Cc , the better the protection. The simulation results are consistent with the theoretical analysis, which verifies the effectiveness of the model.