strained-Si Technology Research Articles

Enhancement of carrier mobility in metal-oxide semiconductor field-effect transistors using negative thermal expansion gate electrodes

Strained-Si technology is crucial to improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs). To introduce large strain into the channel, we proposed a structure for the negative thermal expansion gate electrode. In this study, we used manganese nitride as the gate material, which is a negative thermal expansion material. The fabricated MOSFETs with the manganese nitride gate showed a 10% increase in electron mobility compared to the MOSFET with the Al gate. The results show that the negative thermal expansion gate technology is promising as a technology booster for MOSFET scaling.

Improvement of Drive Currents of FinFET using Strained Si Technology

Improvement of Drive Currents of FinFET using Strained Si Technology

Strained SI/SIGE/SI Nano-Channel Hoi Mosfet

Strained Si technology has headed in the development of single or dual channel strained silicon MOSFETs devices. Comprehending the need of advancement in recent technologies with miniaturized features, developing a novel MOSFET on ultrathin double strained Si with strained SiGe sandwiched in between and forming a tri-channel MOSFET has been the crux of this present research. Incorporation of quantum carrier confinement effect on the ultrathin dual strained Si layers in the channel has been implemented to counterbalance the threshold voltage roll-off induced by the strained layers. A comparison of the conventional strained silicon on relaxed silicon-germanium with double strained silicon channel MOSFET has been perceived leading to eloquent drain current enhancement of ~49% with a small reduction in the threshold voltage caused by the additional bottom strained Si layer. Further, 100nm and 50nm channel length have been compared and a superior device characteristic for the reduced device dimension is attained as the prominence of velocity overshoot is more in short channel device approaching to quasi-ballistic transport in the channel region

Electron Mobility Model for Tensile Strained-Si(101)

Nowadays, the strained-Si technology has been used to maintain the momentum of semiconductor scaling due to its enhancement performance result from the higher mobility. In this paper, the influence of ionizing impurity scattering, acoustic phonon scattering and intervalley scattering to strained-Si (101) material is discussed.In addition, a calculation of the electron mobility in Strained-Si (101) material is made using the average momentum relaxation time method described in Ref [1]. The results show that the electron mobility increases gradually for both [001] and [100] orientations while for [010] orientation increases rapidly with the increasing Ge fraction x.[1]

Comparison of NMOSFET and PMOSFET Devices That Combine CESL Stressor and SiGe Channel

Strained-Si technology could enhance the carrier mobility and improve the device performance. Contact-etch-stop-layer (CESL) structure with different stress and SiGe channel was fabricated with 90-nm technology. The electrical properties of N and PMOSFET devices combining CESL and SiGe channel were investigated. The short channel effects (SCE), such as drain-induced barrier lowering (DIBL), were also studied. Moreover, the stress contour in the SiGe channel has been simulated with TCAD to understand the relationship between stress distribution and device performance for different CESL structures. It is observed that the stress in the channel region was independent of the type of N or PMOSFET devices, but it was dependent on the CESL type and channel length. Based on the experimental and simulation results, it is confirmed that the device performance is associated with the stress in the channel, and the approach of CESL stressor and SiGe channel is shown to effectively improve the mobility of NMOSFETs and PMOSFETs.

Analytical modeling and simulation of subthreshold characteristics of back-gated SSGOI and SSOI MOSFETs: A comparative study

The Silicon–Germanium-on-Insulator (SGOI) and Silicon-on-Insulator (SOI) based MOS structures are spearheading the strained-Si technology. The present work compares the subthreshold characteristics of two short-channel back-gated (BG) strained-Si-on-SGOI (SSGOI) and BG strained-Si-on-Insulator (SSOI) MOSFETs, and provides some solutions to overcome the degradation in subthreshold characteristics with the unrelenting downscaling of the devices. Subthreshold behaviors of the MOS structures are based on surface potential model which is determined by solving the 2D Poisson's equation with suitable boundary conditions by evanescent mode analysis for both of the MOS structures. The closed form expressions for threshold voltage, subthreshold current and subthreshold swing have been derived for symmetrical as well as independent gate operation (IGO). In addition, the Electrostatic integrity (EI) factors for SSOI and SSGOI MOS structures have been estimated and compared with Double-Gate (DG) MOSFET. The numerical simulation results, obtained by ATLAS™, a 2D device simulator from Silvaco, have been used to assess the validity of the models.

Pocket Implant-Dependent Channel Mobility in Advanced p-MOSFETs With Strain Engineering

A new approach to channel mobility engineering using strained-Si technology is described with a complete data analysis. It is discussed that [110]/(100) Si channel mobility in p-MOSFET with embedded SiGe source/drain and compressive stress liner can be strongly dependent on pocket implant dose, resulting from a change in piezoresistance coefficient as a function of p-type carrier dopant concentration in the vicinity of the channel, whereas channel mobility of n-MOSFETs shows weaker dependence on pocket implant dose due to: 1) smaller piezoresistance coefficient of n-channel and 2) less channel strain relative to p-MOSFETs.

Densities of states of strained Si in different crystal systems

There has been aroused a lot of interest in the strained Si technology in the microelectronic field. Density of states (DOS) is an important physical parameter in strained Si materials. Based on the Kleinerts Variational perturbation (KP) theory related to stress, DOSs of electrons and holes near the bottom of conduction band and the top of valence band are obtained in tetragonal, rhombohedral and monoclinic strained Si grown from (001), (101) and (111) substrates respectively. It is found that their DOSs are obviously different from the ones of cubic unstrained Si, except DOSs of electrons near the bottom of conduction band in rhombohedral and monoclinic strained Si. The quantized model obtained can provide valuable references for understanding the strained Si material physics and developing the theoretical model of the other important physical parameters.

Layout Variation Effects in Advanced MOSFETs: STI-Induced Embedded SiGe Strain Relaxation and Dual-Stress-Liner Boundary Proximity Effect

This paper reports two areas of focus for layout variation effects in advanced strained-Si technology: 1) shallow-trench isolation (STI)-induced embedded SiGe (eSiGe) strain relaxation and 2) impact of dual-stress-liner (DSL) boundary on channel mobility. A complete data analysis, including two different strain measurement techniques of nanobeam diffraction and geometric phase analysis, is presented, along with a quantitative understanding for each effect. It is reported that the eSiGe profile can have a significant impact on the STI proximity effect for p-MOSFETs and that DSL boundary proximity can cause significant channel mobility degradation for both n- and p-MOSFETs. Both effects result in the reduction in channel strain along the [110] direction.

Insulating Halos to Boost Planar NMOSFET Performance

Short-channel controllability by insulating halo (IH) is investigated using the NFET strained-Si technology. By embedding SiO2/Si3N4 insulators in the halo regions, the increase of halo implant concentration reduces source/drain depths and improves short-channel effects such as drain-induced barrier lowering. With Ioff similar to the control device at the same gate length by adjusting the threshold voltage, the channel doping can be reduced, and the channel mobility increases due to the decrease of vertical electric field. Moreover, IHs reduce the shallow trench isolation compressive stress in the channel and yield a high-electron mobility enhancement. The device performance is optimized based on the simulation design. Up to a 23% Ion improvement was experimentally achieved by optimal IH insertion. A 7% lower junction capacitance and an 8% ring oscillator speed improvement are demonstrated when the IH is adopted in the NFET alone. Moreover, device reliability is carefully examined and is not adversely impacted by IH insertion.

Advanced SOI CMOS transistor technology for high performance microprocessors

In this paper we present an overview of partially depleted Silicon on Insulator (PD SOI) CMOS transistor technologies for high performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD SOI, strained Si, aggressive junction scaling, asymmetric devices need hand-in-hand development with multiple core- and power-efficient designs. These techniques have been developed, applied and optimized for 45 nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32 nm design rules, High K Metal Gate (HKMG) technology is the key. Different HKMG integrations as well as future strained Si technologies, like strained silicon directly bonded on SOI, and embedded Si:C are discussed.

Interfacial Control and Electrical Properties of Ge MOS structures

Ge MOSFETs have generated a strong interest as a current drive enhancement technology beyond strained-Si technologies. The key technologies for realizing Ge MOSFETs are the formation of superior MOS interfaces. However, control technologies of to provide superior Ge MOS/MIS interfaces has not been fully established yet. In this report we review recent technologies for controlling Ge MOS interfaces. In particular, we report the interface properties of thermally-oxidized GeO2/Ge and Si-passivated GeO2 interfaces in detail. In addition, we introduce a new measurement method for studying the physical origin of low current drive in Ge n-MOSFETs, where electron and hole mobility of SiO2/Ge interfaces are evaluated for an identical MOS interface by using metal source/drain GOI MOSFETs with a Kelvin pattern.

Evaluation of local strain in Si using UV-Raman spectroscopy

“Strained-Si”, in which intentional strain is introduced in Si crystal to improve carrier mobility by using a modulated band structure, is recognized as one of the most important technologies in post-scaling-generation LSIs. Strain-evaluation technology to probe strain in shallow surfaces that correspond to the channels of MOSFETs is crucial to achieving strained-Si technology. In this paper, we introduce the results we obtained by evaluating strain with the new UV-Raman spectroscopy we developed. Quasi-line shape illumination enabled Raman measurements with 200-nm intervals on the sample. The local-strain mechanism caused by SiN stressors covering a MOSFET was clarified by measuring one-dimensional strain profiles induced by patterned SiN film on Si. We also demonstrated that the induced strain was proportional to the inner stresses of SiN film and that it is more effective to introduce strain in SOI substrates than in bulk substrates. In the evaluation of a actual device fabricated by using the gate-last process in which strain was significantly enhanced after the dummy gate was removed, the size effect, i.e., an increase in induced strain with a decrease in gate length, was confirmed through one-dimensional strain-profile measurements with various gate lengths.

Mobility Modeling and Its Extraction Technique for Manufacturing Strained-Si MOSFETs

A new mobility model, together with its extraction method for manufacturing strained-Si MOSFETs, is presented. An accurate mobility extraction is obtained from the linear drain current by excluding the parasitic source/drain resistance and the parasitic gate capacitance. In addition to universal curves, the Coulomb mobility is dependent on whether devices have compressive or tensile stress. The dependences of Coulomb scattering on different stress conditions can be decoupled from the effective channel mobility in Matthiessen's form. From the extracted results, the tensile-stress N-channel MOSFETs have less Coulomb scattering effect, while the compressive counterparts suffer the worse Coulomb mobility degradation. By including the Coulomb scattering corrections, our model can properly predict mobility enhancements for various strained-Si technologies and dimensions.

Effectiveness of Si thin buffer layer for selective SiGe epitaxial growth in recessed source and drain for pMOS

Locally strained Si technology using embedded SiGe has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain areas. Prior to selective SiGe epi growth, a thin layer of Si seed was employed to help nucleate following low-temperature selective SiGe epitaxial film in recessed source and drain areas. In combination with pre-epi wet clean and low-temperature chemical bake, use of Si seed resulted in improved SiGe film morphology and micro-loading effect, and further improved device performance.

Impact of SiN on Performance in Novel Complementary Metal–Oxide–Semiconductor Architecture Using Substrate Strained-SiGe and Mechanical Strained-Si Technology

In this paper, we report the fabrication of a SiN-induced mechanically tensile-strained Si n-type metal–oxide–semiconductor field-effect transistor (nMOSFET) and a compressively strained SiGe p-type MOSFET to improve the drive current of both n- and pMOSFETs simultaneously, and we integrated both devices on the same wafer. Individual MOSFET performance can be adjusted independently to their optimum levels due to the separation process for two types of devices. It is found that n- and pMOSFETs in the novel complementary metal–oxide–semiconductor (CMOS) architecture had a better performance, not only a higher drain-to-source saturation current but also a higher transconductance with wide gate voltage swing, than the Si devices used as a control. Although a degraded performance was found in the pMOSFET with a SiN layer, this effect can be minimized by increasing the Ge content in the Si1-xGex conducting channel, thus demonstrating that the flow has a great flexibility for developing a next-generation high-performance CMOS devices.

Low frequency noise in biaxially strained silicon n-MOSFETs with ultrathin gate oxides

In this paper, a detailed investigation of the low frequency noise in biaxially strained-Si technology has been conducted. The noise behavior is described and compared with the results obtained on ultrathin oxide MOSFETs in an advanced silicon technology. The drain current noise measurements are interpreted by carrier number fluctuation noise models. The extracted oxide trap density is more important for the studied strained-Si devices. Finally, the important excess noise observed in the longest geometries is attributed to the gate-leakage current noise contribution.

Engineering strained silicon-looking back and into the future

The purpose of this article is to explain the basics behind straining and report on the current process technologies available to strain CMOS devices. Strained Si enhances the performance of CMOS devices by increasing carrier mobility without having to make them smaller. As the benefits to be gained from scaling transistors continue to decrease, the commercial interest in using strained Si for CMOS devices has spiked. Additionally, strained Si still retains its integratability in CMOS manufacturing processes, unlike any other semiconductor material. Thus the real test for engineers lies in the ability to cost-effectively develop and apply strained Si technology into current CMOS process. Thus new methods for straining Si is integrated into IC manufacturing as industry interest in this technology continues to grow and also increases the speed, performance and functions of the circuits

Ballistic phonon transport and self-heating effects in strained-silicon transistors

In this manuscript, different aspects of nanoscale thermal transport in strained silicon transistors will be addressed. The two-dimensional Boltzmann transport equations for phonons in Si and SiGe alloy layers, along with the acoustic mismatch model for the interface, are used to capture the sub-continuum heat conduction effects in the device. It is shown that the lateral thermal conductivity of a 10-nm strained-Si layer grown on the SiGe underlayer can vary from 14 to 20W/m-K, depending on the interface specularity parameter. The resulting temperature distribution in the device is used to predict the impact of self-heating on performance of future generations of strained-Si devices. The analysis shows that the merits of strained-Si technology can be suppressed by excessive self-heating; therefore, additional considerations in the design of these devices need to be taken into account.

Low temperature characterization of effective mobility in uniaxially and biaxially strained nMOSFETs

In this paper, a detailed investigation of the mobility in two different strained-Si technologies has been conducted. The mobility gain due to strain is nearly lost in short channel devices. The short channel loss observed in both cases is attributed to a bigger contribution of Coulomb scattering and to a larger subband splitting due to pocket implants. Finally, the mobility gain reduction with temperature lowering has been quantitatively interpreted by a simple analytical model accounting for the fourfold valley depopulation and considering different scattering rates for the two first subbands.