Storage Diode Research Articles

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

A Time-Resolved CMOS Image Sensor With Draining-Only Modulation Pixels for Fluorescence Lifetime Imaging

This paper presents a time-resolved CMOS image sensor with draining-only modulation (DOM) pixels, for time-domain fluorescence lifetime imaging. In the DOM pixels using a pinned photodiode (PPD) technology, a time-windowed signal charge transfer from a PPD to a pinned storage diode (PSD) is controlled by a draining gate only, without a transfer gate between the two diodes. This structure allows a potential barrierless and trapless charge transfer from the PPD to the PSD. A 256 × 256 pixel time-resolved CMOS imager with 7.5 × 7.5 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> DOM pixels has been implemented using 0.18-μm CMOS image sensor process technology with PPD option. The prototype demonstrates high sensitivity for weak signal of less than one electron per light pulse and accurate measurement of fluorescence decay process with subnanosecond time resolution.

A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode

A complementary metal-oxide-semiconductor (CMOS) image sensor with low-noise global shuttering and a dual-shuttering mode is presented. The developed two-stage charge transfer pixel enables noise canceling by means of true correlated double sampling. The implemented prototype demonstrates for the first time that a noise level of less than three electrons can be achieved in a global-shutter CMOS image sensor while attaining high shutter efficiency of 99.7%. In the dual-shuttering mode, both a pinned storage diode signal and a floating diffusion signal are used for desirable functions such as wide-dynamic-range imaging, motion detection, and dual consecutive snapshot imaging.

A Dynamic Range Expansion Technique for CMOS Image Sensors with Dual Charge Storage in a Pixel and Multiple Sampling.

A dynamic range expansion technique for CMOS image sensors with dual charge storage in a pixel and multiple sampling technique is presented. Each pixel contains a photodiode and a storage diode which is connected to the photodiode via a separation gate. The sensitivity of the signal charge in the storage diode can be controlled either by a separation gate which limits the charge to flow into the storage diode or by controlling the accumulation time in the storage diode. The operation of the sensitivity control with separation gate techniques is simulated and it is found that a blocking layer to the storage diode plays an important role for high controllability of sensitivity of the storage diode. A prototype chip for testing multiple short time accumulations is fabricated and measured.

A random noise reduction method for an amorphous silicon photoconversion layer overlaid CCD imager

A novel random noise reduction (RNR) method, which can reduce random noise generated in a storage diode (SD), has been proposed and evaluated with a cell test element. The RNR cell structure features an RNR transistor with a second storage diode, which is inserted between the SD and a vertical CCD (V-CCD). The RNR transistor controls the transfer channel potential and suppresses the random noise generated in the SD. Net first storage diode capacitance with the RNR transistor can be reduced down to (C/sub f//spl times/C/sub a/)/(C/sub f/+m/spl times/C/sub a/), where C/sub f/ is the second storage diode capacitance, C/sub a/ is the first storage diode capacitance, and m is the channel potential modulation factor. Experimentally, the RNR cell can reduce the random noise in the SD from 42 electrons [r.m.s.] down to 18 electrons [r.m.s.] for the SD capacitance of 5 fF. This makes it possible for the photoconversion layer overlaid CCD imager with the RNR cells to reproduce video images with a high S/N ratio.

Random noise generation mechanism for a CCD imager with an incomplete transfer-type storage diode

A random noise for a CCD imager with an incomplete transfer-type storage diode is theoretically and experimentally discussed. The theoretical result based on the Fermi-Dirac distribution function is in good agreement with the well known experimental result as a "kTC" noise, which is equal to the square root of kTC/2. It is also shown that the random noise in the storage diode is dependent on the amount of the signal charge, and can be reduced for the small signal charge. Moreover, a small signal reset operation (SSR operation) is newly proposed to suppress the capacitive-image-lag and larger random noise. The reproduced image with the high signal-to-noise (S/N) ratio is obtained for a STACK-CCD imager with the small signal reset operation.

Analysis of signal to noise ratio of photoconductive layered solid-state imaging device

The signal to noise ratio of the photoconductive layered solid-state imaging device (PSID) has been theoretically derived. In this analysis the noise suppression effect due to residual signal electrons in the storage diode after read-out operation, the optical shot noise, and the fluctuation of the number of transferred signal electrons due to incomplete readout signal electrons were considered. The obtained result showed good agreement to the experimental result.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

積層型ＣＣＤセンサのランダム雑音の解析

Because a charge injection type “two level” CCD image sensor needs metal contact to carry signal charge from its photoelectrical conversion layer to its storage diode, this type of sensor has a peculiar random noise generated in its picture cells. This noise has been studied from the view-point of electron emission from the storage diode, and the noise value obtained by measuring a 1-inch 2-million pixel image sensor corresponds to the analytically derived noise. We expect that the smaller a picture cell is, the less the noise value is.

A device for automatical recording of delayed coincidence curves

A device recording delayed coincidence curves with a charge storage diode as controlled delay element is described. The range of variation for the delay is equal to 100 ns. The maximum dead time equals 135 ns. The integral nonlinearity is less than 0.5%. The temperature stability is better than 1 ns/°C.

Theory of frequency multiplication including transition loss

A theory for frequency multipliers with charge storage diodes is developed including the effects of finite transition time. The transition loss due to the charge storage diode turn-off transient is taken into account with a charge-controlled diode model which requires only limited mathematical effort and has readily measurable characteristics. Furthermore, it very well describes the performance of multipliers: the analytical results agree well with measurements.

Fast timing circuit using charge storage diode

This paper describes a fast timing circuit with time shift compensation, based on the charge storage effect in semiconductor diodes. Within the dynamic amplitude range 0.09–10 V an output pulse time shift smaller than ±140 ps has been achieved with a light pulse generator. In the 5 GeV π −-meson beam with a 25 × 25 × 25 mm plastic scintillator and a XP 1020 photomultiplier time resolution of 0.33 ns has been measured.

High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System

Abstract—A 1024-word by 80-digit exploratory plated-wire store using diode-matrix word selection has a cycle time of 100 ns or less for READ and 140 ns for WRITE, while the destructive READWRITE asts 150 to 200 ns. To match the fluctuation in the type of request encountered, typically 80 percent READ, and thus maximize the throughput, it is advantageous to switch memory mode in an interlaced manner at logic speed. This is done by exploiting the plated-wire properties of NDRO and fast WRITE. A charge storage diode is used for memory protection and common word current control; READ 400 mA, WRITE 900 mA.

A zero-walk charge storage diode discriminator for fast coincidence systems

The use of charge storage diodes in conjunction with discrimination of fast scintillation detector pulses is described. It is demonstrated that the “snap-off” time of such devices can be made independent of the incident pulse amplitude. Several such circuits are shown. A technique for evaluation of such circuits in prompt coincidence systems is described.

Tunnel Diode-Charge Storage Diode Shift Register

A new method for shift register design based on a tunnel diode-charge storage diode combination is described. The tunnel diode acts as the permanent store with the charge storage diode as the temporary store to hold information while the main store is cleared. The circuit has very good tolerances and high rejection of extraneous pickup. Clock frequencies in excess of 100 MHz have been used with 1012 shifts successfully executed without a failure.

Frequency Multiplication using the Charge Storage Effect: An Analysis for High Efficiency, High Power Operation

Abstract A frequency multiplier using an ‘ ideal ’ non-linear capacitance, which may be approximated by a charge storage diode, is examined for the case where both the input and output circuits are tuned and where a finite resistance exists in series with the diode. After stating the problem in general terms, the case of a frequency doubler is examined and curves are given which relate the different circuit parameters and the drive conditions to the conversion efficiency and the output power. It is shown that high efficiencies (e.g. −2 dB) may be obtained and that the converted power is considerably greater than for a varactor with the same bias voltage and total series resistance. The theory is verified experimentally with a 3 Mc/6 Mc doubler and correlation with the theory is found to be good.

The charge storage diode as a logic element

The application of the carrier-storage frequency divider as a parametron-type logical element is described. An analysis of the smallsignal phase locking process is presented and a number of basic logical circuits, which have been tested experimentally, are given. The primary limitation to the speed of operation of the device as a logical element is seen to be the drive frequency.

Charge controlled nanosecond logic circuitry

To date, nanosecond circuitry has been based mainly on two devices--the transistor and the tunnel diode. Unfortunately, the speed advantages of the tunnel diode cannot be utilized because the current gain is limited by practical tolerance requirements. Therefore, any circuits designed "around" these two devices are either practical, but limited to the speed of the transistor, or impractical, for general purpose logic, with the speed performance of the tunnel diode. The region of the tunnel diode gain bandwidth curve which is limited by tolerances can be exploited by using a storage diode as an interstage current amplifier or charge transformer. The operation of the storage diode is discussed, and charge gain bandwidth criteria are developed from the physical equations describing the device. Charge control switching curves are developed for the tnnnel diode which define its operation as a charge amplifier. The combination of tunnel diode and charge transformer (TDCT Logic) enables a wide variety of logic functions to be obtained with a gain bandwidth tolerance performance previously unattainable in nanosecond logic circuitry. To demonstrate this capability a novel "NOR" circuit is described and a worse case analysis of the fan out tolerance performance is given in the Appendix.

An analysis of a circuit for the generation of high-order harmonics using an ideal nonlinear capacitor

A particular harmonic generator circuit using an ideal nonlinear capacitor is analyzed and theoretical expressions are obtained for the loss involved in generating a high-order harmonic. The harmonic energy is developed in a load resistor either as an exponentially decaying sine wave or as a pulse. The analysis is valid for harmonics of about the tenth or greater. The results are presented in a graphical form that allows the losses involved to be found easily and it is thus shown that the minimum loss in generating a high-order harmonic by this circuit is about 8.5 db independent of the order of the harmonic. The degree to which a charge storage diode approximates to an ideal nonlinear capacitor is then discussed and some experimental results using such a diode are presented.

High-Speed Microwave Switching of Semiconductors--II

A relationship between low-power isolation and small-signal, low-frequency diode resistance is reported. A study of ambient heating indicates that with increasing temperature the diode characteristics tend to approach the line characteristic of the above relationship. Observed switching speeds of 1.5 to 3.0 mµs are reported. A theory is presented which agrees with the switching time data and predicts microwave switching times as low as 0.2 to 0.3 mµs. High speed switching is discussed with reference to significant parameters, e.g., hole storage, internal heating, and pulse reverse diode characteristics.