Static Noise Margin Research Articles

Static Response of Three-Dimensional and Printed Complementary Organic TFTs-Based Static Random-Access Memory

A three-dimensional (3-D) and printed static random-access memory (SRAM) based on complementary organic thin-film transistors is demonstrated. The SRAM exhibited the smallest area of 2.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the highest normalized static noise margin of 62%, and the maximum gain of 16.8 V/V compared to the reported values of organic SRAM cells. The transistors’ 3-D integration minimizes the cell area. The 3-D SRAM cell design enables us to match the strengths of transistors by modifying the dielectric thickness without changing the channel geometry. This high-performance complementary organic thin-film transistors-based SRAM shows its high application potential in large-scale and low-cost wearable intelligent electronics for data storage and processing.

A loadless 4T SRAM powered by gate leakage current with a high tolerance for fluctuations in device parameters

A novel loadless four-transistor static random access memory (4T SRAM) cell is proposed that consists of two N-type driver MOSFETs and two P-type access ones whose gate leakage currents from word-line are used for holding data in the cell. It is shown that the proposed cell has a higher tolerance for manufacturing device fluctuations compared with the conventional loadless 4T SRAM. Furthermore, it is free from bit-line disturb in contrast to the conventional cell. It is confirmed by simulation in 32 nm technology node that the read static noise margin (SNM) of the proposed cell reaches 138.7% of the six-transistor SRAM cell and that the hold SNM can be acceptable when the gate insulator thickness of the P-type access MOSFETs is made thinner than the N-type driver MOSFETs. The retention current for the proposed cell decreases to 66.7% of the 6TSRAM and the data rate in read increases to 125%.

Self-heating effect on logic performance of 6T-SRAM based on CFET device

Complementary FET (CFET) devices have become emerging and promising candidates for continuing Moore’s law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the static random-access memory (SRAM) unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells

For many decades, SRAM cell design with low power dissipation is the problem of interest for researchers due to its numerous applications in embedded systems. In this research work, a Bulk double gate FinFET based design of SRAM cell and performance analysis is carried out. Also, a comprehensive analysis is performed on FinFET and CMOS technology based SRAM cells. The novelty in the proposed work is, the designing of the 14 nm bulk double gate FinFET transistor using the FEM tool and eventually designing the SRAM cells. The designed bulk FinFET offers an IDS of 3.5 μA/μm with HfO2 as dielectric material. By using this type of FinFET in SRAM cell design the leakage current is reduced significantly. The performance analysis on 6 T(T represents the number of transistors used in the design of SRAM cell), 7 T, 8 T and 9 T SRAM cells design with MOSFET and FinFET technologies is done in terms of leakage current, power dissipation and static noise margin. Compared with MOSFET, FinFET based SRAM cell offers low leakages especially 7 T SRAM cell has low leakage of 296.7 pW. The SRAM cells SNM value is also improved by 10 %.

Design of a soft error hardened SRAM cell with improved access time for embedded systems

Recent advancements in high-performance processor operation have nurtured the requirement of low power, reliable, and fast static random-access memory (SRAM). Scaling supply voltage is the most preferred technique while minimizing the power dissipation in SRAM cells. However, several challenges follow with this improvement including, increased soft errors and diminishing operating speed. A novel 12T SRAM cell is presented in this work for improving critical charge and operating speed. The improvement in key parameters of the proposed cell is affirmed by comparing with recently reported circuits that use various improvement techniques, i.e., standard 6T (S6T), tunable access transistors 8T (T8T), PPN based 10T (PP10T), Schmitt-trigger based 10T (ST10T), Soft error hardened 10T (SEH10T), Schmitt trigger based 11T (ST11T), stable low power 11T (SL11T), and data-dependent 11T (DPS11T) cell. The critical charge of the proposed 12T is improved by 1.39×/1.30×/1.69×/0.79×/0.92×//1.51×/1.02×/1.6 2× comparing with S6T/T8T/PP10T/ST10T/SEH10T/ST11T/SL11T/DPS11T SRAM cell. Moreover, the proposed cell successfully mitigates the half-select issue that allows implementing a bit-interleaved array. The access time in proposed 12T during read and write operations is reduced by 1.14×/1.04×/1.11×/1.11×/1×/1.02×/1.12×/1.01× and 0.97×/1.02×/1.70×/0.96×/1.39×/0.99×/0.93×/0.96× respectively comparing with S6T/T8T/PP10T/ST10T/SEH10T/ST11T/SL11T/DPS11T SRAM cell. The enhancement in read stability and write ability of the proposed 12T is represented by 1.21×/1.09×/0.60×/0.88×/0.61×/0.61×/1.08×/1.10× and 1.06×/1.10×/1.29×/0.82×/0.93×/1.06×/0.80×/1.05× variation in read and write static noise margin, respectively comparing with S6T/T8T/PP10T/ST10T/SEH10T/ST11T/SL11T/DPS11T cell. Also, the proposed 12T require low data retention voltage in contrast to other considered cells.

A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

AbstractThe design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing “1” problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T.

Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement

Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct examples, many ternary inverters with reduced noise margins have been presented in the literature. The defect is mainly because of their improperly shaped voltage transfer characteristic (VTC). With proper transistor sizing, we can rectify the problem and provide uniformly wide noise margin values while maintaining power-delay product (PDP) low. As far as we know, none of the previous ternary inverters has been given based on a methodical transistor sizing procedure. In this paper, a systematic transistor sizing through physical equations is suggested for an existing standard ternary inverter (STI), whose original sizes for the carbon nanotube FETs (CNFETs) are inappropriate. This paper includes a comprehensive investigation to determine appropriate values for the physical parameters of the CNFET-based STI. Compared with the original design, with a negligible increase in circuit delay and area, simulation results show that the proposed ternary inverter can increase noise margin and static noise margin by up to 47.7% and 83.3%, respectively.

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

The use of Internet of Things (IoT) applications become dominant in many systems. Its on-chip data processing and computations are also increasing consistently. The battery enabled and low leakage memory system at subthreshold regime is a critical requirement for these IoT applications. The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system. Therefore, a process tolerant SRAM cell with low power, improved delay and better stability is presented in this research paper. The proposed cell comprises 11 transistors designed with symmetric approach for write operations and single ended circuit for read operations that exhibits an average dynamic power saving of 43.55% and 47.75% for write and 35.59% and 36.56% for read operations compared to 6 T and 8 T SRAM cells. The cell shows an improved write delay of 26.46% and 37.16% over 6 T and 8 T and read delay is lowered by 50.64% and 72.90% against 6 T and 10 T cells. The symmetric design used in core latch to improve the write noise margin (WNM) by 17.78% and 6.67% whereas the single ended separate read circuit improves the Read Static Noise Margin (RSNM) by 1.88x and 0.33x compared to 6 T and 8 T cells. The read power delay product and write power delay product are lower by 1.94x, 1.39x and 0.17x, 2.02x than 6 T and 8 T cells respectively. The lower variability from 5000 samples validates the robustness of the proposed cell. The simulations are carried out in Cadence virtuoso simulator tool with Generic Process Design Kit (GPDK) 45 nm technology file in this work.

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

This work presents a novel low-leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep submicron technology nodes, it includes static noise margin monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of the first failure. As proof of concept, a macro of 1 Mb is fabricated in 22-nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Design and Analysis of Soft Error Rate in FET/CNTFET Based Radiation Hardened SRAM Cell.

Aerospace equipages encounter potential radiation footprints through which soft errors occur in the memories onboard. Hence, robustness against radiation with reliability in memory cells is a crucial factor in aerospace electronic systems. This work proposes a novel Carbon nanotube field-effect transistor (CNTFET) in designing a robust memory cell to overcome these soft errors. Further, a petite driver circuit to test the SRAM cells which serve the purpose of precharge and sense amplifier, and has a reduction in threefold of transistor count is recommended. Additionally, analysis of robustness against radiation in varying memory cells is carried out using standard GPDK 90 nm, GPDK 45 nm, and 14 nm CNTFET. The reliability of memory cells depends on the critical charge of a device, and it is tested by striking an equivalent current charge of the cosmic ray’s linear energy transfer (LET) level. Also, the robustness of the memory cell is tested against the variation in process, voltage and temperature. Though CNTFET surges with high power consumption, it exhibits better noise margin and depleted access time. GPDK 45 nm has an average of 40% increase in SNM and 93% reduction of power compared to the 14 nm CNTFET with 96% of surge in write access time. Thus, the conventional MOSFET’s 45 nm node outperforms all the configurations in terms of static noise margin, power, and read delay which swaps with increased write access time.

Monolithic 3D Inverter with Interface Charge: Parameter Extraction and Circuit Simulation

We have simulated a monolithic three-dimensional inverter (M3DINV) structure by considering the interfacial trap charges generated thermally during the monolithic three-dimensional integration process. We extracted the SPICE model parameters from M3DINV structures with two types of inter-layer dielectric thickness TILD (=10,100 nm) using the extracted interface trap charge distribution of the previous study. Logic circuits, such as inverters (INVs), ring oscillators (ROs), a 2 to 1 multiplexer (MUX), and D flip-flop and 6-transistor static random-access memory (6T SRAM) containing M3DINVs, were simulated using the extracted model parameters, and simulation results both with and without interface trap charges were compared. The extracted model parameters reflected current reduction, threshold voltage increase, and subthreshold swing (SS) degradation due to the interface trap charge. HSPICE simulation results of the fanout-3 (FO3) ring oscillator considering the interface trap charges showed a 20% reduction in frequency and a 30% increase in propagation delay compared to those without the interface trap charges. The propagation delays of the 2 × 1 MUX and D flip-flop with the interface trap charges were approximately 78.2 and 39.6% greater, respectively, than those without the interface trap charges. The retention static noise margin (SNM) of the SRAM increased by 16 mV (6.4%) and the read static noise margin (SNM) of SRAM decreased by 43 mV (35.8%) owing to the interface trap charge. The circuit simulation results revealed that the propagation delay increases owing to the interface trap charges. Therefore, it is necessary to fully consider the propagation delay of the logic circuit due to the generated interface trap charges when designing monolithic 3D integrated circuits.

A 9T FinFET SRAM cell for ultra-low power application in the subthreshold regime

Due to the scaling of the CMOS, the limitations of these devices raised the need for alternative nano-devices. Various devices are proposed like FinFET, TFET, CNTFET. Among these, the FinFET emerges as one of the promising devices which can replace the CMOS due to its low leakage in the nanometer regime. The electronics devices are nowadays more compact and efficient in terms of battery consumption. The CMOS SRAMs have been replaced by the FinFET SRAMs due to the scaling limitations of the CMOS. Two FinFET SRAM cells have been which power efficient are and having high stability. Performance comparison of these cells has been done to analyze the leakage power and the static noise margins. The simulation of the cells is done at 20 nm FinFET technology. It has been analyzed that the write margin of improved 9T SRAM cell achieves an improvement of 1.49x. The read margin is also showing a drastic improvement over the existing cells which has been compared in the paper. The hold margin was found to be better in the case of the proposed SRAM cell at 0.4 V. The gate length has been varied to find the effect on read margin with gate length.

10T FinFET based SRAM cell with improved stability for low power applications

ABSTRACT Due to scaling, many limitation arise for CMOS-based design memory cells in the nanometre regime, i.e. it becomes necessary to find a substitute for this design. Low power and high speed integrated circuits (ICs) are the demand of the electronics industry in many applications such as Internet of things (IoT) and electronics gadgets, e.g. Mobile, Laptops etc. Now, modern design ICs uses carbon nanotube FET or FinFET to design memory cells because of their excellent features of having low leakage and delay and improved performance. In this paper, two 10 transistor (10 T) FinFET design SRAM cells are proposed along with their hold, read, and write static noise margins (HSNM, RSNM, and WSNM), dynamic and static power consumption. These cells consume low power and provide high stability for electronic gadgets. In the proposed cells, we used a separate read and write path and back gate control method (BG). A comparative analysis of the proposed cells is done with the existing 10 T CMOS and FinFET based cells. All cells are simulated by using the tool HSPICE at 32 nm technology for a supply of 0.5 V. Cells 1 and 2 dissipate 69% and 85% less static power, 54% and 68% less read power and 17% and 56% less write power, respectively, compared to the 10 T FinFET cell. Results signify that the proposed independent gate (IG) FinFET based cells have the highest value of margins and the least value power consumption.

SRAM design leveraging material properties of exploratory transistors

While MOSFET miniaturization continues to face increased challenges related to process variations, supply voltage scaling and leakage currents, exploratory devices such as Graphene Nanoribbon Field Effect Transistors (GNRFET), Tunnel Field Effect Transistor (TFET), and Carbon Nanotube Field Effects Transistors (CNFET) could provide solutions for continued device scaling with better power/performance trade-offs. The GaN TFET used in this work is a heterojunction device, where the material properties of Ga and N result in a bandgap of 3.2eV and ultra-low IOFF current. Moreover, the properties of Ga and N result in a steep-switching device with a subthreshold swing of 30mV/decade. The structure of graphene material results in high conductivity of electrons, even at very high operating temperatures, making GNRFETs a high-performance device. However, graphene specific line-edge roughness can degrade performance, and thus process related variations can have a negative impact for GNRFETs. In CNFETs, the mobility and the velocity of the conducting carriers are functions of the carbon nanotube and the gate length. The length and the diameter of the carbon nanotube material adds parasitic capacitance and resistance to the model, contributing to slower speed of the device. In this paper, the impact on power, performance, and static noise margins (SNM) of the traditional single-port 6T-SRAM and modified single-port 8T-SRAMs designed using exploratory devices are analyzed with a set figure of merit (FOM), elucidating the material properties of the devices. The results obtained from this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array while CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 µW, while TFET- based SRAM bitcell show the best overall average and static power consumption at 4.79 µW and 57.8 pW. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write, and hold SNMs of 201 mV, 438 mV and 413 mV respectively.

Design of low power SRAM- based ubiquitous sensor for wireless body area networks

Purpose Smart ubiquitous sensors have been deployed in wireless body area networks to improve digital health-care services. As the requirement for computing power has drastically increased in recent years, the design of low power static RAM-based ubiquitous sensors is highly required for wireless body area networks. However, SRAM cells are increasingly susceptible to soft errors due to short supply voltage. The main purpose of this paper is to design a low power SRAM- based ubiquitous sensor for healthcare applications. Design/methodology/approach In this work, bias temperature instabilities are identified as significant issues in SRAM design. A level shifter circuit is proposed to get rid of soft errors and bias temperature instability problems. Findings Bias Temperature Instabilities are focused on in recent SRAM design for minimizing degradation. When compared to the existing SRAM design, the proposed FinFET-based SRAM obtains better results in terms of latency, power and static noise margin. Body area networks in biomedical applications demand low power ubiquitous sensors to improve battery life. The proposed low power SRAM-based ubiquitous sensors are found to be suitable for portable health-care devices. Originality/value In wireless body area networks, the design of low power SRAM-based ubiquitous sensors are highly essential. This design is power efficient and it overcomes the effect of bias temperature instability.

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

Systematic Control of Negative Transconductance in Organic Heterojunction Transistor for High-Performance, Low-Power Flexible Ternary Logic Circuits.

Organic multi-valued logic (MVL) circuits can substantially improve the data processing efficiency in highly advanced wearable electronics. Organic ternary logic circuits can be implemented by utilizing the negative transconductance (NTC) of heterojunction transistors (H-TRs). To achieve high-performance organic ternary logic circuits, the range of NTC in H-TRs must be optimized in advance to ensure the well-defined intermediate logic state in ternary logic inverters (T-inverters). Herein, a simple and efficient strategy, which enables the systematic control of the range and position of NTC in H-TRs is presented. Each thickness of p-/n-type semiconductor in H-TRs is adjusted to control the channel conductivity. Furthermore, asymmetric source/drain (S/D) electrode structure is newly developed for H-TRs, which can adjust the amount of hole and electron injection, independently. Based on the semiconductor thickness variation and asymmetric S/D electrodes, the T-inverter exhibits full-swing operation with three distinguishable logic states, resulting in unprecedentedly high static noise margin (≈48% of the ideal value). Moreover, a flexible T-inverter with an ultrathin polymer dielectric is demonstrated, whose operating voltage is less than 8V. The proposed strategy is fully compatible with the conventional integrated circuit design, which is highly desirable for broad applicability and scalability for various types of T-inverter production.

A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications.

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

Architecture and Optimization of 2T (Footprint) SRAM

A 6T-SRAM bitcell with the footprint of only two transistors is demonstrated by stacking four n-type vertical gate-all-around transistors (VFET) on two pFinFETs. The local interconnects are all within the footprint of the two bottom pFinFETs. The bitcell area is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.014~\mu \text{m}^{{2}}$ </tex-math></inline-formula> considering the experimentally achievable metal pitch of 52 nm and bottom pFinFETs of 5 nm node. It can be further reduced to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.009~\mu \text{m}^{{2}}$ </tex-math></inline-formula> considering the metal pitch of 30 nm. The minimum operating voltage is analyzed considering the dominant work function variation. The fin height of pFETs and the gate length of nFETs are used to optimize the read/write static noise margin (RSNM/WSNM) for the same bitcell area. The cell ratio is insensitive to pFET fin height and nFET gate length, leading the read stability to be less affected by pFET fin height and nFET gate length as compared to the write stability. The minimum operating voltage is reduced to 0.59 V using pFET fin height of 15 nm and nFET gate length of 20 nm to balance the read/write SNM without assist circuit techniques. The minimum operating voltage can be further improved to 0.56 V by optimizing the threshold voltage of −0.27 and 0.27 V for pFETs and nFETs, respectively. Moreover, using the negative bitline (NBL) technique can provide an additional 320 mV reduction on the write minimum operating voltage.