Static Frequency Divider Research Articles

The Study on Single-Event Effects and Hardening Analysis of Frequency Divider Circuits Based on InP HBT Process.

The single-event effects (SEEs) of frequency divider circuits and the radiation tolerance of the hardened circuit are studied in this paper. Based on the experimental results of SEEs in InP HBTs, a transient current model for sensitive transistors is established, taking into account the influence of factors such as laser energy, base-collector junction voltage, and radiation position. Moreover, the SEEs of the (2:1) static frequency divider circuit with the InP DHBT process are simulated under different laser energies by adding the transient current model at sensitive nodes. The effect of the time relationship between the pulsed laser and clock signal are discussed. Changes in differential output voltage and the degradation mechanism of unhardened circuits are analyzed, which are mainly attributed to the cross-coupling effect between the transistors in the differential pair. Furthermore, the inverted output is directly connected to the input, leading to a feedback loop and causing significant logic upsets. Finally, an effective hardened method is proposed to provide redundancy and mitigate the impacts of SEEs on the divider. The simulation results demonstrate a notable improvement in the radiation tolerance of the divider.

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

A broadband static frequency divider up to 62GHz in InP DHBT with capacitive degeneration

A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver

This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz.

Power and area‐efficient static current mode logic frequency divider in 180‐nm complementary metal‐oxide‐semiconductor technology

AbstractThis paper presents power and area optimized, high‐speed metal‐oxide‐semiconductor (MOS) current mode logic (MCML)‐based frequency dividers. Each differential pair in the divider is sized separately to minimize the overall power consumption. The divide‐by‐2 frequency divider has been realized in a 180‐nm complementary MOS (CMOS) process technology, and postlayout simulation results show that the proposed frequency divider can work up to an operating frequency of 18.8 GHz in the worst‐case process corner with a maximum power dissipation of 1.715 mW under 1.8‐V supply. It gives a bandwidth of 19.9 GHz which ranges from 1 to 20.9 GHz. The divider occupies a 0.106 × 0.09 mm2 area. The performance corresponds to the figure of merit (FoM) of 43.61 dB. The same optimized latches and two EX‐OR gates are used to design a divide‐by‐5 frequency divider that is also realized in 180‐nm CMOS process technology. The postlayout simulation results show that the proposed divide‐by‐5 frequency divider can faithfully work up to an operating frequency of 12.12 GHz in worst‐case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8‐V supply. It occupies a 0.166 × 0.116 mm2 area. The performance corresponds to the FoM of 26.56 dB which compares favorably with the state of the art.

A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Post layout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74-μW power consumption for the high-speed design and a maximum frequency of 10 GHz with 53-μW power consumption for the minimum PDP design.

A Novel Design Method of SOF for InP DHBT ECL and CML Static Frequency Dividers

In this letter, we present a novel analysis and design approach of self-oscillation frequency (SOF) for 0.8-μm indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) emitter-coupled logic (ECL) and current-mode logic (CML) static frequency dividers. SOF of ECL and CML dividers is designed to be the maximum value after theoretical analysis and multiparameter optimization. The results show that the SOF of the ECL and CML divider is 62 and 37.5 GHz, respectively. With sinusoidal waveform input, the operating frequency range of the ECL divider is from 0.1 to 65 GHz, and CML is from 0.1 to 55 GHz, while the cut-off frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> is 150 GHz. For ECL, the f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> utilization of SOF (SOF /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) is 0.413, and CML is 0.25. These are the maximum SOF results that can be designed for the two dividers under the same design conditions.

Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 (DIV2) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different both from the one of the conventional MCML DFF (D-type Flip-Flop) and from FMCML DFF without a level shifter. Then an analytical strategy to optimize the divider in different design scenarios: maximum speed, minimum power-delay product (PDP) or minimum energy-delay product (EDP) is presented. The possibility to scale the bias currents through the divider stages without affecting the speed performance is also investigated. The proposed analytical approach allows to gain a deep insight into the circuit behavior and to comprehensively optimize the different design tradeoffs. The derived models and design guidelines are validated against transistor level simulations referring to a commercial 28nm FDSOI CMOS process. Different divide-by-8 circuits following different optimization strategies have been designed in the same 28nm CMOS technology showing the effectiveness of the proposed methodology.

A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS

A power efficient static frequency divider in commercial 55 nm SiGe BiCMOS technology is reported. A standard Current Mode Logic (CML)-based architecture is adopted, and optimization of layout, biasing and transistor sizes allows achieving a maximum input frequency of 63 GHz and a self-oscillating frequency of 55 GHz, while consuming 23.7 mW from a 3 V supply. This results in high efficiency with respect to other static frequency dividers in BiCMOS technology presented in the literature. The divider topology does not use inductors, thus optimizing the area footprint: the divider core occupies 60 × 65 μm2 on silicon.

Feasibility study of the feed‐forward carrier recovery technique for E‐band integrated receivers

A feasibility study of a carrier recovery technique based on a feed-forward controlled leakage transmission carrier is presented. The study proposes a receiver topology and verifies its feasibility by means of the system-level simulations. The results of the study indicate that the proposed technique is theoretically modulation-independent and can be used with each modulation format. To demonstrate a practical feasibility, a BPSK receiver topology is proposed and based on it a demonstrator chip is implemented in a SiGe 0.13 μm heterojunction bipolar transistor technology. To reduce the complexity of the integrated receiver and to sustain low risks at the first production run, the receiver was implemented as all-resistive. The carrier recovery circuit on the chip comprises a static frequency divider and a K a -band phase-locked loop with quadrature outputs. A direct-conversion sub-harmonic mixer plays the role of a E-band demodulator. The proposed technique can be used in various high baud rate communication applications, saving on the computing power of the digital process.

Phase noise prediction for static frequency dividers and ring oscillators

This Letter presents a method of predicting the phase noise limits of static frequency dividers. The proposed phase noise model for free-running and injection-locked modes is based on the circuit parameters only. The model provides an intuitive comprehension of the phase noise behaviour of static frequency dividers and is proved to be useful in primary hand calculations. The method was verified against measurement results of a static frequency divider-by-two, operated at 77 GHz and fabricated in a SiGe 0.13 μ m process.

A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes

In this work, a novel architecture is proposed for designing the clocked master-slave TFF (M/S-TFF) based on modified gate-diffusion input (m-GDI) method. By noting that we used clocked phase scheme or feedback input technique in designing the M/S-TFF circuit. The advantages of the proposed scheme can be cited as reduce the number of required transistors, lower power consumption-propagation delay product (PDP) in all activity factors and layout area in comparison with similar state-of-the art designs. More importantly, Monte-Carlo simulations confirm proposed topology gains substantial variation tolerance with a substantial small standard deviation and considerable lower variability percentage in metrics than other schemes in same technology. At the end, the presented static frequency divider (SFD) using proposed M/S-TFF, works at wider frequency range with 0.198 milli-Watt (mW) power dissipation at the maximum operating frequency (fmax.) about 46 Giga-Hertz (GHz) under 0.9 Volt supply voltage. Therefore, using the proposed scheme can be improved in data storing elements, prescaler block in phase-locked loop (PLL) chips for future of generation communication networks like: fifth generation (5G) and microprocessors performance.

Analytical Approach for SiGe HBT Static Frequency Divider Design for Millimeter-Wave Frequency Operation

This paper presents a new analytic approach for static frequency divider design. It consists of derivations of analytic expressions for the self-oscillation frequency and frequency divider oscillation condition, based on the device-level circuit parameters only. Additionally, an analytic expression for frequency divider sensitivity is obtained based on injection-locking theory. The proposed approach is verified against measurement results of a static frequency divider, fabricated in SiGe BiCMOS 0.13- $\mu \text{m}$ process. This approach enables fast preliminary frequency divider design based on time- and resource-efficient simulations.

Layout and Interconnect Optimization for Low-Power and High-Sensitivity Operation of $E$ -Band SiGe HBT Frequency Dividers

A layout and interconnect optimization techniques for low-power and high-sensitivity performance of static frequency dividers in $E$ -band is reported. The layout optimization provides optimal transistor placement and identifies critical interconnects, which allows to reduce their parasitics. These measures provide high operation frequency and good sensitivity of the divider without a need of investing additional dc current.

Advanced Heterojunction Bipolar Transistor for Half-THz SiGe BiCMOS Technology

The high-frequency performance of a novel SiGe heterojunction bipolar transistor (HBT) module with monocrystalline base link is investigated in an industrial 0.13-μm BiCMOS environment. The main feature of this new HBT module is a significant reduction of the external base resistance as shown here by direct comparison with a conventional double-poly-silicon technology. Peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values of 300/500 GHz are achieved. A minimum current-mode logic ring oscillator gate delay of 1.8 ps and a record operation frequency for a SiGe static frequency divider of 161 GHz are demonstrated.

Dynastat frequency divider with DC‐153 GHz range

A dual-mode dynamic/static (dynastat) divided-by-two combines the range of a static frequency divider (DC-117 GHz from simulation) and the higher toggle frequency of a dynamic divider (85–153 GHz, simulated) at a low input sensitivity of 0.2 Vpk differential (<−3 dBm into 50 Ω). The measured self-oscillation frequencies of the prototype are 79 GHz (static) and 129 GHz in dynamic mode. The 8880 μm2 dynastat implemented in 90 nm silicon germanium (SiGe)-bipolar CMOS consumes 38 mA (static) and 19 mA (in dynamic mode) from a 4.5 V supply.

Ring Oscillator Based Injection Locked Frequency Divider Using Dual Injection Paths

Ring oscillator based injection locked frequency dividers (ILFD) generally feature higher power efficiency compared to conventional static frequency dividers. However it is difficult for ring oscillator based ILFDs to achieve large division ratio and wide input locking range at the same time. To increase the input locking range, a ring oscillator based ILFD utilizing dual injection technique is proposed in this letter. For this, both tail injection and direct injection are applied in phase such that the output currents of the two mixing processes corresponding to the two injection paths are added constructively at the output frequency $\omega o$ and the overall injection efficiency is therefore increased. A differential buffer circuit with dual injection is proposed. Equivalent circuit modeling of the dual injection buffer and mathematical analysis of locking range enhancement are presented. The core ring oscillator consists of 4 stages of the dual injection buffers. It is fabricated in a 65 nm CMOS technology and consumes less than 2 mW with supply voltage of 1.2 V. Its locking range is from 1.2 to 20.7 GHz without any tuning at 0 dBm injection power level. The proposed ILFD is compact with the core only occupying 15 $\mu$ m $\,\times\,$ 30 $\mu$ m and does not need any extra controls, making it suitable for integrated wideband phase locked loop.

A 83 GHz InP DHBT static frequency divider

A static frequency divider is presented using 0.7 μm InP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master–slave D-flip–flop topology with 30 HBTs and 20 resistors with a chip size 0.62 × 0.65 mm2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.

A 120 GHz Voltage Controlled Oscillator Integrated with 1/128 Frequency Divider Chain in 65 nm CMOS Technology

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of 1385 × 835 μm².

A Low-Power Wideband Transmitter Front-End Chip for 80 GHz FMCW Radar Systems With Integrated 23 GHz Downconverter VCO

A low-power FMCW 80 GHz radar transmitter front-end chip is presented, which was fabricated in a SiGe bipolar production technology ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> =180 GHz, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> =250 GHz ). Additionally to the fundamental 80 GHz VCO, a 4:1-frequency divider (up to 100 GHz), a 23 GHz local oscillator (VCO) with a low phase noise of -112 dBc/Hz (1 MHz offset), a PLL-mixer and a static frequency divider is integrated together with several output buffers. This chip was designed for low power consumption (in total <; 0.5 W, i.e., 100 mA at 5 V supply voltage), which is dominated by the 80 GHz VCO due to the demands for high output power (≈ 12 dBm) and low phase noise (minimum -97 dBc/Hz at 1 MHz offset) within the total wide tuning range from 68 GHz to 92.5 GHz (Δ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> = 24.5 GHz). Measurements of the double-PLL system at 80 GHz showed a low phase noise of -88 dBc/Hz at 10 kHz offset frequency.

Quadrature current-reused divide-by-3 semi-dynamic frequency divider with active balun

A divide-by-3 semi-dynamic frequency divider (SDFD) with active balun is presented using the current-reused technique. The proposed SDFD is composed of a Gilbert cell mixer, one stage of static divider and an active balun. The LO switching stage of the Gilbert cell mixer is also the current source of the static frequency divider to construct the current-reused architecture. At the incident power of 0 dBm, this frequency divider operates at the maximum bandwidth of 1100 MHz from 21.5 to 22.6 GHz. The power consumption of the divider is 12 mW at a 1.5 V supply voltage.