Standard Data Bus Research Articles

Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system

This paper concentrates on the Automatic Identification System (AIS receiver) and various interfaces on FPGA which is used in the satellite. The AIS is used to detect a collision of ships. Vessels equipped with AIS provide vessel navigation information like their speed, location etc. Satellites that are fitted with S-AIS receivers, receives the information and transmits it to the on-board computers. Transmission of information requires various interfaces. The paper presents the design and implementation of I2C and MIL-STD-1553 bus protocol, which interfaces FPGA board and on board computers in satellite and synthesized on Virtex-5 FPGA in Xilinx ISE 14.2 platform. The functional simulation of the bus is also carried under different test cases. Small satellites make use of an I2C bus. For the purpose of interfacing low-speed peripheral device on FPGA, I2C bus which is a multi-master, the two-wire bi-directional serial bus is used. The MIL-STD-1553 bus is a standard data bus, mostly use in spacecraft on-board data handling subsystem in the military. In this, communication is in between one master terminal called bus controller and other slave terminals called remote terminal (RT). MIL 1553 bus can hold up to 30 RT.

Towards an innovative electrical interface standard for PocketQubes and CubeSats

Developers experience issues with the compatibility, connector size and robustness of electrical interface standards for CubeSats and PocketQubes. There is a need for a lean and robust electrical interface standard for these classes of satellites. The proposed interface standard comprises a linear data bus which is used for housekeeping data, internal commands and small-to-moderate payload data. A community based analytic hierarchy process is used for the trade-off of design options, resulting in the selection of RS-485 as standard data bus, mainly due to its low power consumption and high effective data throughput compared to other candidates. Several switched and protected battery voltage lines are distributed from the central electrical power subsystem unit to the other subsystems to enable a simple and efficient power distribution. The harness comprises a 14 and 9 pin stackable connector for CubeSats and PocketQubes, respectively, occupying very little board space.

Instrumentation of kinetic spectroscopy—10. A modular data acquisition system for laser flash photolysis and pulse radiolysis experiments

A modular instrumental system for processing transient signals in laser flash photolysis and pulse radiolysis experiments is described. Modules with fast time-response and terminated interconnections allow signal capturing over a large time range, from nanoseconds to infinity, through the use of various kinds of detectors. A standard data bus is used to connect this system to the computer.

Introduction to the FASTBUS standard data bus

The FASTBUS standard data bus is a development of the U.S. NIM Committee, National Bureau of Standards, U.S. Department of Commerce, Washington, DC (Chairman, L. Costrell). Although originally conceived to provide an upgraded framework for the high data rate experimental apparatus of nuclear particle physics, the system is designed with sufficient generality to support a broad range of data acquisition as well as control applications. FASTBUS is based on an emitter-coupled logic interface technology and a generalized multiprocessor system architecture. The background and status of the development project are described.

Status of the FASTBUS Standard Data Bus

FASTBUS is a new laboratory standard data bus intended for use in experimental data acquisition and control. The development of FASTBUS began with a feasibility study in 1976 and is presently at the development prototyping stage. The principal aims of the standard are to provide a factor of ten or more improvement in speed of data transfers over present systems, as well as to provide an architecture for systems containing multiple processors. Developmental prototypes now in progress include crates, backplanes, cooling devices, power supplies, test and diagnostic modules, and user modules. A sizeable software development effort is also underway. Several experiments have made commitments to use FASTBUS. A review of current work and potential applications is given.

Status of the Interlaboratory Development of a High-Speed Standard Data Bus - FASTBUS

The FASTBUS project is an interlaboratory effort to develop a next generation laboratory standard data bus. The principal design goals are high speed (<100 nsec per word block transfers), wide data path (32 bits), identical parallel addressing architectures at both system and sub-system levels, ability to support multiple parallel master controllers, and ability to support special modes of operation for high energy physics applications. The current status of development is briefly described.