Stage CMOS Operational Amplifier Research Articles

Design of low offset voltage in second stage CMOS operational amplifier using 90nm technology

In this paper a low offset voltage; low power and high gain second stage op-amp of differential amplifier along with common source amplifier with compensated capacitor is proposed. The mathematical analysis of two-stage op-amp is elaborated and this work is compared with exiting similar work. The experimental work carried in CADENCE Virtuoso with 0 gpdk090 process technology is used to obtain 60.994 of Phase Margin, 61 dB DC gain and Offset voltage is 2mV. The M/L ratios are selected accordingly where supply voltage and load voltage are fixed at 1.8V and 12pF respectively. The parametric analysis helps, where the values are fixed to get better response.

A Two Stage CMOS Operational Amplifier with Trans Conductance Stabilization by Stacking Technique for Biomedical Applications

A low power bio signal recording frontend two-stage CMOS operational amplifier is presented. The first stage of the amplifier is designed with stacking technique in order to reduce the noise and for stabilizing overall trans-conductance using the same current. The supply voltage is 1.8V. Simulation process carried out with 180nm CMOS technology. Gain, bandwidth and input referred noise are keeping as a main aspect. The designed amplifier has a gain 83.1dB, consumes power is 102.5μW.

Offset voltage minimization based circuit sizing of CMOS operational amplifier using whale optimization algorithm

Evolutionary algorithms are simple and efficient techniques for optimization of VLSI circuits. In this work, Whale Optimization Algorithm (WOA) is used to design a two stage CMOS operational amplifier (OpAmp)with optimum area so as to achieve minimum offset voltage and also meet different design specifications such as Slew Rate, Gain etc. for the operational amplifier. For maintaining current imbalance at the output stage of the OpAmp, offset minimization is an important requirement. Algorithmic results were further validated by redesigning the OpAmp in the standard CADENCE Virtuoso circuit simulator. There is a good agreement found between the virtuoso simulated and algorithmic results. The results obtained from WOA is then compared with the performance of other algorithms such as Particle Swarm Optimization(PSO), Human Behaviour based Particle Swarm Optimization (HBPSO), Differential Evolution (DE) etc. Based on comparative analysis, it is found that the WOA performed better for circuit sizing the CMOS OpAmp for minimum offset as compared to the other algorithms by having a better convergence rate, low power dissipation and a minimum offset, although to achieve this, it required a little higher area.

Process Variation and Optimization of Two Stage CMOS Operational Amplifier at 45 nm and 32 nm Technology

Process Variation and Optimization of Two Stage CMOS Operational Amplifier at 45 nm and 32 nm Technology

Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback

This paper presents an ultra high gain two stage CMOS Operational Amplifier which is designed using self-cascoding and positive feedback technique in order to provide gain enhancement. By comparing the circuit with other designed circuits it has been shown that applying positive feedback increases the gain of the Op-Amp without affecting other properties of the amplifier. The proposed circuit is designed in 45 nm technology using Cadence Virtuoso Analog Design Environment tool at ±1 V supply. The Op-Amp is designed to achieve a high gain of 141 dB while maintaining a UGB of 101 MHz and phase margin of 60°. The simulation results conforms the estimated theoretical improvements. The dependence of various properties such as slew rate, UGB, settling time and phase margin of the designed Op-Amp on compensating capacitor CC has also been analyzed in this paper. Finally, the simulation results have been compared with a previously reported Op-Amp utilizing positive feedback technique.

Implementation of MIN/MAX Functions using Operational Transconductance Amplifier

This paper shows the different steps to realize and simulate the MIN/MAX fuzzy operators using operational transconductance amplifier, operational amplifier and 2 stage CMOS operational amplifier using SPICE. This paper also shows the calculation of different parameters like slew rate, power dissi, CMRR and gain for all the fuzzy operators. Later comparison of all parameters was discussed. The results with OTA comes out to be the best as it uses less voltage, more slew rate for high speed operations.

An Ultra-Low-Power Low-Voltage Two Stage CMOS Operational Amplifier in 45 nm Technology

An Ultra-Low-Power Low-Voltage Two Stage CMOS Operational Amplifier in 45 nm Technology

An ultra-high gain low power two stage CMOS op-amp based on inverse aspect ratio self cascode structures

A very high gain (137 dB) two stage CMOS operational amplifier having structural simplicity of classical Widlar architecture has been presented. The differential input stage of proposed operational...