Spin Transfer Torque Magnetic Tunnel Junction Research Articles

Scaling Projections on Spin-Transfer Torque Magnetic Tunnel Junctions

We investigate scaling of technologically relevant magnetic tunnel junction devices in the trilayer and pentalayer configurations by varying the cross-sectional area along the transverse direction using the non-equilibrium Green's function spin transport formalism. We study the geometry dependence by considering square and circular cross-sections. As the transverse dimension in each case reduces, we demonstrate that the transverse mode energy profile plays a major role in the resistance-area product. Both types of devices show constant tunnel magnetoresistance at larger cross-sectional areas but achieve ultra-high magnetoresistance at small cross-sectional areas, while maintaining low resistance-area products. We notice that although the critical switching voltage for switching the magnetization of the free layer nanomagnet in the trilayer case remains constant at larger areas, it needs more energy to switch at smaller areas. In the pentalayer case, we observe an oscillatory behavior at smaller areas as a result of double barrier tunneling. We also describe how switching characteristics of both kinds of devices are affected by the scaling.

Exploring Hybrid STT-MTJ/CMOS Energy Solution in Near-/Sub-Threshold Regime for IoT Applications

Emerging memories have been developed to achieve energy efficiency target in the Internet of Things era. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile (NV) memory has demonstrated attractive performance because of zero standby power, reduced switching power, infinite endurance, and high density. Meanwhile, hybrid STT-MTJ/CMOS integration is a promising solution to overcome the bottleneck of dynamic and leakage power dissipation. In this paper, ultralow power methodologies are developed at device and circuit level in 28 nm fully depleted silicon on insulator CMOS technology. Supply voltage scaling, near-/sub-threshold (V t ) operation, and back-bias adjustment are demonstrated, showing 81% dynamic power reduction under 0.6 V near-V t sensing operation, with the tradeoff of 6.2% increased sensing error rate. Through the case study on STT-MTJ-based NV flip-flops (NV-FFs), up to 76% dynamic and 79% leakage power saving can be realized in ultra-low power NV-FF implementation.

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

The Internet of Things (IoTs) relies on efficient node memories to process data among sensors, cloud and RF front-end. Both mainstream and emerging memories have been developed to achieve this energy efficiency target. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile memory (NVM) has demonstrated great performance in terms of zero standby power, switching power efficiency, infinite endurance and high density. However, it still has a big performance gap; e.g., high dynamic write energy, large latency, yield and reliability. Recently, voltage-controlled magnetic anisotropy (VCMA) has been introduced to achieve improved energy-delay efficiency and robust non-volatile writing control with an electric field or a switching voltage. VCMA-MTJ-based MRAM could be a promising candidate in IoT node memory for high-performance, ultra-low power consumption targets.

Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ

Nonvolatile flip-flop (NVFF) using spin-transfer torque magnetic tunnel junctions (STT-MTJs) has been proposed to enable fine-grain power gating systems. However, the STT-MTJ-based NVFF (STT-NVFF) may not perform fast backup and disturb-free restore operations. We propose a new NVFF using complementary polarizer MTJ (CPMTJ) to alleviate these limitations. Our proposed NVFF exploits the CPMTJ structure for fast- and low-energy backup operation. The estimated backup delay is less than 10 ns in 7-nm node FinFET technology with CPMTJ size of $12\,\,\text {nm} \,\,\times $ 33 nm in a rectangular shape. Furthermore, during the restore operation, CPMTJ provides guaranteed disturb-free sensing, since the disturb torque from the two complementary pinned layers of CPMTJ cancels each other. The simulation results show >2 times improvement in the backup delay with higher restore-disturb margin compared with STT-NVFF.

Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology

In the upcoming internet of things (IoT) era, spin transfer torque magnetic tunnel junction (STT-MTJ) based non-volatile (NV) memory and circuits for IoT nodes and normally-off electronics will need to meet constraints in speed, energy and robustness. This study focuses on NV logic-in-memory (LIM) architecture. Supply voltage ( $V_{dd}$ ) scaling in MTJ based NV-LIM is evaluated on FD-SOI 28 nm node. In order to overcome $V_{dd}$ scaling bottleneck, an efficient framework for $V_{dd}$ scaling in NV circuits is proposed with design strategies, e.g., back-bias (BB), poly biasing (PB), and approximate computing. The design vector ( $V_{dd}$ , $V_{BB}$ ,PB) generated power-delay curves can provide user-defined LIM circuit aiming for dynamic/leakage power saving, power/speed efficiency and process variation resilient. The design space is explored in near-threshold regime around 0.5 V supply. Simulations of NV-logic, full adder (NV-FA) and flip-flop (NV-FF) are performed, along with insights for circuit design and practical implementation of NV-LIM circuits with FD-SOI technology.

Non-Volatile In-Memory Computing by Spintronics

Exa-scale computing needs to re-examine the existing hardware platform that can support intensive data-oriented computing. Since the main bottleneck is from memory, we aim to develop an energy-efficient in-memory computing platform in this book. First, the models of spin-transfer torque magnetic tunnel junction and racetrack memory are presented. Next, we show that the spintronics could be a candidate for future data-oriented computing for storage, logic, and interconnect. As a result, by utilizing spintronics, in-memory-based computing has been applied for data encryption and machine learning. The implementations of in-memory AES, Simon cipher, as well as interconnect are explained in details. In addition, in-memory-based machine learning and face recognition are also illustrated in this book.

Inverse-magnetostriction-induced switching current reduction of STT-MTJs and its application for low-voltage MRAM

A new spin-transfer torque (STT) magnetic tunnel junction (MTJ) using an inverse magnetostriction (IMS) material for the free layer is proposed for low-voltage MRAMs. The MTJ is surrounded by a piezoelectric gate structure so that a pressure for introducing the IMS effect can efficiently be applied to the free layer without any high-yield-strength support structure. During STT-induced magnetization switching, the energy barrier height for the switching can be lowered by the IMS effect, and thus a critical current density (JC) for the magnetization switching can dramatically be reduced. Energy performance of a low-voltage STT-MRAM cell using the proposed MTJ and a FinFET is also demonstrated.

Reliability analysis of hybrid spin transfer torque magnetic tunnel junction/CMOS majority voters

Majority voters are typically used in redundancy hardening techniques aiming to increase the reliability of nanoscale circuits. Besides, Spin Transfer Torque Magnetic Tunnel Junction (STT-MJT) has been identified as the most promising candidate for low power and high speed applications. In this paper, we present two majority voter circuits based on nanometer STT-MTJ. By using STMicroelectronics FDSOI 28nm process and a precise STT-MTJ compact model, electrical simulations have been carried out to compare their performances and analyze their reliability. Both radiation sensitivity and variability have been investigated in the reliability-aware analysis.

A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI

Due to the process variation, Spin Transfer Torque Magnetic Tunnel Junction (STT-MTJ) faces great challenges in fabrication process. Meanwhile, its neighbor CMOS is also influenced by significant process variation with the continuous technology scaling down. Both of the two effects lead to degraded performance of hybrid MTJ/CMOS circuit. This paper proposes a methodology to alleviate the impact of process variation on the performance of MTJ based applications. The methodology is presented by carrying out a novel design of non-volatile flip-flop (NVFF) using asymmetrical forward body bias (FBB) in fully depleted silicon on insulator (FDSOI). Simulation results show that the sensing errors have been almost removed by this method with the minimum size of circuit. In addition, the thermal robustness of this circuit has also been dramatically improved.

Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost

The planar ultrathin body and buried oxide fully depleted silicon-on-insulator (FDSOI) technology is one of the proper candidates to replace bulk CMOS due to its high volume, low cost, and lower power. In this paper, we investigate the performance of hybrid magnetic-MOS non-volatile (NV) magnetic flip-flops (MFFs) in the FDSOI technology. The NV-MFF performance parameters, e.g., active power, leakage power, and sensing delay, are optimized with selected design vectors: supply voltage ( $V_{\mathrm{ dd}}$ ), forward body bias (FBB), and poly bias (PB). NVFF reliability can be improved by FBB performance compensation. The perpendicular magnetic anisotropy spin-torque transfer magnetic tunnel junction (MTJ) is used to design the MTJ/MOS hybrid MFFs. Two typical MFF circuits: master-slave MFF and multiplexing sense amplifier-based MFF are implemented and analyzed with the 28 nm FDSOI technology. The simulation results show that the MFFs in the FDSOI technology feature high energy efficiency and enhanced reliability. The energy efficiency of MFF is guaranteed by the proper selection of $V_{\mathrm{ dd}}$ and FBB voltage. PB is useful for low leakage power design, with the tradeoff of additional sensing delay. The highest PB and the lowest BB transistor configuration lead to large improvements in leakage power consumption.

The Physics of Spin-Transfer Torque Switching in Magnetic Tunneling Junctions in Sub-10 nm Size Range

The spin-transfer torque magnetic tunneling junction (MTJ) technology may pave a way to a universal memory paradigm. MTJ devices with perpendicular magnetic anisotropy have the potential to have high thermal stability, high tunneling magnetoresistance, and low critical current for energy-efficient current-induced magnetization switching. Using devices fabricated through focused ion beam etching with Ga- and Ne-ion beams, this paper aimed to understand the size dependence of the current/voltage characteristics in the sub-10 nm range. The switching current density drastically dropped around 1 MA/cm $^{\mathrm { {2}}}$ as the device size was reduced below 10 nm. A stability of over 22 kT measured for a 5 nm device indicated a significantly reduced spin relaxation time.

Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits.

A non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction Based Circuits

This paper presents a non-Monte Carlo (MC) methodology for variability analysis of spin transfer torque magnetic tunnel junction (STT-MTJ)-based circuits. The methodology is implemented by using worst case corner models of STT-MTJ and transistor. The MTJ compact model of worst case corners is proposed for the first time. The design specifications are detailed in non-volatile memory cells and arithmetic unit, e.g., one transistor–one MTJ (1T-1M) memory array, pre-charge sense amplifier (PCSA)-based STT-MRAM and magnetic full-adder circuit. The methodology is implemented by using a 28 nm fully depleted silicon on insulator design kit and this compact model of MTJ. Results show that the proposed methodology is much more efficient than conventional MC method while keeping the same target of performance evaluation. The simulation speed has been improved up to $226\times $ for an effective evaluation of circuit performance (compared with 1000 times MC simulation). MTJ-based circuit designers can assess the impact of process variation on circuit performance without time consuming MC simulations by using this method.

Reliable majority voter based on spin transfer torque magnetic tunnel junction device

A reliable majority voter circuit using a nanometre spin transfer torque magnetic tunnel junction (STT-MTJ) is presented. The circuit tolerates single transient faults and manages process variations due to technology downscaling. The use of this magnetic device brings non-volatility memory to logic circuits and promises to overcome the rising standby power issue. By using the STMicroelectronics fully depleted silicon on insulator 28 nm design kit and a precise STT-MTJ compact model, electrical simulations have been carried out to show its low-power and high reliability performances.

Multiplexing Sense-Amplifier-Based Magnetic Flip-Flop in a 28-nm FDSOI Technology

A novel low-power nonvolatile magnetic flip-flop is introduced in this paper. The perpendicular magnetic anisotropy spin torque transfer magnetic tunnel junction (STT-MTJ) is used to design the hybrid MTJ/CMOS circuit, which is implemented with 28-nm high- $\kappa$ metal gate and planar ultrathin body and buried oxide fully depleted silicon on insulator technology. The proposed flip-flop structure named SA-MFF shares a sensing amplifier for normal flip-flop mode and nonvolatile data sensing mode. The modified latch at output stage improves flip-flop latency. The proposed SA-MFF is symmetrical, which provides an equal delay for both true and complementary outputs. It can strengthen weak input signals (minimum 300 mV) and latch them to supply voltage. Forward body biasing transistors allow for fast operation and minimum energy consumption across all modes. The proposed SA-MFF achieves 45.2- ${\rm ps}$ latency, 50.1- ${\rm ps}$ clock to output delay, 12.71 $\mu {\rm W}$ active power and 343.6 ${\rm n}{\rm W}$ of leakage power with 1-V supply voltage, and 6.47- $\mu$ m $\times \,$ 4.54 $\mu$ m layout area. Moreover, reliability issues are highlighted with reliability-aware simulations. Process variations of transistors/MTJs and stochastic characteristics of MTJs are investigated. Clock jitter effect and flip-flop metastability are studied.

Spin-transfer torque magnetic memory as a stochastic memristive synapse for neuromorphic systems.

Spin-transfer torque magnetic memory (STT-MRAM) is currently under intense academic and industrial development, since it features non-volatility, high write and read speed and high endurance. In this work, we show that when used in a non-conventional regime, it can additionally act as a stochastic memristive device, appropriate to implement a "synaptic" function. We introduce basic concepts relating to spin-transfer torque magnetic tunnel junction (STT-MTJ, the STT-MRAM cell) behavior and its possible use to implement learning-capable synapses. Three programming regimes (low, intermediate and high current) are identified and compared. System-level simulations on a task of vehicle counting highlight the potential of the technology for learning systems. Monte Carlo simulations show its robustness to device variations. The simulations also allow comparing system operation when the different programming regimes of STT-MTJs are used. In comparison to the high and low current regimes, the intermediate current regime allows minimization of energy consumption, while retaining a high robustness to device variations. These results open the way for unexplored applications of STT-MTJs in robust, low power, cognitive-type systems.

MTJ-based hybrid storage cells for “normally-off and instant-on” computing

Besides increasing a computing throughput, multi-core processor architectures bring increased capacity of SRAM-based cache memory. As a result, cache memory now occupies large proportion of recent processor chips, becoming a major source of the leakage power consumption. The power gating technique applied on a SRAM cache is not efficient since it is paid by data loss. In this paper, we present two hybrid memory cells that combine a conventional volatile CMOS part with Magnetic Tunnel Junctions (MTJs) able to store a data bit in a non-volatile way. Being inherently non-volatile, these hybrid cells enable instantaneous power off and thus complete reduction of the leakage power. Moreover, given that the data bit can be stored in local MTJs and not in distant storage memories, these cells also offer instantaneous and efficient data retrieval. To demonstrate their functionality, the cells are designed using 28 nm FD-SOI technology for the CMOS part and 45 nm round spin transfer torque MTJs (STT-MTJs) with perpendicular magnetization anisotropy. We report the measured performances of the cells in terms of required silicon area, robustness, read/write speed and energy consumption.

Evaluation of hybrid MRAM/CMOS cells for “normally-off and instant-on” computing

To meet the ever-growing demand for higher computing throughput, the clock frequency of the processor was continually increased. After decades of success, this trend stopped at frequencies of 2---3 GHz due to heating issues and energy consumption. To keep pace, multi-core processor architectures began to rise. This, in turn, significantly increased the amount of the SRAM-based cache memory required. As a result, cache memory now occupies large proportion of recent processor chips. In addition, it has become a major source of the leakage power consumption. The power gating technique applied on a SRAM cache is not efficient since it is paid by data loss and by the significant time and the energy required to retrieve the lost data. In this paper, we present three memory cells that can overcome this issue. They combine a conventional volatile CMOS part with magnetic tunnel junctions (MTJs) able to store a data bit in a non-volatile way. Being inherently non-volatile, these hybrid cells enable instantaneous power off and thus complete reduction of the leakage power. Moreover, given that the data bit can be stored in local MTJs and not in distant storage memories, these cells also offer instantaneous and efficient data retrieval. To demonstrate their functionality, the cells are designed using 28 nm FD-SOI technology for the CMOS part and 45 nm round spin transfer torque MTJs (STT-MTJs) with perpendicular magnetization anisotropy. We report the measured performances of the cells in terms of required silicon area, robustness, read/write speed and energy consumption. We also demonstrate that the body-biasing technique offered by the FD-SOI technology can be used to boost the performances of the hybrid cells.

Spin-torque sensor with tunable sensitivity and detection range

A linear magnetic-field sensor utilizing a MgO-based spin-transfer torque magnetic tunnel junction (STT-MTJ) is demonstrated in this study. In order to obtain a linear field sensor, the behaviour of the resistance, R, versus the magnetic field, H, is controlled by the application of bipolar voltage pulses. The R(H) loops are collapsed completely and show a linear response to the applied field with a sensitivity of 4.21%/Oe in the sensing mode. This loop-collapsing method, i.e. eliminating coercivity, is an important technique in the design of STT-MTJ sensors. The bipolar pulse-driven STT-MTJ sensor was observed to have adjustable sensitivity. Furthermore, the linear response region could be intentionally shifted by applying a varying direct current voltage. This bipolar pulse-driving method for realizing a tunable field sensor is a good candidate for embedded multifunctional sensing devices.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.