Special Function Units Research Articles

Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs

Ensuring the reliability of GPUs and their internal components is paramount, especially in safety-critical domains like autonomous machines and self-driving cars. These cutting-edge applications heavily rely on GPUs to implement complex algorithms due to their implicit programming flexibility and parallelism, which is crucial for efficient operation. However, as integration technologies advance, there is a growing concern regarding the potential increase in fault sensitivity of the internal components of current GPU generations. In particular, Special Function Unit (SFU) cores inside GPUs are used in multimedia, High-Performance Computing, and neural network training. Despite their frequent usage and critical role in several domains, reliability evaluations on SFUs and the development of effective mitigation solutions have yet to be studied and remain unexplored. This work evaluates the impact of transient faults in the main hardware structures of SFUs in GPUs. In addition, we analyze the main overhead costs and benefits of developing selective-hardening mechanisms for SFUs. We focus on evaluating and analyzing two SFU architectures for GPUs (’fused’ and ’modular’) and their relations to energy, area, and reliability impact on parallel applications. The experiments resort to fine-grain fault injection campaigns on an RTL GPU model (FlexGripPlus) instrumented with both SFUs. The results on both SFU architectures indicate that fused SFUs (in commercial-grade devices) require lower area overhead (about 27%) for their integration in GPUs but are more vulnerable to transient faults (in up to 47% for the analyzed cases) and less power efficient (in up to 36.6%) than modular SFUs. Moreover, the reliability estimation shows that Modular SFUs are structurally more resilient than Fused ones in up to one order of magnitude. Similarly, selective-hardening mechanism based on Triple-Modular Redundancy (TMR) shows that coarse-grain strategies might increase the reliability of the overall SFUs under feasible overhead costs.

Hardware Acceleration of Hash Operations in Modern Microprocessors

Modern microprocessors contain several special function units (SFUs) such as specialized arithmetic units, cryptographic processors, etc. In recent times, applications such as cloud computing, web-based search engines, and network applications are widely used, and place new demands on the microprocessor. Hashing is a key algorithm that is extensively used in such applications. Hashing can reduce the complexity of search and lookup from O(N) to O(N/n), where n bins are used. Hashing is typically performed in software. Thus, implementing a hardware-based hash unit on a modern microprocessor would potentially increase performance significantly. In this article, we propose a novel hardware hash unit (HU) design for use in modern microprocessors, at the microarchitecture level and at the circuit level. First, we present the design of the HU at the microarchitecture level. We simulate the HU to compare its performance with a software-based hash implementation. We demonstrate a significant speedup (up to 15×) for the HU. Furthermore, the performance scales elegantly with increasing database size and application diversity, without increasing the hardware cost. Second, we present the circuit design of the HU for use in modern microprocessors, using a 45nm technology. Our proposed hardware hash unit is based on the use of a content-addressable memory (CAM) to implement each bin of the hash table. We simulate the HU circuit and compare it with a traditional CAM design. We demonstrate an average power reduction of 5.48× using the HU over the traditional CAM. Also, we show that the HU can operate at a maximum frequency of 1.39 GHz (after accounting for process, voltage and temperature (PVT) variations and accounting for wiring parasitics). Furthermore, we present the delay, power and area trade-offs of the HU design with varying hash table sizes.

P-318 Survival outcomes among patients with locally advanced gastric cancer treated within a multidisciplinary gastro-esophageal cancer functional unit

Gastric cancer is a complex disease and the third leading cause of cancer deaths worldwide. To date, surgery remains the only curative strategy in locally advanced gastric cancer (LAGC) patients (pt), although the results of the MAGIC trial supported the implementation of a perioperative treatment (ttx) with epirubicin-cisplatin-5FU (ECF). Since 2019, the FLOT4-AIO trial showed that perioperative 5FU-leucovorin-oxaliplatin-docetaxel (FLOT) improved median overall survival (mOS) compared to ECF. We aimed to assess outcome differences in a non-clinical trial scenario in our LAGC cohort, according to multidisciplinary management in a highly specialized gastro-esophageal cancer functional unit (UFEG) integrating different specialists.

P-317 Survival outcomes among patients with locally advanced esophageal cancer treated within a multidisciplinary gastro-esophageal cancer functional unit

Management of locally advanced esophageal cancer (LAEC) is challenging given its aggressive behaviour and that it is often diagnosed in patients (pt) with significant comorbidities. A multimodal approach could enhance treatment results and quality of life. We aimed to assess outcome differences in a non-clinical trial scenario in our LAEC cohort, according to multidisciplinary management in a highly specialized gastro-esophageal cancer functional unit (UFEG) integrated with different specialists.

A Distributed Neural Code in the Dentate Gyrus and in CA1

Neurons are often considered specialized functional units that encode a single variable. However, many neurons are observed to respond to a mix of disparate sensory, cognitive, and behavioral variables. For such representations, information is distributed across multiple neurons. Here we find this distributed code in the dentate gyrus and CA1 subregions of the hippocampus. Using calcium imaging in freely moving mice, we decoded an animal's position, direction of motion, and speed from the activity of hundreds of cells. The response properties of individual neurons were only partially predictive of their importance for encoding position. Non-place cells encoded position and contributed to position encoding when combined with other cells. Indeed, disrupting the correlations between neural activities decreased decoding performance, mostly in CA1. Our analysis indicates that population methods rather than classical analyses based on single-cell response properties may more accurately characterize the neural code in the hippocampus.

An integrated process-based approach to intellectual capital management

PurposeNowadays, the aspects of the intellectual capital (IC) management have become important, valuing it as an integral part of the organisation. Researchers emphasise the strategic importance of IC management, particularly in the context of satisfying the stakeholders' interests and value creation. However, the existing studies reflect individual elements of IC management, not analysing them as a system which is a part of the organisational management system, and hence it is impossible to draw valid conclusions on the impact of IC on the organisation's performance. The aim of the paper is to describe an approach to the elaboration of the IC management strategy and its integration into the organisation's management system.Design/methodology/approachThe developed approach is based on a holistic and systemic view of the organisation, where IC management is integrated into the organisation's management . This approach is based on the structure of IC developed by Lentjušenkova and Lapina (2016). In this structure, business processes are the IC component that unites the other three ones – human capital, technologies and intangible assets. The study has used induction and deduction, as well as analytical and synthetic qualitative research methods, including logical constructive and conceptual (concept) analysis.FindingsElaborating the organisational strategy by taking into account the stakeholder interests, the organisation is able to ensure sustainable development. Using the integrated management approach, IC management is integrated into the organisation's activities and joint operational strategy. In this case, IC management becomes an integral part of the organisation's activities functioning in conjunction with the other organisation's systems, and it is integrated into all ongoing business processes.Research limitations/implicationsThe approach the authors have proposed to IC management could be adapted by small and medium-sized companies. Using it, companies do not need to create special functional units or division, because IC becomes an integral part of organisation's processes.Originality/valueIn previous studies, business processes were considered as one of the components of IC. In the study’s approach, business processes imply integration of IC into the overall organisation management system. As a framework for the proposed approach, the authors have used the Deming cycle “Plan-Do-Check-Act” that envisages dividing the development and implementation of the IC management and development strategy into four phases, with a clear allocation of tasks and a defined outcome for each individual phase. To use this approach, it is enough for organisations to conduct an analysis of processes and, depending on the strategic goals of the organisation, make additions related to managing IC.

Reviewing GPU architectures to build efficient back projection for parallel geometries

Back-Projection is the major algorithm in Computed Tomography to reconstruct images from a set of recorded projections. It is used for both fast analytical methods and high-quality iterative techniques. X-ray imaging facilities rely on Back-Projection to reconstruct internal structures in material samples and living organisms with high spatial and temporal resolution. Fast image reconstruction is also essential to track and control processes under study in real-time. In this article, we present efficient implementations of the Back-Projection algorithm for parallel hardware. We survey a range of parallel architectures presented by the major hardware vendors during the last 10 years. Similarities and differences between these architectures are analyzed and we highlight how specific features can be used to enhance the reconstruction performance. In particular, we build a performance model to find hardware hotspots and propose several optimizations to balance the load between texture engine, computational and special function units, as well as different types of memory maximizing the utilization of all GPU subsystems in parallel. We further show that targeting architecture-specific features allows one to boost the performance 2–7 times compared to the current state-of-the-art algorithms used in standard reconstructions codes. The suggested load-balancing approach is not limited to the back-projection but can be used as a general optimization strategy for implementing parallel algorithms.

Stem cell derived phenotypic human neuromuscular junction model for dose response evaluation of therapeutics

There are currently no functional neuromuscular junction (hNMJ) systems composed of human cells that could be used for drug evaluations or toxicity testing in vitro. These systems are needed to evaluate NMJs for diseases such as amyotrophic lateral sclerosis, spinal muscular atrophy or other neurodegenerative diseases or injury states. There are certainly no model systems, animal or human, that allows for isolated treatment of motoneurons or muscle capable of generating dose response curves to evaluate pharmacological activity of these highly specialized functional units. A system was developed in which human myotubes and motoneurons derived from stem cells were cultured in a serum-free medium in a BioMEMS construct. The system is composed of two chambers linked by microtunnels to enable axonal outgrowth to the muscle chamber that allows separate stimulation of each component and physiological NMJ function and MN stimulated tetanus. The muscle's contractions, induced by motoneuron activation or direct electrical stimulation, were monitored by image subtraction video recording for both frequency and amplitude. Bungarotoxin, BOTOX® and curare dose response curves were generated to demonstrate pharmacological relevance of the phenotypic screening device. This quantifiable functional hNMJ system establishes a platform for generating patient-specific NMJ models by including patient-derived iPSCs.

An efficient implementation of 3D high-resolution imaging for large-scale seismic data with GPU/CPU heterogeneous parallel computing

De-absorption pre-stack time migration (QPSTM) compensates for the absorption and dispersion of seismic waves by introducing an effective Q parameter, thereby making it an effective tool for 3D, high-resolution imaging of seismic data. Although the optimal aperture obtained via stationary-phase migration reduces the computational cost of 3D QPSTM and yields 3D stationary-phase QPSTM, the associated computational efficiency is still the main problem in the processing of 3D, high-resolution images for real large-scale seismic data. In the current paper, we proposed a division method for large-scale, 3D seismic data to optimize the performance of stationary-phase QPSTM on clusters of graphics processing units (GPU). Then, we designed an imaging point parallel strategy to achieve an optimal parallel computing performance. Afterward, we adopted an asynchronous double buffering scheme for multi-stream to perform the GPU/CPU parallel computing. Moreover, several key optimization strategies of computation and storage based on the compute unified device architecture (CUDA) were adopted to accelerate the 3D stationary-phase QPSTM algorithm. Compared with the initial GPU code, the implementation of the key optimization steps, including thread optimization, shared memory optimization, register optimization and special function units (SFU), greatly improved the efficiency. A numerical example employing real large-scale, 3D seismic data showed that our scheme is nearly 80 times faster than the CPU-QPSTM algorithm. Our GPU/CPU heterogeneous parallel computing framework significant reduces the computational cost and facilitates 3D high-resolution imaging for large-scale seismic data.

Hierarchical Multipartite Function Evaluation

Function evaluation is an important arithmetic computation in many signal processing applications, such as special function units in modern graphics processing units (GPUs). Hardware implementations of function evaluation usually consists of lookup tables (LUT) and some simple arithmetic units of multipliers and/or adders. LUT usually takes a significant portion of total area cost, especially when function evaluators are allowed to compute several different arithmetic functions with shared arithmetic units where evaluation of each function needs separate LUT. In this paper, we focus on the category of table-addition (TA) function evaluators that are composed of two types of LUT, table of initial values ( TI ) and table of offset values ( TO ), followed by a multi-operand adder. It has been shown that multipartite table method (MP) has significant improvement over prior similar designs such as symmetric bipartite table methods (SBTM) and symmetric table addition methods (STAM) for applications with low-to-medium precision requirements. This paper presents an extension of MP, called hierarchical multipartite (HMP), which further reduces total table size by applying several levels of table decompositions. Furthermore, we perform the bit-width optimization by jointly considering the impacts of all error sources during the search of best table decompositions, leading to more efficient hardware design. Besides, a new lossless decomposition of TI is presented, resulting in additional saving of table size without incurring any extra errors. Experimental results show that the proposed design can efficiently reduce the total area cost in ASIC and FPGA implementations.

Changes in Protein Expression and Lysine Acetylation Induced by Decreased Glutathione Levels in Astrocytes

Astrocytes and neurons form a highly specialized functional unit, and the loss or gain of astrocytic functions can influence the initiation and progression of different neurodegenerative diseases. Neurons depend on the antioxidant protection provided by neighboring astrocytes. Glutathione (γ-l-glutamyl-l-cysteinyl-glycine) is a major component of the antioxidant system that defends cells against the toxic effects of reactive oxygen/nitrogen species. A decline in glutathione levels has been observed in aging and neurodegenerative diseases, and it aggravates the pathology in an amyotrophic lateral sclerosis-mouse model. Using a SILAC-based quantitative proteomic approach, we analyzed changes in global protein expression and lysine acetylation in primary astrocyte cultures obtained from wild-type mice or those deficient in the glutamate-cysteine ligase modifier subunit (GCLM). GCLM knockout astrocytes display an ∼80% reduction in total glutathione levels. We identified potential molecular targets and novel sites of acetylation that are affected by the chronic decrease in glutathione levels and observed a response mediated by Nrf2 activation. In addition, sequence analysis of peptides displaying increased acetylation in GCLM knockout astrocytes revealed an enrichment of cysteine residues in the vicinity of the acetylation site, which suggests potential crosstalk between lysine-acetylation and cysteine modification. Regulation of several metabolic and antioxidant pathways was observed at the level of protein expression and lysine acetylation, revealing a coordinated response involving transcriptional and posttranslational regulation.

Novel plasticity rule can explain the development of sensorimotor intelligence

Grounding autonomous behavior in the nervous system is a fundamental challenge for neuroscience. In particular, self-organized behavioral development provides more questions than answers. Are there special functional units for curiosity, motivation, and creativity? This paper argues that these features can be grounded in synaptic plasticity itself, without requiring any higher-level constructs. We propose differential extrinsic plasticity (DEP) as a new synaptic rule for self-learning systems and apply it to a number of complex robotic systems as a test case. Without specifying any purpose or goal, seemingly purposeful and adaptive rhythmic behavior is developed, displaying a certain level of sensorimotor intelligence. These surprising results require no system-specific modifications of the DEP rule. They rather arise from the underlying mechanism of spontaneous symmetry breaking, which is due to the tight brain body environment coupling. The new synaptic rule is biologically plausible and would be an interesting target for neurobiological investigation. We also argue that this neuronal mechanism may have been a catalyst in natural evolution.

Floating Point High Performance Low Area SFU

Objectives: Designing a highly accurate high speed low area Special Function Unit (SFU) is the objective of this work. 32 bit IEEE-754 floating point data format is supported in this system. Methods: The SFU implements elementary functions like inverse, exponential, inverse square root, square root and logarithm accurately. The unit can be utilized in programmable graphics processors where high performance and high accuracy evaluation is needed. The coefficients of the elementary functions are optimized by Genetic algorithm. The simulations were carried out in Xilinx EDA tool and MATLAB. Synthesis reports were taken from Cadence RTL compiler. Findings: Coefficient optimization and extraction is done using genetic algorithm by doing curve fitting with a second degree polynomial. There is a significant reduction around 40% in the area when constraint piecewise quadratic genetic approximation scheme is used. The number of iterations performed in optimization algorithm is 104. The percentage of error is 0.2578 %. The circuits operated at a frequency of 228MHz and the power dissipation was found to be 3.94 mW. This results in a highly accurate SFU. Conclusion: A significant advantage in area when compared to other previous techniques is obtained. The SFU can be utilized in programmable graphics engine.

The Calculation and Anticipation Unit for Floating-Point Addition

Most recent microprocessors present multiple special functional units to optimize their performance. In this paper, a new functional unit called the calculation and anticipation (C&A) unit is presented for the IEEE 754 standard floating-point adder (FPA) that is the most important and frequently used calculation part for both modern CPUs and GPUs. C&A unit parallelize rounding step and readjustment step, which are known as the time-consuming steps for floating-point addition with significand addition. Therefore it reduces FPA critical path delay enormously, and even more decreases a little FPA area occupation. The synthesis results show that the double-precision FPA with C&A unit takes about 17.17% improvement in the critical path delay, while saves about 8.32% area than the conventional one. It takes 5.90% advantage in area and 19.58% improvement in the worst case delay than the double-precision FPA from the Open Core module "fpu_double" (rev 14 2010-02-13) synthesized in the same 0.13-μm CMOS bulk. Furthermore, comparing with the two-path double-precision FPA synthesized using LSI Logic's gflxp 0.11-μm CMOS library, it takes about 4.30% advantage in the critical path delay, and saves almost one-third area in the number of the individual cells.

Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System

The world of 3D graphic computing has undergone a revolution in the recent past, making devices more computationally intensive, providing high-end imaging to the user. The OpenGL ES Standard documents the requirements of graphic processing unit. A prime feature of this standard is a special function unit (SFU), which performs all the required mathematical computations on the vertex information corresponding to the image. This paper presents a low-cost, high-performance SFU architecture with improved speed and reduced area. Hybrid number system is employed here in order to reduce the complexity of operations by suitably switching between logarithmic number system (LNS) and binary number system (BNS). In this work, reduction of area and a higher operating frequency are achieved with almost the same power consumption as that of the existing implementations.

Accelerating an application domain with specialized functional units

Hardware specialization has received renewed interest recently as chips are hitting power limits. Chip designers of traditional processor architectures have primarily focused on general-purpose computing, partially due to time-to-market pressure and simpler design processes. But new power limits require some chip specialization. Although hardware configured for a specific application yields large speedups for low-power dissipation, its design is more complex and less reusable. We instead explore domain-based specialization, a scalable approach that balances hardware’s reusability and performance efficiency. We focus on specialization using customized compute units that accelerate particular operations. In this article, we develop automatic techniques to identify code sequences from different applications within a domain that can be targeted to a new custom instruction that will be run inside a configurable specialized functional unit (SFU). We demonstrate that using a canonical representation of computations finds more common code sequences among applications that can be mapped to the same custom instruction, leading to larger speedups while specializing a smaller core area than previous pattern-matching techniques. We also propose new heuristics to narrow the search space of domain-specific custom instructions, finding those that achieve the best performance across applications. We estimate the overall performance achieved with our automatic techniques using hardware models on a set of nine media benchmarks, showing that when limiting the core area devoted to specialization, the SFU customization with the largest speedups includes both application- and domain-specific custom instructions. We demonstrate that exploring domain-specific hardware acceleration is key to continued computing system performance improvements.

Accelerating an application domain with specialized functional units

Hardware specialization has received renewed interest recently as chips are hitting power limits. Chip designers of traditional processor architectures have primarily focused on general-purpose computing, partially due to time-to-market pressure and simpler design processes. But new power limits require some chip specialization. Although hardware configured for a specific application yields large speedups for low-power dissipation, its design is more complex and less reusable. We instead explore domain-based specialization, a scalable approach that balances hardware’s reusability and performance efficiency. We focus on specialization using customized compute units that accelerate particular operations. In this article, we develop automatic techniques to identify code sequences from different applications within a domain that can be targeted to a new custom instruction that will be run inside a configurable specialized functional unit (SFU). We demonstrate that using a canonical representation of computations finds more common code sequences among applications that can be mapped to the same custom instruction, leading to larger speedups while specializing a smaller core area than previous pattern-matching techniques. We also propose new heuristics to narrow the search space of domain-specific custom instructions, finding those that achieve the best performance across applications. We estimate the overall performance achieved with our automatic techniques using hardware models on a set of nine media benchmarks, showing that when limiting the core area devoted to specialization, the SFU customization with the largest speedups includes both application- and domain-specific custom instructions. We demonstrate that exploring domain-specific hardware acceleration is key to continued computing system performance improvements.

Knowledge Modeling and Solving Strategy for Product Innovation Design

Knowledge modeling and solving strategy are the key techniques of improving the innovation design ability of a complex product with design knowledge system. Aiming at a formal expression of product behavior knowledge, generalized variables are introduced from the bond graph theory. The attributes of motion behavior are used to realize the unity of dynamic behavior and static behavior. The ontology model of product design function, behavior, structure knowledge is constructed with the six-tuple structure. With the breadth first search FBS ontology mapping strategy, product design is realized by searching within product design knowledge base according to the name similarity. For the new function introduced by new demand in product design, concept learning based on variant space is proposed to get the general function unit or special function unit. Then the innovation design is realized through FBS ontology mapping strategy. The validity of the proposed method is verified by example of innovation design of multi-wire diamond saw.

Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders

We embed special function units (SFUs) in homogeneous stream processors (SPs) within a graphics processing unit (GPU), to improve its performance in running modern programmable shaders, which make poor use of a single-instruction multiple-data (SIMD) architecture. We also compact instructions, so as to reduce the size of the instruction memory, and reduce area requirements by using a partial SFU in SPs, and a lookup table which is shared between multiple SFUs. The result is an increase of 88% in utilization and a reduction in the normalized area-delay product of 27%, compared to a baseline SIMD architecture. We verified our architecture on an field-programmable gate-array evaluation platform with an ARM9 host processor and a full 3-D graphics pipeline.

A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications

A fully programmable vertex shader based on Transport Triggered Architecture (TTA) is proposed in this paper to provide high efficiency of performance and connectivity for embedded applications. At the architecture level, fine-grained data transport in TTA datapath and multi-threading method are adopted to exploit instruction and data level parallelism respectively in the graphics applications. The datapath connectivity can be optimized mainly by native architectural visible bypass in TTA and hybrid result re-collection schemes. At the shader core level, a novel SIMD multi-functional dot-production unit and an area efficient special function unit are introduced for floating-point processing. The proposed processor which achieves peak capacity of 1.5 GFLOPS and 125 Mvertices/s can totally acquire 17.6% reduction in hardware cost and can provide 1.3 times improvement in performance per logic cost ratio under a 0.18μm CMOS process for real graphics benchmarks compared to previous expanded VLIW vertex processor.