Source Pocket Research Articles

Steep subthreshold swing Double - Gate tunnel FET using source pocket engineering: Design guidelines

In this work, we propose a promising source engineered Double - Gate (DG) Tunnel Field Effect Transistor (TFET) device capable of providing remarkably low value of Subthreshold Swing (SS) with sufficiently high drive current. Using Sentaurus TCAD simulations, we demonstrate that counter-doped horizontal pockets (doping of pocket is kept opposite to that of source) when placed in the source region introduces a built-in band bending at the source-pocket junction. This lowers the minima of Conduction Band (CB) in pocket region thereby reducing the barrier width as the pocket CB moves closer to source Valence Band (VB). As a result, stronger electric field is observed thereby reducing the threshold voltage (onset of band-to-band tunneling (BTBT)) and subsequent reduction in subthreshold swing. To boost the ON-current and suppress ambipolarity, high-k dielectric material along with low work-function gate material is introduced at source side and low-k gate dielectric along with high work-function gate material is introduced at drain side. Compared to point tunneling in conventional TFETs, the gate overlapped pockets in the proposed structure result in an increase in cross-section area available for BTBT thereby leading to line tunneling of carriers from the source to the pocket, resulting in higher ON-current. In this work, we discuss the role of source engineering in boosting the performance of Hetero-Dielectric (HD) Dual-Metal-Double-Gate (DMDG) TFET. We provide design guidelines to achieve steeper subthreshold swing while considering pocket doping and pocket thickness as the key parameters. A comparative study of conventional DG-TFET and HD-DG-TFET with the proposed Gate-over-Pockets (GoP) HD-DMDG-TFET structure is done. When compared to the conventional DG-TFET with same geometrical parameters, the proposed structure provides ∼33× steeper SS, more than two order improved ON-current, two order lower ambipolar current and 133 folds better Ion/Ioff thus becomes the perfect choice for low power applications.

Cutting-edge vertical tunnel FETs: GaSb/InSb heterojunction source-all-around tunnel FET with I60 of 2.73×10⁻⁴ A/μm and Sub-10 mV/dec SS

This work introduces an innovative Source-All-Around Vertical Tunnel Field-Effect Transistor (SAA-VTFET) design based on III-V semiconductors. The unique combination of a GaSb/InSb heterojunction, a wider tunneling space, and an n+ source pocket significantly enhances band-to-band tunneling (BTBT), leading to exceptional on-current levels. The device architecture utilizes InSb in the source pocket and channel, materials chosen for their properties that enable efficient carrier transport, ultimately boosting overall device performance. Through meticulous optimization, the SAA-VTFET achieves an I60 (Ids at SS = 60mV/dec) of 2.73 × 10−4 A/μm, an exceptionally low off-current of 1.7 × 10−17 A/μm, a low threshold voltage of 0.16 V, an outstanding ION/IOFF Ratio of 1.64 × 1013, and an attractive subthreshold swing (point SS of 4 mV/dec, average SS of 7 mV/dec). These remarkable achievements underscore the SAA-VTFET's potential to surpass conventional TFETs, paving the way for advanced low-power, high-speed electronics.

Analog and linearity performance analysis of ferroelectric vertical tunnel field effect transistor with and without source pocket

AbstractThis study examines the electrical performance characteristics of a ferroelectric vertical tunnel field‐effect transistor (TFET) with and without a source pocket (Si0.5Ge0.5). The incorporation of Germanium in the source of the TFET aims to enhance the on‐current. The Silvaco TCAD simulation tool is utilized to simulate the proposed structure. To improve device performance, a ferroelectric layer with a vertical length is employed in the gate of the TFET. When the ferroelectric layer partially controls the channel region, device characteristics, such as on‐current and subthreshold swing (SS) can be improved (i.e., ION = 15.21 × 10−5 A/μm, ION/IOFF = 5.03 × 109, and a minimum SS of 20.87 mV/decade at 300 K). This article studied a comparison between ferroelectric vertical TFETs and nonferroelectric vertical TFETs, as well as ferroelectric vertical TFETs with and without source pockets. The comparison is done on the basis of DC and RF parameters. Analysis of this comparison represents that ferroelectric vertical TFET with source pocket has improved characteristics.

GaSb/Si Heterojunction Based Pocket Engineered Vertical Non-Uniform Channel Double Gate TFETs for Low Power Applications

This article compares the performance of two Vertical Non-Uniform Channel Double Gate Tunnel Field Effect Transistors (VNUCDGTFETs), a normal all-Silicon Tunnel Field-Effect Transistor (TFET) having a pocket and another one a Gallium Antimonide/Silicon heterojunction TFET with pocket. GaSb is a III-V narrow energy band gap material, employed in the source area of the TFET structure to decrease the tunneling width and thus to make more number of carriers capable enough to tunnel through the heterojunction. The proposed source pocket heterojunction non uniform channel TFET presents superior performance as compared to the conventional non uniform channel vertical TFET with a pocket, regarding a larger ION/IOFF ratio, a reduced sub-threshold swing, and a smaller threshold voltage at VDS = 0.5 V. Furthermore, the proposed TFET device undergoes a comprehensive analysis of both DC parameters and various analog/RF parameters.

Analysis of Negative Capacitance Source Pocket Double-Gate TFET with Steep Subthreshold and High ON–OFF Ratio

Analysis of Negative Capacitance Source Pocket Double-Gate TFET with Steep Subthreshold and High ON–OFF Ratio

Circuit Level Implementation of Negative Capacitance Source Pocket Double Gate Tunnel FET for Low Power Applications

This manuscript presents a pioneering study on enhancing analog and radio frequency performance through the implementation of negative capacitance source pocket double gate tunnel field-effect transistor. By integrating a ferroelectric material into the gate stack and introducing a fully depleted n-type pocket near the source/channel junction, we achieved significant enhancements in key metrics such as ON current (ION), switching ratio, subthreshold swing (SS), and various analog/RF parameters like transconductance (gm), cutoff frequency (fT) when compared to existing literature. Additionally, we extend our analysis to circuit-level applications such as inverter and 5-stage ring oscillator. Our findings reveal an impressive inverter delay of 1.09 ps with a gain of 104, as well as a ring oscillator operating at a frequency of 500 GHz. These results position the proposed device as an ideal candidate for high-speed, low-power applications.

Design, optimization, and performance analysis of GaP/Si heterojunction Fin-TFET with MoS2 nanoribbon channel

This article presents the design and optimization of GaP/Si heterojunction Fin-TFET with a MoS2 channel. The elevated fin structure, coupled with ultrathin MoS2 layers and the tuneable bandgap properties of MoS2 material, significantly enhances gate control over the channel and improves device performance. Additionally, the GaP/Si heterojunction with a heavily doped n-type source pocket leads to a narrow barrier junction, promoting Band-to-Band Tunneling (BTBT). The optimized Fin-TFET boasts exceptional electrical characteristics: a high ON-current (7.72 × 10−5 A/μm), an ultra-low OFF-current (4.16 × 10−17 A/μm), and leading to an outstanding ION/IOFF ratio (7.23 × 1012). Furthermore, the device demonstrates a steep subthreshold slope (SS) of 6 mV/dec (point) and 16.8 mV/dec (average), alongside impressive analog performance with a transconductance (gm) of 2.75 × 10−4 S, a cut-off frequency (fc) of 1.3 × 1012 THz, and a gain-bandwidth product (GBP) of 0.17 × 1012 THz. The entire analysis was conducted utilizing the Sentaurus TCAD-3D simulation tool.

A new approach for ammonia gas sensing using a source pocket dopingless tunnel FET with PANI catalyst

This article presents a new ammonia (NH3) gas sensor designed using a dopingless tunnel field effect transistor with a SiGe source pocket (SP-DLT) and investigates its sensitivity using a polyaniline (PANI) conducting polymer as the gate catalyst. PANI nanofiber has a greater specific surface area and a linked network structure, which increases its sensing performance as a catalyst. Combining an HfO2 gate dielectric and SiGe source pocket improves the drain current. The sensing film is deprotonated when the PANI conducting polymer is exposed to the gas, reducing the film’s resistance. As a result, more electron or proton transfer is possible, ensuring a more substantial interaction between the sensor and the analyte gas. This modulates the electrical characteristics and work function of the TFET. The sensor’s electrical performance is examined in terms of drain current, average subthreshold swing (SS), electric field, band-to-band tunneling rate (BTBT), and energy band diagram for an ammonia gas pressure (AGP) range of 10−12 torr to 10−9 torr. The sensitivity and selectivity of the proposed PANI-SP-DLT sensor in terms of different metrics, including drain current, average SS, current ratio, transconductance, and gain factor, are further investigated. The study is expanded to consider the impact of temperature affectability and the germanium mole fraction on current sensitivity performance. The Silvaco ATLAS device simulator is used for the brief simulation work for the developed gas sensor.

Design and Modelling of Tunnel Field Effect Transistor- using TCAD Modeling

The purpose of this research was to suggest a junction-less strategy for a vertical Tunnel Field Effect Transistor, which would increase the device's efficiency. In this study, we examine the similarities and differences between a negative capacitor TFET and a vertically generated TFET with a source pocket and a heterostructure-based nanowire gate. And how the channel transit impacts the output qualities of a sub-100 nanometer sized device. The Silvaco TCAD (a commercially available tool) was used to simulate a tri-layer high-K dielectric made of hafnium zirconium oxide (HZO) and titanium dioxide (TiO2) materials as gate stacking to the V-TFET and GAA-NC-TFET structures, and the tunnelling and transport parameters were calibrated experimentally. A short bandgap material, GaSb, in the home region to enhance carrier tunnelling via the mentioned three source (GaSb)-channel (Si) heterojunction at varying biases were utilized. Motion, tube length, and saturating velocity are only few of the transport channel characteristics that are investigated. As a result of the building's vertical orientation, the electric field is enhanced, allowing for an ION current of up to 104 Am2. The most unexpected result of this device is that a high ION/IOFF may increase mobility and reduce saturation velocity, perhaps reducing the drain voltage at saturation. The proposed biosensor's sensitivity was multiplied by 108 when vertical and lateral tunnelling were used in tandem. We apply a variety of optimisation strategies to deal with this problem, despite the fact that quantum confinement reduces the effect of mobility variations on device performance. When biomolecules were positively charged, the drain current increased, and when they were negatively charged, the drain current decreased.

Assessing the Impact of Source Pocket Length Variation to Examine DC/RF to Linearity Performance of DG-TFET

This research examines the variation in source pocket length at the corner region of source–channel interface (SCi) with hetero-oxide triple metal gate. The investigated DC and analog parameters include energy band profile in ON/OFF state, electric field ([Formula: see text]), potential, transconductance ([Formula: see text]), capacitance gate to source and gate to drain ([Formula: see text], [Formula: see text]), cut-off frequency ([Formula: see text]), gain bandwidth product, transconductance generation factor, transconductance frequency product, transit time ([Formula: see text]) and for linearity figure of merit it includes [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], 1-dB compression point. The comprehensive study is done with varying lengths of source pocket, and while keeping doping of source pocket same and keeping work function of triple metal gate constant, it shows the enhancement in overall device performance triple metal gate hetero-oxide corner source pocket double gate TFET (TMG-HO-CSP-DGTFET).

Performance Investigation of GaSb/Si Heterojunction based Gate Underlap and Overlap Vertical TFET Biosensor.

The present paper estimates the performance of vertically developed double gate GaSb/Si tunnel field-effect transistor (V-DGTFET) biosensor with source pocket. A commercially accessible tool, Silvaco-TCAD, is exploited for carrying simulations of V-DGTFET. The device's novelty is deploying a material with a small bandgap, namely GaSb, in the source region to improve the carrier tunneling in source-channel (GaSb-Si) heterojunction. Further, the present work has analysed the performance on half gate underlap and half gate overlap V-DGTFET based label-free biosensor. The performance of V-DGTFET biosensor corresponding to various biomolecules such as APTES with κ=3.57, bacteriophage-T7 with κ=6.4, apomyoglobin with κ =8.1 and gelatin with κ=12 is investigated with reference to energy band diagram, potential profile, electric field and drain characteristics. Furthermore, by considering the different values of dielectric constants from 1 to 12, the present paper computed the figure of merits (FOMs) essentially linearity and sensitivity. The results demonstrated that neutral biomolecules with higher dielectric constant values showed higher sensitivity compared with other biomolecules. Moreover, it is estimated that gelatin has to drain current sensitivity of 5.6×105, which is 13%, 20%, and 41% more in comparison to apomyoglobin (κ =8.1), bacteriophage-T7 (κ=6.4), and APTES (κ =3.57) sensitivity at 15 nm cavity length.

Application of a Charge Plasma Tunnel FET with SiGe Pocket as an Effective Hydrogen Gas Sensor

In this article, we have investigated the potential applications of a charge plasma TFET with a source pocket (SP-CPTFET) as a hydrogen gas sensor. The Si0.6Ge0.4 source pocket and HfO2 gate dielectric together greatly enhance the drain current. The presence of an intrinsic silicon body in the channel and drain controls the leakage current. Palladium (Pd) is considered the top and bottom gate catalyst for hydrogen (H2) gas sensing. The flat band voltage and CV properties of the sensor change as a result of the adsorption of H-atoms at the Pd-HfO2 and Pd surfaces. As a result, the gate work-function () modulates, affecting the drain current. The electrical analysis of the sensor is carried out in terms of transfer characteristics, band energy, current ratio, interband tunneling rate, and electric field. Additionally, the suggested sensor’s drain current sensitivity and current ratio sensitivity are estimated for various H2 pressure concentrations. The scope of the investigation has been expanded to include the effect of variation in the H2 gas pressure, germanium mole fraction, temperature, pocket length, interface trap charges (ITC), oxide thickness variation, and comparison of different catalytic metals on the drain current performance. The reported sensor exhibits a much-improved drain current sensitivity and current ratio sensitivity compared to the CPTFET gas sensor.

Performance investigation of a charge plasma tunnel FET with SiGe source pocket as a photosensor

This study investigates a highly sensitive and low-power photosensor using a pocket-based charge plasma tunnel field-effect transistor (PCPTFET) structure for visible light detection. Here, zinc oxide, the transparent optical region over the channel, is the catalyst for the photo-sensing operation. When light strikes the sensitive portion of the device, creating optical charge carriers in the illumination region and substantially increases the device’s conductance. The analysis of various parametric and structural variations like intensity power density (Pj ), optical wavelength (λ), drain to source voltage (V DS), incident angle (θ), and silicon body thickness (t si) have been investigated for the reported pocket-based charge plasma TFET (PCPTFET) photosensor. Further, the PCPTFET’s superior performance as a highly sensitive photosensor is revealed by comparing the several optical figures of merit (FOM) with conventional tunnel field-effect transistor. The reported photosensor provides much-improved responsivity (R) of 1.52 A W−1 and quantum efficiency (η) of 4.96.

Design and investigation of dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal pocket TFET device as a label-free biosensor

In this article, a dielectric modulated triple metal gate-oxide-stack Z-shaped gate horizontal source pocket tunnel field-effect transistor (DM-TMGOS-ZHP-TFET) structure has been investigated for the application of label free-biosensor. This work explores the advantage of gate work function engineering along with the gate-oxide-stack approach for the ZHP-TFET for the first time. An asymmetric nano-cavity is created adjacent to the source-channel junction to immobilize the target biomolecules conjugation to the proposed device. The sensitivity of the device is thoroughly investigated in terms of average subthreshold swing (SS), threshold voltage (V th) and the switching ratio (I on/I off) of the proposed device with the variation of the dielectric constant value inside the nano-gap under the gate electrode. The device characteristics are investigated with different combinations of metal work functions to match the desired feature and sensitivity of the device. In addition, the sensitivity analysis of the proposed device is analyzed in the presence of both positive and negative charged biomolecules in the cavity region to study the charge effect on label-free detection of the device. A comparative study is conducted between a single metal gate (SMG) ZHP-DM-TFET biosensor with the DM-TMGOS-ZHP-TFET biosensor explores the advantage of gate-work function engineering with a gate-oxide-stack approach. Interestingly the DM-TMGOS-ZHP-TFET biosensor shows superior results with a high current ratio sensitivity of 103 which is ten times more than the SMG-ZHP-DM-TFET biosensor and this device also exhibits low subthreshold characteristics.

CONTROLLING AMBIPOLAR CURRENT AND ENHANCEMENT OF ON-STATE CURRENT WITH HIGH AND LOW CONCENTRATION SOURCE POCKETS

This paper proposes and investigates a new architecture of PNPN TFET by using 2-D ATLAS Device Simulation Software TCAD Tool. The source pocket plays a crucial role in increasing the ON-state current through Tunnel FET. In order to enhance the source pocket characteristics, the source pocket is divided laterally into high and low concentration source pockets without modulating its width (LP). This modification results in reduction of tunnelling width (?), thereby increasing the significant amount of lateral electric field and suppressing the horizontal electric field, which in turn enhance the tunnelling probability as well as tunnelling rate. This proposed structure is a promising candidate for getting higher ON-state current (Ion), higher current ratio (Ion/Ioff), lower threshold voltage (VT) and reduced steepness sub-threshold slope (SS). These parameters are calculated with respect to conventional PNPN TFET and hetero-dielectric BOX (HDB) PNPN TFET, which enable the device to be operated efficiently with lower power consumption.

Modeling of Source Pocket Engineered PNPN Tunnel FET on High-K Buried Oxide (H-BOX) Substrate for Improved ON Current

Modeling of Source Pocket Engineered PNPN Tunnel FET on High-K Buried Oxide (H-BOX) Substrate for Improved ON Current

Source pocket-engineered hetero-gate dielectric SOI Tunnel FET with improved performance

In this paper, we have studied and proposed a planar Tunnel FET device with source side SiGe pocket and hetero-gate dielectric structure that works by utilizing quantum mechanical Band-to-Band tunnelling (BTBT) mechanism. Simulation results obtained using a calibrated SILVACO TCAD device simulator show that the device exhibits good ambipolar performance because of the hetero-gate dielectric and the use of source pocket leads to steep point subthreshold swing of 4.90 mV/dec., an average subthreshold swing of 25.31 mV/dec. and a threshold voltage of 0.23 V. For including the hetero-gate dielectric, the variation in drain current values with high-κ dielectric length is analysed. The change in transfer characteristics with pocket parameters including pocket length and pocket doping is also reported. A 4 nm Si0.7Ge0.3 n+ pocket with doping concentration of 5 × 1019 cm−3 is found to show the maximum ON-OFF current ratio of 5.23 × 1011. This paper also performs a comparative study between different TFET structures and the analysis clearly highlights the potential of proposed Source Pocket-Engineered Hetero Gate Dielectric (SPE-HGD) TFET device for low-power and energy-efficient applications.

Lateral and Vertical Gate Oxide Stacking Impact on Noise Margins and Delays for the 8T SRAM Designed With Source Pocket Engineered GaSb/Si Heterojunction Vertical TFET: A Reliability Study

This work investigates the impact of gate-oxide stacking on the performance of source-pocket engineered (SPE) GaSb/Si heterojunction (HJ) vertical TFETs (VTFETs) based 8T SRAMs. The 8T SRAMs circuits are designed using the SPE-HJ-VTFETs with three different gate-oxide engineered structures: laterally stacked HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate-oxide, vertically stacked Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate-oxide and only Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> as gate-oxide. The surface potential, electric field, transfer characteristics, drain characteristics and intrinsic capacitances of all three types of VTFETs considered in this paper are compared. The read static noise margin (RSNM), write margin (WM), read delay as well as write delay of the SRAMs designed by three forms of the SPE GaSb/Si HJ-VTFETs structures have been compared. It is shown that the intrinsic capacitances originated from different stacking-based gate-oxide structures affect the performance of the SRAM significantly. The read delay is significantly the highest for the 8T SRAM designed by laterally stacked gate-oxide based SPE-HJ-VTFETs than the other two 8T SRAMs under consideration. Electrical performance analysis of the VTFETs under study has been studied using commercially available SILVACO ATLAS TCAD tool whereas performance analysis of the 8T SRAMs have been carried out utilizing CADENCE Virtuoso tool by virtue of Verilog A code.

Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide

This work reports the impact of interface trap charges (ITCs) on the electrical performance characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET (V-TFET) with an HfO2/Al2O3 laterally stacked heterogeneous gate oxide (LSHGO) structure. SILVACO ATLAS™ 3-D TCAD tool has been used to compare various electrical performance parameters which includes DC parameters (i.e. ION, IOFF, ION/IOFF and subthreshold swing), RF figures of merit (i.e. transconductance, output conductance, cut-off frequency, the maximum frequency of oscillation, transit time, gain bandwidth product, transconductance generation factor (device efficiency) and transconductance frequency product) and linearity figures of merit (i.e. gm2, gm3, Third order voltage intercept point (VIP3), third intercept input power (IIP3), third order intermodulation distortion power (IDM3), 1-dB compression point and zero crossover point (ZCP)) of the proposed Ge/Si SPE-HJ-LSHGO-V-TFET with their corresponding values of SPE-HJ-V-TFET with only Al2O3 as the gate oxide for both donor (+ve) and acceptor (−ve) interface trap charges at the gate oxide/channel interface. The reported study shows that the proposed HfO2/Al2O3 based SPE-HJ-LSHGO-V-TFET device is more immune to ITCs than the SPE-HJ-V-TFET device with only Al2O3 as the gate oxide.

Design of Si0.45Ge0.55-based core–shell-type dual-material dual-gate nanotube TFET with source pocket technique

Design of Si0.45Ge0.55-based core–shell-type dual-material dual-gate nanotube TFET with source pocket technique