Source Field Plate Research Articles

Effect of lateral inhomogeneous AlGaN barrier layer on electronic properties of GaN HEMTs

In this study, an AlGaN/GaN high electron mobility transistor with lateral inhomogeneous AlGaN barrier layer (LI-AlGaN HEMT) is proposed and studied systematically. The LI-AlGaN HEMT comprises three AlGaN regions with varying Al content, connected to the source, gate, and drain, respectively. With the increase of Al content in each region, the saturation current of the LI-AlGaN HEMT increases gradually, while the on-resistance (Ron) and breakdown voltage (BV) decrease. The threshold voltage (Vth) of the LI-AlGaN HEMT depends only on the Al content of AlGaN beneath the gate. By introducing the source field plate (FP), the calculated output current of the conventional FP-HEMT is consistent with the experimental data. After optimizing Al content, the LI-AlGaN FP-HEMT has the same Vth compared with conventional FP-HEMT. However, the saturation current is increased by approximately 20 % and the Ron is decreased by approximately 30 %. Additionally, the BV is increased to 1008 V. So the optimized lateral inhomogeneous AlGaN HEMT has better DC characteristics and is suitable for high power GaN device applications.

Using U-Net convolutional neural network to model pixel-based electrostatic potential distributions in GaN power MIS-HEMTs

This study demonstrates a novel use of the U-Net convolutional neural network (CNN) for modeling pixel-based electrostatic potential distributions in GaN metal–insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) with various gate and source field plate designs and drain voltages. The pixel-based images of the potential distribution are successfully modeled from the developed U-Net CNN with an error of less than 1% error relative to a TCAD simulated reference of a 500-V electrostatic potential distribution in the AlGaN/GaN interface. Furthermore, the modeling time of potential distributions by U-Net takes about 80 ms. Therefore, the U-Net CNN is a promising approach to efficiently model the pixel-based distributions characteristics in GaN power devices.

Analysis of breakdown voltage for GaN MIS-HEMT with various composite field plate configurations and passivation layers

The effects of different field plate designs on the breakdown voltage of GaN Metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) were examined in this study. The study's primary goal was to determine the dependence of breakdown voltage with respective to composite field plate designs using TCAD simulation. For devices featuring only G-FP, with a fixed gate to drain distance of 15 μm and a fixed G-FP to drain distance of 15 μm, the maximum breakdown voltage was achieved 1 μm G-FP. Breakdown voltage trends were also determined for composite field plate configurations, such as adding a source field plate (S-FP) or a drain field plate (D-FP) with a fixed 1 μm G-FP length. A further enhancement in device breakdown performance was demonstrated by employing a novel D-FP structure. A single D-FP improves the breakdown voltage from 1.4 kV (conventional breakdown voltage with 1um G-FP) to 1.6 kV when combined with 1 μm G-FP, while the novel two-step D-FP achieves a breakdown voltage of about 1.7 kV when combined with 1 μm G-FP. We also investigated the influence of high-k dielectric passivation layers on the breakdown voltage. The breakdown voltage of the devices with optimized G-FP can be further improved by using high-k dielectric material as a passivation layer. The thorough investigations contribute to a better understanding of GaN MIS-HEMT breakdown characteristics and prospective pathways for improving their performance via unique field plate designs and superior dielectric materials.

Optimization of 150 nm GaN HEMT for Ku-band applications using field plate engineering

This work presents a systematic study to achieve the best result of having high breakdown voltage with high-frequency operation for a 150 nm GaN HEMT device (fabricated) using different field plate engineering techniques. The device breakdown voltage, cut-off frequency and maximum frequency should be high for high power and high frequency applications. The conventional device has a lower breakdown voltage but good cut-off and maximum frequency ranges. Field plate engineering has been done for breakdown improvement. However, the device's frequency operation is hampered by the typical source and gate field plate. As a result, an Air bridge source connected field plate and floating gate field plate architectures are explored and investigated. The best outcome is obtained with air bridge source connected field plate with VBOff = 100 V maintaining the cut-off frequency and maximum frequency at 29.8 GHz and 50.3 GHz respectively which is suitable for high power and high frequency applications.

Improved breakdown voltage mechanism in AlGaN/GaN HEMT for RF/Microwave applications: Design and physical insights of dual field plate

This work investigated and proposed the source–gate dual field plate (SG-FP) AlGaN/GaN HEMT for different gate-to-drain drift distances with a fixed gate length of 0.25 μm using ATLAS-TCAD. The increment in the GaN buffer thickness and gate-to-drain drift distance with the variation in the field plate length improves the device performance and breakdown voltages by maintaining the impact ionization mechanism. The breakdown voltage behavior, physical insights of electric field contour, impact generation rate, and potential profile intricacies of source field plate (S-FP), gate field plate (G-FP), and dual field plate (SG-FP) are illustrated. The proposed source–gate dual field plate (SG-FP) with the SiN passivation interfacial layer, SiO2, thicker GaN buffer, and extended gate-to-source drift region is best suited for optimal performance in high breakdown voltage, with optimum cut-off frequency and low gate-leakage current. The proposed dual field plate AlGaN/GaN device with the source field plate (LS-FP = 4 μm), gate field plate (LG-FP = 2 μm), the AlGaN buffer thickness of 3.697 μm, and gate-to-drain drift distance of 8 μm show the highest breakdown voltage of 562 V with the optimum frequency of 8.861 GHz. Finally, the AC/DC characteristics of the optimized dual field plate (SG-FP) are demonstrated. We observed that the source–gate dual field plate (SG-FP) device shows a 6.70% and 4.09% improvement in breakdown voltage compared to individual source field plate (S-FP) and gate field plate (G-FP) designs, respectively. This work shows that the proposed dual field plate device is used in power switching, high-power, and RF/Microwave applications due to its superior breakdown voltage performance, reduction in parasitic capacitances, and optimal cut-off frequency.

DC and RF performance of HR Si(111)-based AlGaN/GaN MIS-HEMT with a symmetrical multi-finger grid array structure for 5G N28 700MHz low-bias-control applications

HR Si(111)-based AlGaN/GaN metal insulator semiconductor high electron mobility transistor (MIS-HEMT) for 5G mobile communication at N28 700 MHz band is proposed in this paper. The device is ingeniously designed with a symmetrical dual-column multi-finger grid array structure. In addition, the device is designed with an MIS gate with a 6 nm SiN dielectric film to suppress the leakage current and a source field plate to suppress the current collapse effect. The fabrication process of the device is studied in detail, including the epitaxial surface treatment, F ion implantation isolation, ohmic contact, electron beam lithography gate process, surface passivation, and source field plate. A device with a gate length of 0.25 μm, gate-source space of 1 μm, a gate width of 1200 μm (the number of gate fingers is 12 with a single-finger gate width of 100 μm), and source field plate length of 0.2 μm is fabricated successfully. Results of electrical tests show that the HEMT device has a threshold voltage of about −7.5 V, a low knee voltage of about 4 V, a high saturation drain current density of 750 mA/mm, and a gate leakage current as low as less than 160 pA at the gate bias of 0 V. At the frequency band of 703–803 MHz, with low bias control of 10 V, the S21 of HEMT is about 5.923–7.261 dB, the gain flatness is 1.338 dB, the current gain is about 27.3 dB, and the stability factor is more than 1. This device would be a good candidate for future 5G low-frequency and low-voltage-control applications.

Exploring the efficacy of implementing field plate design with air gap on β-Ga2O3 MOSFET for high power & RF applications

In the present work, source field plate design with an air gap has been studied on lateral β – Ga2O3 MOSFET with the objective of achieving improvement in high power as well as RF performance by employing exhaustive TCAD simulations. A comprehensive investigation of various analog Figure of Merits (FoMs) and RF Figure of merits (FoMs) have been carried out and a thorough comparison has been drawn between the proposed device β-Ga2O3 MOSFET with source field plate and air gap, the β-Ga2O3 MOSFET with gate field plate and the conventional β-Ga2O3 MOSFET. It can be noted that the proposed design yields significantly higher breakdown voltage and Power Figure of Merit (PFoM) as compared to gate field plate design and conventional device without any of these designs and also, the proposed design demonstrates improvement in RF performance as compared to gate field plate design.

The Device Instability of p-GaN Gate HEMTs Induced by Self-Heating Effect Investigated by on-State Drain Current Injection (DCI) Technique

In this work, the device stability of p-GaN gate HEMTs under self-heating effect is comprehensively investigated by the ON-state drain current injection (DCI) technique. By delicately modulating the DCI condition, the devices exhibit different chip temperatures ranging from 40 °C to 150 °C, while the devices show quite distinguishing instability behaviors. Particularly, substantial threshold voltage shift and saturation drain current degradation is constantly observed in the device with severe self-heating effect after DCI stress. Significant <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> shift of +0.83 V and saturation current reduction up to 18% are observed after the DCI stress, corresponding to a chip temperature of ~150 °C. After the device degradation, the device characteristics show a recoverable dynamic. By investigating the gate leakage current together with the electrothermal device TCAD simulation, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> instability induced by the self-heating is revealed to be the electron trapping in the p-GaN gate-stack, while the saturation drain current degradation originates from a composited action of thermally enhanced electron trapping/de-trapping in p-GaN gate-stack as well as the access region at the hot spot close to the source field plate. The results reported in this work suggest that self-heating is a critical issue that may cause unstable operation of p-GaN gate HEMTs. The revealed underlying mechanisms are beneficial for further improving device stability.

Effect of Source Field Plate Cracks on the Electrical Performance of AlGaN/GaN HEMT Devices

In the current study, the effects of cracks in source field plates (SFPs) on the electrical performance of AlGaN/GaN high electron mobility transistors (HEMTs) are investigated systematically using numerical simulation. In detail, the influence of crack width and junction angle in SFPs on device performance is studied. The results indicate that the SFP structure increases the breakdown voltage of a device, but the occurrence of cracks causes premature breakdown, which is confirmed experimentally by the structural analysis of these devices after breakdown. With an increase in crack width, the electrical performance becomes worse. A beveled SFP architecture is proposed by increasing the angle at the SFP junction to reduce the probability of cracking and enhance the reliability of the device. However, with an increase in bevel angle, the modulation effect of the SFP on the channel electric field is gradually weakened. Therefore, it is necessary to balance the relationship between electrical performance and bevel angle according to the actual demands. This work provides potential support for SFP structural optimization design for AlGaN/GaN HEMTs.

Study of Normally-Off AlGaN/GaN HEMT with Microfield Plate for Improvement of Breakdown Voltage.

In this paper, we introduce a new type of AlGaN/GaN high electron mobility transistor (HEMT) with microfield plate (FP). We use Silvaco-ATLAS two-dimensional numerical simulation to calculate the performance of conventional HEMT and HEMT with micro-FP and analyze its principle. By studying a new charge balance method provided by HEMTs and micro-FPs, the physical mechanism of FP adjusting the HEMT potential distribution and channel electric field distribution is analyzed. The new FP structure consists of a drain field plate (D-FP), a source field plate (S-FP) and several micro-gate field plates (G-FP) to improve the output characteristics of HEMTs. By adjusting the distribution of potential and channel electric field, a wider and more uniform channel electric field can be obtained, and the breakdown voltage can be increased to 1278 V. Although the on-resistance of the HEMT is slightly increased to 5.24 mm, it is still lower than other reference values. These results may open up a new and effective method for manufacturing high-power devices for power electronics applications.

First demonstration of X-band AlGaN/GaN high electron mobility transistors using free-standing AlN substrate over 15 W mm−1 output power density

In this letter, we successfully achieved high-power radio frequency (RF) operation of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on free-standing AlN substrate at X-band. The developed HEMT on AlN substrate comprised a 200 nm thick GaN channel and AlGaN buffer with an Al composition of 30%. Thanks to high breakdown voltage of the HEMT on AlN substrate, we successfully demonstrated 15.2 W mm−1 output power density at operating voltages of 70 V even without device technologies such as source-field plate and optimization of device dimension. Our results show that the potential of GaN HEMTs on AlN substrate as next-generation high-power RF devices.

Impact of Structural and Process Variations on the Time-Dependent OFF-State Breakdown of p-GaN Power HEMTs

In this article, we present an extensive investigation of the time-dependent drain breakdown occurring in GaN-on-Si power HEMTs with p-GaN gate under long-term OFF-state stress. In particular, the time-dependent breakdown induced by high-temperature-reverse-bias stress is investigated as a function of different process and structural variations. Main results demonstrate that, by varying the gate-to-drain distance ( $\text{L}_{\mathrm{ GD}}$ ) and the field plates configuration, the physical location of failure changes as well. If $\text{L}_{\mathrm{ GD}}$ is relatively short ( $3~\mu \text{m}$ ), the time-dependent breakdown occurs through the GaN channel layer between drain and source. In this case, a thinner GaN layer significantly improves the device robustness to long-term OFF-state stress. If $\text{L}_{\mathrm{ GD}}$ is relatively long ( $\ge 4 ~\mu \text{m}$ ), the failure occurs between the two-dimensional electron gas (2DEG) and the source field plates. In this second case, the GaN layer thickness and $\text{L}_{\mathrm{ GD}}$ have no significant impact on the time-dependent breakdown, whereas the field plate lengths can be optimized to reduce the area exposed to high electric fields, hence limiting the probability of failure. Finally, the role of the AlGaN barrier layer has been analyzed as well. If $\text{L}_{\mathrm{ GD}} = 3 ~\mu \text{m}$ , a thinner AlGaN layer is preferred, whereas if $\text{L}_{\mathrm{ GD}} \ge 4 ~\mu \text{m}$ , a thicker layer with lower aluminum content gives rise to longer time to breakdown under OFF-State stress.

Challenges to overcome breakdown limitations in lateral β-Ga2O3 MOSFET devices

In this work, the fabrication of high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs) on Si-doped homoepitaxial layers on (100) Mg-doped semi-insulating β-Ga2O3 substrates is demonstrated. Furthermore, the influence of additional gate and source field-plates is analyzed in regards to the breakdown properties of the MOSFET devices. The comparative study reveals comparable transistor performances of devices with and without field-plates showing maximum drain currents, on/off-current ratios and ON-resistances of ~75 mA/mm, 109 and 110 Ω∙mm, respectively. Moreover, both MOSFET structures show comparable breakdown voltages at around 1200 V which equals an average breakdown field strength of 2 MV/cm emphasizing no influence of the field-plates on the breakdown properties. Analysis of the thin film composition by secondary ion mass spectrometry on the processed β-Ga2O3 wafers indicates an increased concentration of silicon dopants at the interface between epitaxial layer and substrate. Our findings suggest that this might be the current main limitation factor in reaching higher breakdown voltages using field-plated β-Ga2O3 MOSFET devices.

TCAD-Based Optimization of Field Plate Length & Passivation Layer of AlGaN/GaN HEMT for Higher Cut-Off Frequency & Breakdown Voltage

ATLAS TCAD-based comparative investigation (mainly breakdown voltage, cut-off frequency and leakage current) has been presented in this work for different length of gate field plate and source field plate. 127 V of breakdown voltage has been achieved at 0.25 µm gate length having 0.8 µm gate field plate length and 1 µm source field plate length. By amalgamating source field plate, maximum cut-off frequency of 38 GHz was achieved at 0.25 µm channel length. Passivation layer permittivity and barrier thickness has also been used to optimize the device performance. The improvement in breakdown voltage is less prominent than the deterioration in cut-off frequency with the enhancement in passivation layer permittivity. Leakage current of source field plate HEMT has also been studied for different passivation layer permittivity.

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

In this paper, input capacitance (CISS) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. CISS includes gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD). In comparison with the normally-on HEMTs, it is found that the phenomenon of CISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of CISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of CGS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing CGS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of CGD. Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on CISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the CISS related capacitance design and gate driver optimization of the devices.

Improved Current Collapse in Recessed AlGaN/GaN MOS-HEMTs by Interface and Structure Engineering

Enhancement-mode (E-mode) GaN MOS-HEMTs using recess process typically face the challenge of precise thickness control, surface roughness issue, and interface traps, all of which could lead to the degradation of the device performance and cause reliability issues. In this article, we use a combined process of atomic layer etching (ALE) technique and atomic layer deposited (ALD) HfSiO dielectric. ALE is repeated oxidation and dry etching process with minimal surface damage, leading to a precisely controlled low-damage recess channel area. The fabricated AlGaN/GaN MOS-HEMTs exhibit E-mode operation with a positive threshold voltage ( ${V}_{\text {th}}$ ) of +2.1 V with small ${V}_{\text {th}}$ dispersion for different devices, an ultrahigh drain current ON– OFF ratio over 1010 and a low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $11.5~\Omega \cdot \text {mm}$ at gate-to-drain length ( ${L}_{\text {GD}}$ ) of $25~\mu \text{m}$ . Source field plate (SFP) structure is employed to reduce the charge trapping process and improve the reliability at high voltages. The current collapse of the E-mode device with SFP structure can be effectively suppressed due to the optimized redistribution of the peak electric field in the gate-to-drain access region, where a significantly improved dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of only 1.17 times increase from the static ${R}_{ \mathrm{\scriptscriptstyle ON}}$ after OFF-state ${V}_{\text {DS}}$ stress of 600 V. Moreover, the enhanced vertical electric field with decreased AlGaN barrier thickness and the positive shift in threshold voltage for the E-mode device can effectively suppress the current collapse, which outperforms the depletion-mode counterpart. The breakdown voltage reaches a considerable value of 1560 V at an OFF-state current density of ${1}~\mu \text{A}$ /mm.

Lateral source field-plated β-Ga2O3 MOSFET with recorded breakdown voltage of 2360 V and low specific on-resistance of 560 mΩ cm2

In this letter, lateral β-Ga2O3 MOSFETs with source field plate are fabricated on Si-doped homoepitaxial film on (010) Fe-doped semi-insulating β-Ga2O3 substrate. The drain extension in the source field plate effectively suppresses the peak electric field in the Ga2O3 channel, and improves the breakdown voltage greatly. Moreover, fluorinert FC-770 is used to reduce air breakdown potential during the breakdown testing. The breakdown voltage of the device with Lsd of 28 μm is measured as high as 2360 V, which is the highest value in reported lateral Ga2O3 MOSFET. Besides, Si-ion implantation is adopted to reduce the ohmic contact resistance (Rc). The value of specific on-resistance (Ron,sp) is calculated to be 560 mΩ cm2, which is a recorded value under such high breakdown voltage, and also lower than the theoretical limit of Si-based power devices under the same breakdown voltage.

Analysis of Gain Variation With Changing Supply Voltages in GaN HEMTs for Envelope Tracking Power Amplifiers

Envelope tracking (ET) is a promising power amplifier (PA) architecture for current and future communications systems, which uses dynamic modulation of the supply voltage to provide high efficiency and potentially very wide bandwidth over a large dynamic range of output power. However, the dynamic nature of the supply voltage can lead to a problematic variation in transistor gain, particularly in GaN HEMTs. This paper describes and analyzes this behavior and the detrimental effect it can have on ET PAs. Contributing factors and origins of gain variation are described in detail along with how, for the first time, meaningful comparisons can be made between different devices. Using these guidelines, gain variation is shown to be a widespread issue effecting most GaN HEMTs presented in literature. To allow an analysis of the intrinsic device behavior, an extended transistor model is developed that takes the effect of gate and source field plates into account. This model is refined using measurement data and used to demonstrate the fact that the parasitic gate–drain capacitance ( $C_{\textrm {GD}}$ ) is the main contributor to the small-signal gain variation—a significant part of the overall gain variation. Based on this knowledge, possible strategies to reduce gain variation at the transistor technology level are proposed, allowing the optimization of GaN HEMTs specifically for ET PAs. One identified strategy involves reducing the length of the gate field plate and is shown to be a viable approach to reduce the gain variation in GaN HEMTs, albeit at an increased RF/dc dispersion.

A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 960 V with a superior figure of merit (FOM = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 5.98 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

High Three-Terminal Breakdown Voltage Exfoliated β-Ga2O3 Nanolayer Field-Effect Transistors with Dual Field Modulating Plates

β-Ga2O3 is an intriguing material for high efficiency power devices because of its large direct bandgap (4.85 eV), high breakdown field (~8 MV/cm) and excellent thermal and chemical stability. Baliga’s figure of merit of β-Ga2O3 is 3214.1, superior to those of other materials such as GaN (846.0) or SiC (317.1). Interestingly, although β-Ga2O3 is not a van der Waals material, β-Ga2O3 can be mechanically exfoliated from single crystal substrate into thin layer due to the large anisotropy of the unit cell. The fabrication of high crystal quality β-Ga2O3 nanolayer devices could pave a way for next-generation high-power nanoelectronics devices. In power device operation, the premature electrical induced by the concentrated electric fields limits the device operation under a high bias voltage, and threaten the reliability of devices. Various techniques such as recess gate or field-plate configurations have been proposed to relieve the electric field concentration and prevent premature breakdown. Adopting gate field plate, source field plate, or multiple field plate greatly enhance the performance of power devices, which can be applied to β-Ga2O3 based nanoelectronic power devices that can unlock the full potential of β-Ga2O3. Due to the exceptional mechanical and electronic properties of 2D materials, researches about 2D materials has been at the forefront of this area during the last years. Studies on fabrication of functional devices based on 2D materials, including integration with themselves, are exploding. Among 2D materials, hexagonal boron nitride (h-BN) has been used as a dielectric material of 2D devices due to its excellent thermal conduc tivity (1700 – 2000 W/m∙K) and high dielectric constant (8 – 12 MV/cm), as well as defect-free and atomically flat surface, which can easily be obtained through mechanical exfoliation method. In our work, we used h-BN as a gate field plate dielectric layer by precise and selective transfer on β-Ga2O3 channel by using PDMS film. SiO2 dielectric layer was deposited on devices, followed by metal deposition for source field plate. By applying dual field plate structure β-Ga2O3 based power devices can show excellent performance in high voltage condition than conventional metal-semiconductor field effect transistors (MESFETs). β-Ga2O3 MESFETs with h-BN gate field plate were fabricated by using the β-Ga2O3 and h-BN flakes obtained from respective crystals. Ohmic metal (Ti/Au) was deposited on both end of mechanically exfoliated β-Ga2O3 flakes, followed by precise positioning of exfoliated h-BN flakes on the channel. Top-gate electrode (Ni/Au) was deposited to fabricate β-Ga2O3 MESFETs, with a part of the electrode overlapped with h-BN to achieve a stepped gate field-plate structure. After deposition of SiO2 layer as dielectric layer of source field plate, selective etching of SiO2 layer was performed to construct source field plate structure. Fabricated β-Ga2O3 MESFETs showed excellent n-type DC output and transfer characteristics even after storage for one month in ambient air, which shows excellent long-term air-stability. Three-terminal off-state breakdown voltage of dual field-plated β-Ga2O3 MESFET was measured, which shows improvement in breakdown voltage compared with that of conventional β-Ga2O3 MESFET. The distribution of electric fields was calculated by Silvaco Atlas device simulation framework to study the effect of source field plate and h-BN gate field plate on electric field, which explain the improvement of breakdown voltage in those structure. By adopting dual field plate structure, ease of distribution of concentrated electric field was observed. In this study, we present that the performance of β-Ga2O3 MESFET as a power device can be greatly improved by adopting dual field plate structure, paving a way to the high-power nanoelectronic devices of β-Ga2O3. The details of our work will be discussed in the conference.